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ISCAS 2005
Performance Model for Inter-chip Busses
Considering Bandwidth and Cost
Authors:
Brock J. LaMeres
University of Colorado, Boulder, CO
Sunil P. Khatri
Texas A&M University, College Station, TX.
“Performance Model for Inter-chip Busses”
1
Problem : Packaging Limits Performance
• Transistor Technology is Faster than Package Technology
IC
Package
“Moore’s Law”
- # of transistors will
double every 18 months
“Rent’s Rule”
- # of I/O will double
in next 10 years
“Performance Model for Inter-chip Busses”
2
Outline
• Inductive noise in packaging
• Package performance model
– Relationship with inductive parasitics
– “Bandwidth per unit cost” metric
• Experimental results
– Model versus SPICE
• Conclusions
“Performance Model for Inter-chip Busses”
3
Inductive Noise in Packaging
1) Supply Bounce
• Switching current through inductive packaging induces voltage:
Vbnc
 di 
 L11  

dt


L11 = Inductance of
pwr/gnd pin that
current is being
switched through.
• Multiple Signals Switching Increase the Problem:
 dik 
 L11   

dt

k 1 
n
Vbnc
“Performance Model for Inter-chip Busses”
n = # of drivers
sharing the power/gnd
pin (L11).
4
Inductive Noise in Packaging
2) Pin-to-Pin Coupling
• Switching Signals Couple Voltage onto Neighbors:
Vcouple
 dik 
 M 1k  

 dt 
M1k = Mutual
Inductance between
pwr/gnd pin and kth
signal pin.
• Multiple Signals Switching Increase the Problem:
 dik 
  M 1k  

 dt 
k 1
n
Vcouple
“Performance Model for Inter-chip Busses”
5
Analytical Model
• Bus Parameters
S
S
G
S
S
P
S
S
G
S
S
P
S
S
G
S
S
P
P
S
S
G
S
S
P
WBUS
WBUS : # of signals in the bus
S
NG
S
G
S
S
P
S
S
G
S
S
: # of Grounds in the bus
“Performance Model for Inter-chip Busses”
6
Analytical Model
• Bus Parameters
P
S
S
G
S
S
P
S
S
G
S
S
P
S
S
G
S
S
Repetitive Pattern of Signal, Power, and Ground Pins
SPG : (# of Signals) : (# of PWR’s) : (# of GND’s)
= 4:1:1 in above example
“Performance Model for Inter-chip Busses”
7
Analytical Model
• Bus Performance Description
Slewrate
v(t)
dv
dt
t
 dv   di 
slewrate        Z load
 dt   dt 
“Performance Model for Inter-chip Busses”
8
Analytical Model
• Bus Performance Description
Risetime
90%
v(t)
(0.8)VDD
VDD
10%
t
trise
(0.8) VDD

slewrate
“Performance Model for Inter-chip Busses”
9
Analytical Model
• Bus Performance Description
Minimum Unit Interval
DATA
DATA
DATA
UI
UI min  (1.5)  trise min
1

DRmax
“Performance Model for Inter-chip Busses”
10
Analytical Model
• Bus Performance Description
Bus Throughput
DATA
DATA
DATA
DATA
DATA
DATA
WBUS
Tx
DATA
DATA
Rx
DATA
TPmax  WBUS  DRmax
“Performance Model for Inter-chip Busses”
11
Analytical Model
• Bus Performance Limits
Maximum Acceptable Ground Bounce
pVDD
v(t)
VDD
NOISE
t
Vbnc  MAX  p VDD
“Performance Model for Inter-chip Busses”
(ptypical = 5%)
12
Analytical Model
• Model Development
Maximum Ground Bounce
Vgnd bnc  p  VDD
 Wbus  L11   di  Wbus 
di 

   M 1k 



 N g   dt  k  2 
dt 


Self
Contribution
“Performance Model for Inter-chip Busses”
Coupling
Contribution
13
Analytical Model
• Model Development
Maximum Slewrate
p VDD  Zload
 dv 
  
 dt max  Wbus  L11  Wbus

   M1k
 N g  k 2
- pull out (di/dt)
- convert to (dv/dt)
“Performance Model for Inter-chip Busses”
14
Analytical Model
• Model Development
Minimum Risetime : But since trisemin 
trise min
(0.8) VDD
 slewrate max
 W  L  Wbus

bus
11
 0.8  
    M 1k  
 N g  k  2


p  Z load
- convert slewrate to risetime
“Performance Model for Inter-chip Busses”
15
Analytical Model
• Model Development
Maximum Datarate : Also, since (1.5)  trise min
DRmax 
p  Z load
1

DRmax
 W  L  Wbus

bus
11
1.5   0.8  
   M 1k 
 N g  k  2

- convert Risetime to Datarate
Maximum Throughput : Finally, we have
TPmax  WBUS  DRmax
“Performance Model for Inter-chip Busses”
16
Experimental Results
• Per-pin and Bus throughput values computed for 3
packages
– Compared our model with SPICE simulations
QFP – Wire Bond
BGA – Wire Bond
“Performance Model for Inter-chip Busses”
BGA – Flip-Chip
17
Experimental Results
• QFP Wire-Bond Package Simulations
Per-Pin Data-Rate
Bus Throughput
Model
Simulation
- Throughput reaches an asymptotic limit as channels are added
“Performance Model for Inter-chip Busses”
18
Experimental Results
• BGA Wire-Bond Package Simulations
Per-Pin Data-Rate
Bus Throughput
- Level 1 : BGA Increases Performance Over QFP
“Performance Model for Inter-chip Busses”
19
Experimental Results
• BGA Flip-Chip Package Simulations
Per-Pin Data-Rate
Bus Throughput
- Level 2: Flip-Chip Increases Performance Over Wire-Bond
“Performance Model for Inter-chip Busses”
20
Experimental Results
• Cost Must Also Be Considered in Analysis
Bandwidth Per Cost
 TP 
BPC  

 Costbus 
Units = (Mb/$)
• This Metric Represents “Cost Effectiveness of the Bus”
“Performance Model for Inter-chip Busses”
21
Experimental Results
• Bandwidth Per Cost Results
Faster Narrower Busses = More Cost Effective
“Performance Model for Inter-chip Busses”
22
Conclusions
• Presented a model for bus performance
– Accounts for inductive parasitics in packaging
– Developed a “bandwidth-per-unit-cost” metric to evaluate packages
• Experiments indicate
– Strong agreement with SPICE simulation
– Throughput for a bus reaches asymptotic limit as channels added
• Increase in channels compensated by decrease in per-pin throughput
• Optimal number of channels is small (4-8)
• “Bandwidth-per-unit-cost” experiments indicate
– Flip-chip packages are actually most cost-effective
– Narrower buses have better bandwidth-per-unit-cost
“Performance Model for Inter-chip Busses”
23
Thank you!
“Performance Model for Inter-chip Busses”
24
Backup Slides
“Performance Model for Inter-chip Busses”
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Example
PACKAGE
On-Chip
- 8 bit Data Bus
- 300 Mb/s
- Rent’s Rule
IC Core
- Moore’s Law
Package
- Need
(8)(300M) = 2400 Mb/s
“Performance Model for Inter-chip Busses”
26
Example
Need:
2400 Mb/s
X
X
X
X
QFP – Wire Bond
BGA – Wire Bond
BGA – Flip-Chip
- 4 bits wide, SPG=2:1:1
- 1 bit wide, SPG=2:1:1
- 16 bits wide, SPG=4:1:1
- 1 bit wide, SPG=2:1:1
- 1 bit wide, SPG=4:1:1
- 1 bit wide, SPG=8:1:1
“Performance Model for Inter-chip Busses”
27
Example
• Cost of Each Bus Configuration
Most Cost Effective:
- BGA-WB
- Wbus = 1
- SPG = 2:1:1
“Performance Model for Inter-chip Busses”
28
Experimental Results
• Cost per Bus Configuration
$
• Performance Increases with Cost (Package, SPG)
“Performance Model for Inter-chip Busses”
29