Download Fuzzy Logic Controller

LABORATOIRE
DE
BATIMENT MAXWELL
B-1348
MICROELECTRONIQUE
LOUVAIN-LA-NEUVE BELGIQUE
An Approach to the Design of
Analog Fuzzy Logic Controllers in CMOS Technologies:
Implementation, Test and Application
Carlos Dualibe
UCL- June 2001
1
FUZZY LOGIC:
Formalism for codifying Human Reasoning
within a Numerical Framework.
FUZZY SYSTEM:
Model-Free Universal Approximator.
Structured Knowledge Base (“if-then” rules)
Usefulness: To solve problems that are either difficult to tackle mathematically or
where its use provides improved performances and/or
simpler implementations.
Engineering Applications :
(examples)
-Process and Environmental Control
-Robotics and Automation
-Automotive Industrial Applications
-Signal and Image Processing
-Power Electronics
-…………
UCL- June 2001
2
Hardware Implementation Choices for Fuzzy Controllers
Allocation of the applications in the
space [Complexity ; Time Response]
Systemresponsetime
m
s

s
E
xper
t
S
ys
em
t
s
M
echani
cal
S
ys
em
t
s
s
8bm
i
ti
cr
ocont
ol
r
er
s
M
cr
i
om
echani
ca
l
S
ys
em
t
s
m
s
Systemresponsetime
s
Allocation of hardware solutions in the
space [Complexity ; Time Response]
E
ect
l
oni
r
c
S
ys
em
t
s
16bi
m
t
cr
i
ocont
ol
r
er
s
32bi
m
t
cr
i
ocont
ol
r
er
s

s
G
ener
al
P
ur
pos
eP
oces
r
or
s
w
hf
t
i
uzzys
uppor
t
F
uzzyC
opr
oces
or
s
ns
ns
10
100
1000
C
om
pl
exi
y(
t
uzzyr
f
ul
es
)
D
edi
cat
edA
S
C
I
s
10
100
C
om
pl
exi
y(
t
uzzyr
f
ul
es
)
1000
a)
b)
Intended Target Applications: Signal and Image Processing, Power Electronics
UCL- June 2001
3
Why Analog?
•Fuzzy Processing is analog in ‘nature’.
•Usual applications demand reduced accuracy.
•Low Power and/or High Speed
•Reduced Complexity: Small area – No need of A/D and D/A
to interface Sensors and Actuators
•Ideal for Embedded Subsystems.
Main Goals of this Work
•Comprehensive study of the Analogue Fuzzy Operators
•Design and Test of Programmable Architectures for Analogue Fuzzy Controllers
Secondary Goal:
•To undertake preliminary studies of an embedded Fuzzy Logic application
in the field of Signal Processing.
UCL- June 2001
4
Fuzzy Controller Architecture and Fuzzy Algorithms
Ante cedentpartofthe rule s
Cons equentpartofthe rule s
T -N o rm = M in

TAKAGI-SUGENO

C
 
1 = a
z
1 x * + b
1 y * + c
1
R1:
Building Blocks:
M
AM
DANI

C

w1
z
•Membership Functions
x
•T-Norms ; T-CoNorms

 
C 2
R2:
•Consequents
2 = a
z
2 x * + b
2 y * + c
2
C 
2
w2
•Defuzzifiers
Inputs
y
z
x
x *
y
y *
IN P U T S
z
*
z
Fuzzification
Interface
Decision
Making Unit
Defuzzification
Interface
Outputs
Suits optimal for Hardware
Implementation !
Fuzzy Controller
UCL- June 2001
5
Membership Functions Circuits: -Trapezoidal Shapes Based on Triode Transconductors
TYPE –I: Differential Regulated Cascode Triode Transconductor
Transfer Curve: Slopegm
CrossoverVk
Non-Symmetric Diff.
Amp. DA1,DA2
Circuit : M1, M2Triode
(W/L)Md1 > (W/L)Md2
I2
I1
Mc1
Vdd
Mc2
Vs
I[

A]
Md5
Io
DA2
DA1
Ip
Vin-
Vds
Vds
M2
Md2
Vout
g
t α
2
Io
2
V
Md6
Vin
I1
Vin+
Md1
M1
I2
Io
Md3
Md4
Vk

Vk
Vin[
W
gm  μCox  
Vds
 L  M1-2
 (W/L)

(W/L)
M d5
M d5 

Vdd - VTp  Vs
Vds  Vin  Vin 

 2 (W/L)

2 (W/L)
M
d2
M
d1


-

UCL- June 2001
6
Membership Functions Circuits (2):
TYPE –II: Single Regulated Cascode Triode Transconductor
Transfer Curve:
Circuit : M1Triode
M2 Saturated
Slopegm
KneeV2=Vk + n Vds/2
1
I
gm
M
<
1<
gm
M
2
M
1
c
1[
I
A
]
V
dd
o
I
D
A
2
I
M
1
1
I
M
2
Vds
V
t
g
=
gm
M
1
V
n
i
o
I

V
k
V
1
)
a
V
2V
3
o
I
gm
M
1
V
4V
n[
i
V
]
b)
M2: Large size transistor aimed for
setting a conduction threshold
n = Subthreshold slope factor
UCL- June 2001
7
Membership Functions (3) : Four Independent Parameters  2 slopes (gm1, gm2); 2 Crossover (Vk1 , Vk2)
Iout1
Iout2
gm2
gm1
Vk1
Vin
Io
o
Iu
1
t
o
Iu
2
t
2
I
o
3
I
o
2
o
I
o
I
2
gm
1
2
V
k
1
gm
1
2
gm
2
2
o
I
gm
2
2
V
k
2
Complementary FMF
a
)(CFMF)
Vk2
Io
V
n
i
UCL- June 2001
V
k
1
Direct b
FMF
)
V
k
2
V
n
i
8
Membership Functions Circuits (4): Comparison against saturated transconductor
i+ i-
vi+
Io
vi-
Analogue Programming: Electrically Tunable Slopes by setting Vds
Discrete Programming: large slope range is optimally allowed by a set of (W/L)s:




W/L max    gm max 
W/L min   gm min 
 W/L max

 W/L 
min

Triode
  gm max

  gm
 
min




2
Saturated
Small Slopes can be set by using small Vds rather than very long channel Transistors
Increased Current Consumption (Differential Amplifiers at the Regulation loop)
More sensible to Mismatch (Triode transistors Vds)
UCL- June 2001
9
Membership Functions Circuits (6): Full Programmable Compact Fuzzy Partition
(Based on [1])
V
dd
5
I
V
dd
3
I
4
I
V
s
4
V
s
3
V
k4
V
dd
2
I
1
I
V
s
2
V
k3
V
s
1
V
k2
V
k1
o
I
V
n
i
SlopesVs1,…Vs4 - Crossover points  Vk1<Vk2…<Vk4
SPICE simulation for a 7-label
Circuit: Io= 10A, Vdd=5V
Reduced number of transconductors
Reduced Current Consumption
Cumulative mirroring errors and delay due to cascading
[1] Willamosky B. et al, ANNIE’96
UCL- June 2001
10
T-Norm and T-CoNorm circuits: General Requirements
In1
T-Norm
Out
or
InN
• Multiple inputs
T-CoNorm
(N)
• O(N) Complexity:
 Size and consumption proportional to N
• Parallel Processing:
 No cascade tree of binary operators
• Inputs Transparency:  Same load at each input - Same input/output delay
Circuits: - Improved Lazzaro’s WTA-MAXIMUM
- Mixed-Mode O(N) MAXIMUM
- O(N2) LTA-MINIMUM
- O(N) LTA-MINIMUM
UCL- June 2001
11
T-Norm and T-CoNorm (1): Lazzaro’s WTA-MAXIMUM
V
d
d
IN
V
d
d
I1
M
1
M
1
IN
I1
M
1
M
2
M
2
M
1
M
c
V
b
as
i
M
c
M
o Im
ax
M
2
M
2
M
c
Im
ax
M
o
Improved Version
a)b
)
Concept
Systematic Errors: ~1.6%
•N current-controlled voltage-sources ( M1, M2 ) ‘fighting’ in parallel
• Propagation error   Early effect in M2 ( Mo)
• Discrimination error:   Early effect in M2 -  inversion degree of M1
• Mismatch error:  VT and  of M2, Mo
UCL- June 2001
12
T-Norm and T-CoNorm (2): Lazzaro’s WTA-MAXIMUM
Delay & Undershot Improvement!
E
M1
E
E
Imax
M1 MOST
Ids
I1=5A
Vt
I2=pulse 3A to 7A - 100ns
Vgs
0
UCL- June 2001
Emax
13
T-Norm and T-CoNorm (3): Mixed-Mode MAXIMUM
M
p
c
o
I
u
=
t
M
A
X
1
I
(
IN
.
)
C
V
d
d
M
1
M
p
M
2
A
1
2
M
p
M
2
M
1
V
+
M
n
1
I
I m ax_1
d
I
d
I
A
M pc_1
V
M
n
M
s
V
o
u
t
N
I
M1
M AX_1
RULE_1
N
Ii
CFM F
M
n
c
Q
I
p
I
M pc_k
I m ax_k
1
2
M AX_k
WI RE
RULE_k
N
Systematic Errors: ~2.3%
•Set of N Source Followers ‘fighting’ in parallel
Distribution of Input Signals
•Propagation error:   Voff = offset of A
achievable in voltage-mode !!
•Discrimination error:   Ao = DC gain of A
•Mismatch errors:  due to Voff mainly
UCL- June 2001
14
T-Norm and T-CoNorm (4): New O(N2) LTA-MINIMUM [2]
V
dd
M
p4
1:
1
1:
1
M
p5
1:
1
M
p2 1:
1
V
dd
M
p6
M
p4
1:
1
V
1
M
p1
V
o
1
I1
M
n1
M
p3
V
4
I1
M
n2
V
3
1
M
p21:
Im
n
i
I2
M
p6
V
2
M
p3
V
o
2
1
M
p51:
M
c
V
o
u
t
I2
M
n2
M
n1
a)b
)& MINIMUM
2-Input LTA
Im
n
i
M
c
2-Input MINIMUM
Systematic Errors: ~3%
• Parallel comparison between
input currents -Vdd limits the number of inputs
•Propagation error:  Due to the Early Effect in transistors Mp
•Discrimination error :   with the impedance of internal nodes (i.e.: V2)
•Mismatch errors:  Associated with mirrors Mn and Mp
[2] Dualibe, Jespers, Verleysen,
IEEE ISCAS’2001
UCL- June 2001
15
T-Norm and T-CoNorm (5): New O(N) LTA-MINIMUM [3]
C
el
i
C
el
i
-
V
dd
i
I
C
om
m
onC
el
op
I
M
p
V
dd C
om
m
onC
el
i
I
op
I
M
1
V
2
M
pc
V
1
N
c
M
1
M
2
m
In
i
M
2
on I
I
oi
N
c
M
3
V
oi
M
n
a
b
)
c
)
)
Concept
m
In
i
M
4
M
M
3
M
4
N
b
oi
on I
I
V
4
M
n
M
5
i
I
V
5
M
6
Improved Version with current feedback
Ii Mirror
• N current-controlled voltage sources (Cells-i) ‘fighting’ in parallel
• Current feedback improves accuracy of the MINIMUM (~ enhanced Wilson mirror)
•Systematic error (~0.4%)
•Mismatch error: due to VT and  of M5, M6
[3] Donckers, Dualibe, Verleysen,
IEEE ISCAS’2000
UCL- June 2001
16
Defuzzifiers : Closed Loop Defuzzifiers
ngl
i
s
on
t
e
ngl
i
s
on
t
e
I
1
TNor
m
FM
F


G1
I
1
I
1
out
I
=i
I
i

αG
V
G
m

 I
m
m
Gm
I
m
m

I
αI I
I
m
G=
io
f
;
)
i
I
(=
i
r 1.m
.
Voltage mode
b)
a
)
• Complexity increases with the
number of rules
• May need frequency compensation
due to feedback:  speed
αI
I
o=I
I
=c ons
i
nt
a
t
Fe e
dba
kc ont
c
ol
r
node
Current mode
• FMF or T-Norms’ gain must be controlled
•May need frequency compensation
due to feedback:  speed
UCL- June 2001
17
Defuzzifiers(2): Open Loop Defuzzifiers

 m
I
1N
in
s gle ton
I
1
mI
mN


out=iI N
I

I
m
I
mN
I
1N
R1
I
m
o
I
=I
i N=Cons
ta nt
I
eudo-Normalizer
DI V Vo
m
Rm
iI

I
i

αI
V

I
Divider
a)
b)
ty may increase with the
rules (i.e.:R1….Rm)
•Only one extra mirror per rule
to compute denominator
UCL- June 2001
18
Defuzzifiers(3): Open Loop Defuzzifier with Divider
‘Common Weighting’ strategy for digitally programmable
singletons.
toDI V(  )i
Def uzzif ie r
T- Nor ms
toD/A

I1
i
Ii
irors
(n+1)Curr.M
1
:
1
:
1
:
1
:
1
C1o
C1n-1
n- mir r or s
Vdd
/
DA
m
Im
irors
(n+1)Curr.M
Cmo
Cmn-1
2:1
2n:1
4:1
/
DA
α I
 I
toDI V(  i )i
DI V.
Vo
• ‘n’ mirrors
per singleton
•Silicon surface and input
capacitance of each
singleton result much
smaller than in the ‘local
weighting’ approach (i.e.:
(2n/n) times reduced)
•Only one D/A- Can be
i i
optimized
to
get
desired
i
accuracy
•Simplicity
UCL- June 2001
19
Defuzzifiers(4): Novel Two-Quadrant Analog Divider [4]
Vdd
•
M7
M1= M2=M3triode

Input Nodes Nd and Nn become resistive!
M9
M8
IN
ID
M4
Thus:
M6
M5
Nd
I1
Vb1
I2
I3
Vbo
M1
Vout
M2
1
:
Nn
1
Vout-Vbo= (Vb1-Vbo) (IN/ k ID)
•Current/input voltage/output IDEAL!
M3
:
k
•Systematic errors: - Mainly due to mobility reduction in triode transistors M1, M2, M3.
- Gain error and offset can be neglected if cascoded PMOS mirrors
are used (M7, M8, M9).
•Mismatch errors: -For small current ID, strongly influence of mismatch of VT between
transistors M4,M5,M6.
[4] Dualibe, Verleysen, Jespers, IEE
Electronics Letters, 1998.
UCL- June 2001
20
Defuzzifiers(5): Two-Quadrant Analog Divider-Measurement
(+) Measured
D
I
=
0
1

A
relativo
(Vout-Vbo)[V]
(-) Calculated
N
I=
8

A
D
I[

A
]
N
I[
A
]
b
)
a
(Vout-Vbo) vs. IN:
Relative errors vs. ID:
0< IN <10A; 10A< ID <30A
2 A < IN < 8A; 10A< ID <30A
Non-Linearity: NL 
maximum deviation
100%  ~ 1%
maximum output swing
UCL- June 2001
21
Defuzzifiers(6): Comparison Against other Dividers
Wiegerink R., Kluwer A. P., 1993
Iout  Iout1  Iout2 
IxIy
2IB
• Inputs must
be supplied at different nodes
at least twiceAdditional mirroring errors
•NL = ~1%
Huertas et al, Trans. Fuzzy Systems, 1996
Vo  V1  V2 
β'
Ia - Ib
(v1  v2)
β
Ic - Id
• Need
extra I-to-V converter
•Differential currents inputs
•NL = ~1% (only divider)
Current-to-voltage converter
Divider
UCL- June 2001
22
Defuzzifiers(7): Electrically Programmable Singletons
V
dd
M
8
M
7
M
9
1:
B
M
11
n
i
I
M
5
M
4
V
b1
out
I
V
bo
M
1
M
10
M
6
V
b2
M
2
M
3
Iout  B
(Vb2 - Vbo)
Iin
(Vb1 - Vbo)
1
:
1
:
1
New Electrically
Tunable
a)
b)
Linear Current-Mirror
Spice Simulation: 1V<Vb2<1.5V
Other Approach:
Iin
Sasaki et al, 3th
Int. Conf. On
Industrial Fuzzy
Control and
Intelligent
Systems
1993
Vref1
Vc1
Iout
Vc1
Vc2
M1
Iout 
Vc2
βM2 (Vref2 VTn)
βM1 (Vref1 VTn)
Vref2
M2
UCL- June 2001
23
Iin
Estimation of the global accuracy of the Controller
Consequent + D/A
IN
Vin
CFMF
Iout
f1
fo
σ
2
Vout
 a div σ
2
div
T-Norm
 a cons D/A σ
2
cons D/A
Divider
Mirror 1:1
 a mirror σ
Vout
f3
Iout1
ID
f4
f2
2
mirror
 a T - Norm σ T2 - Norm  a Io σ 2Io  a FMF σ 2FMF
Only One Fired Rule: 2% < Vout/Vout <3%
Unrealistic!
Divider
Singletons +D/A
Mirror
Vout
b)
)
a
UCL- June 2001
%
24
Estimation of the global accuracy of the Controller(2)
Two Fired Rules in a complementary way: 2.5% < Vout/Vout <3.5%
w
F

S

Z
u
S
M
B
Vout for: 0.1< 1 < 0.9
b)
)
a
25
2=0.9
%: (+) Divider
UCL- June 2001
25
(o) CFMF+T-Norm+Io
Programmable Fuzzy Architectures: General Guidelines
• Standard CMOS Technologies Mixed Signal :  Analogue Processing + Digital Programming
• Current-Mode vs. Voltage-Mode:
Current Mode
Voltage Mode
Analog Computation:…………. +
-
Signal Routing…….:…………..-
+
Chip external Interface:……….. -
+
MIXED MODE
• Building Blocks Interface: Avoid the use of extra V-to-I or I-to-V convertersImproves Delays and
Accuracy.
• Modularity:
Share operators (i.e: Membership Functions Circuits, Common weighting)
•Transistors Sizing: Large size Good MatchingPoor Integration Density (dedicated controllers)
Small size Poor MatchingGood Integration Density (programm. controllers)
Programmability can help to relax sizing requirements for a given accuracy!
UCL- June 2001
26
A 9-Rule 2-Input 1-Output Programmable Fuzzy Controller [6]
Fuzzif
ie rs
&
Rule s Set
Rule s Evaluat
ion
Def
uzzif
ie r
Digita
lbus
or
f
ingle
s
tons
pr
ogr
mming
a
Vin1
s ingle t
on
CF
M
1
F
CF
M
2
1
F
CF
M
3
1
F
_
Io
+
M
AX
I1
2
1

n+1)
(
Cur
.mir
r
or
1:1)
(
s
Cn1
Co
Io
2
M
AX
CF
M
1
2
F
CF
M
2
F
Digita
lbus
or
f
CFM
Fs
pr
ogr
mming
a
_ +
I9
9

n+1)
(
Cur
.mir
r
or
1:1)
(
s
CF
M
3
2
F
Vin2
DA
/
i*I
i
I
i
•Zero-Order Controller-Fixed Number of Rules (Grid Partition)
•Complementary MF Labels (Type II – Three per input)
• T-Norm: Complemented Lazzaro’s MAXIMUM
•Defuzzifier: ‘Common weighting’
•Discrete Programming of Antecedents and Consequents
•Intended for embedded applications
[6] Dualibe, Jespers, Verleysen,
IEEE ISCAS’2000
UCL- June 2001
DV
I
Vo
27
9-Rule Fuzzy Controller (1): Membership Function Programming
Vdd
Vdd
Vs1
Ms1
Linear Resistor
Mp2
s0
S2
S3
Vin
s1
s2 s3
Mp1
Is
Iout
Is 2Is
Is
M1_0 M1_1 M1_2
Vdd
Mc1
Vdd
Vs1
DA1
MR2
MR1
Vk
MR3
R
M2
M1
V
p0 p1
Vin
Io
p2 p3
p4
Vk
Ip
Ip 2Ip
4Ip 8Ip 16Ip
•Measured CFMF Type-II:
•Io=10A ; Vdd=5V
Half CFMF Type-II
•Input Range: 1.5V<Vin<4.5V
•Local setting of analog parameters
•s0…..s3Slopes (2x4-bit)
•p0….p4Knees (2x5-bit)
UCL- June 2001
28
9-Rule Fuzzy Controller (2):Test Result
TARGET
Relative Error Surface
MEASURED
Relative Error Distribution
Settling time (90%):
RMSE
_max
Mean()
S.Signal: ~190ns
L.Signal: ~450ns
27mV
(2.7%)
62mV
(6.2 %)
35mV
(3.5%)
UCL- June 2001
29
9-Rule Fuzzy Controller (3):Comparison
[KeSc93]
Complexity
[MaFr96]
[GuPe96]
[BaHu98]
[VaVi99]
[DuVe00]
9rules@2input 9rules@2input 13rules@3input 9rules@2input 16rules@2input 9rules@2input
@1output
@2output
@1output
@1output
@1output
@1output
3 Bi-CMOS
0.7 CMOS
2.4 CMOS
2.4 CMOS
1 CMOS
2.4 CMOS
no data
44mW@5V
550mW@10V
20mW@5V
8.6mW@5V
13.4mW@5V
no data
550ns
160ns
2000ns
471ns
450ns
Precision
no data
RMSE: 3.33%
no data
no data
MAX: 4%
MAX: 6.2%
Interface
currents@
voltages@
voltages@
voltages@
voltages@
voltages@
currents
voltages
voltages
voltages
currents
voltages
2
2
2
Technology
Power
Consumption
Input to Output
Delay
(inputs@outputs)
13.75mm
1.9mm
16.2mm
1mm
1.6mm
4.5mm2
MF Knees:
fixed
on chip (6b)
off chip
on chip (6b)
off chip
on chip (5b)
MF Slopes:
fixed
fixed
on chip (4b)
on chip (2b)
fixed
on chip (4b)
Consequents:
fixed
on chip (6b)
off chip
on chip (4b)
on chip (4b)
on chip (5b)
Area
2
2
Programmability
UCL- June 2001
30
Application Example: Fuzzy Control of a DC/DC “Buck”
Converter[9]
L
Q

RL
IL
Vin
Vout
C

IL
Dp
D
PWM
Vout

E
t

Di
0

Vref

PWM “duty cycle”: D(t)  Dp(IL(t), E(t))   Di E(t) dt
Dp, Di: Highly Nonlinear functions
Small Steady-State Error and Fast Settling Time for RL Changes
([9] Franchi E. et al., IEEE JSSC, June 1998) UCL- June 2001
31
Application Example(2): Fuzzy Control of a DC/DC
“Buck” Converter[10]
Optimal Control Surfaces
DP: 2 Inputs-1 Output
4 Rules
DI: 1 Input-1 Output
4 Rules
([10] Rashid M., Power Electronics-Circuits, Devices and Applications,
Prentice Hall, 1993)
UCL- June 2001
32
A General-Purpose Programmable and Reconfigurable Fuzzy Controller
CFM
Fs
Ba
nk
s
Switc
hM
trix
a
T-Norms
N
Q
M
AX1
M
AX2
-
C F M F -1
C F M F -2
Single
tons
Co
lumns


 

Q


Q
C F M F -3
Cons
que
e
nt
Pa
me
ra
trs
RAM
Ante
de
c
nt
Pa
me
ra
trs
RAM
C F M F -F
M
AXM
-




Q
D /A 1 D /A 2
D /A Q
Con
figura
tionRAM
Vin
1Vin
2
Vin
N
N  5; Q  3; M  27; F  16
INPUTS
•CFMF type-II
•Programmable MAXIMUM mixed mode O(N)
UCL- June 2001
•SWITCH MATRIX: ‘smartly’ wired
D iv
2
D iv
Q
D iv
1

V01Vo2 VoQ Firs
t-Orde
rOUTPUT
Ze
ro-Ord
OUTPUTS
e
33
General-Purpose Controller (2): First-Order Output Configuration
Single tons Column0
Single tons Column1
Vdd
Single tons Column2
IN
ID
R
ule-i
a0i
a1i
D
/A
_0
D
/A
_1
V
bo
V
b1
a2i
V
in1
M-R
ules
D
/A
_2
Divider
V
in2
D
iv_0
D
iv_2
D
iv_1
s w1
Vout
Vbo
Vb1
s w2
Vdd

ID
V
out0
V
out1
V
out2
Q:1
1:1
Q:1
1:1
V
out
Q:1
Ci  a0i  a1i Vin1  a2i Vin2; for i  1...M
Consequent Rule-i
 M a2i Ii 


1
1
1
1





  Vin2
Vout  M



Vin1

M
M
M





 Ii   Ii    Ii 
  Ii 
1
 1
  1

 1

M
Defuzzified
Value

M
 
M
IN

 Ci Ii   a0i Ii    a1i Ii 
UCL- June 2001
MiQ
VQ
Mi2
V2
Vout
1:1
Vbo
Mi1
V1
Novel High-Input Impedance Voltage
Mode Adder:
Q
(Vout  Vbo)  IN  (Vi  Vbo)
ID i1
34
General-Purpose Controller (3): Zero-Order Test Result
Rules Map
Measured Surface
Relative Errors
a)
b)
Surface
RMSE
_max
Mean()
Settling time (90%):
S.Signal: 570ns
a)
80mV (4%)
180mV (9 %)
64mV (3.2%)
b)
94mV (4.7%)
240mV (12 %)
75mV (3.75%)
UCL- June 2001
L.Signal: 1100ns
35
General-Purpose Controller (4): 4-rules First-Order Controller Test Result
Measured CFMF
b)
a
)
Measured Surface
ANFIS Fitting: A comparison
•1st-Order; 4-rules
•Zero-Order; 4-rules
)
c
•Zero-Order;
9-rules
•28 parameters
•20 parameters
•33 parameters
•RMSE: 0.8%
•RMSE: 2%
•RMSE: 1.4%
)
b
)
a
UCL- June 2001
36
Technology
COMPARISON
Processing Mode
[FaMa94]
[FrMa98]
Our Approach
0.8 CMOS
0.7 CMOS
2.4 CMOS
Sampled Time
Continuous Time
Continuous Time
Mamdani:
32rules@8input
Complexity
Vdd=5V
Vdd=5V
Vdd=5V
no data
44mW (2.93mW/rule)
63mW (2.33mW/rule)
~2S
~600ns
~1.1s
Accuracy
no data
RMSE < 3%
RMSE < 4.7%
Interface
digital@
voltages@
voltages@
(inputs@outputs)
digital
voltages
voltages
Input Range
8-bits
2V
3V
8
Output Range
6-bits
2V
2V
11
Area
70mm2
33mm2 (2.2mm2/rule)
39.5mm2 (1.4mm2/rule)
MF Crossover:
on chip(8b)
on chip (6b)
on chip (5b)
MF Slopes:
on chip(5b)
fixed
on chip (4b)
Consequents:
on chip (6b)
on chip (6b)
on chip (5b)
Total storing capacity
needed
~3200 bits
16000 bits
909 bits
4
5
6
Power
Consumption
Input to Output
Delay
2
7
1
12
10
27rules@5input
@1output (max)
Power supply
13
15rules@3input
Zero and First-Order Sugeno:
@4output
(max)
3
9
Zero-Order Sugeno:
13
@3output (max)
Programmability
UCL- June 2001
37
General Purpose Controller (6):Further Improvements
•Scaling to Modern Technologies:
A) Analog Circuits:
Silicon Area
Same Current
Cox
Early
AVTo
CMOS 2.4
50 A/V
10V/
24mV 
CMOS 0.8
100 A/V 10V/
12mV 


Id  1 (u Cox)  W  Vgs - VTo 2
2n
 L
Same Vdd, VTo
2
2
-Same L (keep same Early)
-W  W/2 ===>50% Area Reduction
Mismatch
A*2
A2
A2
1
1
2
VTo
VTo
VTo  50% Mismatch Improvemen t!!
σ



VTo
WL
4
2 WL
W*L
2
B) Digital Circuits: theoretical scaling factor: (1/9). Let us assume (1/4.5).
Total Area Reduction: 39.5mm2 == 13.6mm2
UCL- June 2001
38
Time-Domain Signal Analysis Using Fuzzy Logic and its
Application to Self-Adaptive Channel Equalization
S
)
t
(
y
~
S
)
(
t
F
e
a
u
t
e
r
s
E
x
a
r
t
c
o
i
t
n
R
e
e
f
e
r
n
c
e
P
a
e
t
n
r
x
~
t
t
S
g
i
n
a
l
s
s
e
o
i
t
r
n
s
F
u
z
z
yA
D
e
c
s
i
o
i
n
M
a
k
n
i
g
2
D
F
g
i
u
e
r
F
u
z
z
y
n
I
e
f
e
r
n
c
e
S
y
s
e
t
m
General Setup
Built-in ‘Oscilloscope’: inferred Assertions could be used for adaptation,
detection, testing, etc.
UCL- June 2001
39
Continuous-Time Self-Adaptive Equalization based
on the Eye-Pattern [8]: System Architecture
A)
E(s) = (s-z) (s+z)
Adaptive Equalizing System
• On-Chip Real-Time Scope: 
B)
Control Surface related to the Eye Pattern
SIGNAL 2D-FIGURE (EYE PATTERN)
•Controller’s Decision Making : “Keep ACTUAL EYE within AREA TOLERANCE”
•Controller’s Output:

[8] Dualibe, Jespers, Verleysen,
IEEE ISCAS’2001
EQUALIZER’S ZEROS PLACEMENT
UCL- June 2001
40
Fuzzy Logic Controller : Rule Base and Input Partition
P
PB
Vs
R5 R10
R4 R9
R15
R14
R20R25
R19R24
Z
R8
N
R23
R2 R7
NB
R3
R1 R6
R11
NB N
Z
Boosting must Increase
R13
R12
R18
R17R22
R16R21
P
Vt
PB
Area Tolerance
Boosting must Decrease
•RULE BASE: 25-Rules controlling Equalizer Amplitude Boosting (5-labels per input)
•Area Tolerance: immunity to NOISE, RINGING, PULSE SHAPE, ETC
UCL- June 2001
41
Architecture of the Fuzzy Controller
NB
Vs
T-Norms
N Z P
MIN
MIN
MIN
MIN
PB
Defuzzifier

I1
(n+1) Curr. Mirrors (1:1)
Co
Cn-1
Fuzzy
Partition
Circuits
NB
N Z P
PB
I25
25
(n+1) Curr. Mirrors (1:1)
Co
Cn-1
D/A
Vt
 Ii
Div.
 αi  Ii
Vo
•Zero-Order Sugeno :25 rules
•Fuzzifiers: 5-Labels per input.
•T-Norms: 2-input MINIMUM (O(N2) )
•Defuzzifier: Averaged Weighted Sum
•Discrete Programming of singletons (5-bits)
UCL- June 2001
42
5-Labels Fuzzy Partition Circuit
Vdd
IPB
IP
Vk4
IZ
Vk3
IN
INB
Mb
Vk1
Vk2
Ma
Mc
Vin
Io
Vin
SPICE simulation for Io=10A
•Chained differential pairs: low consuming, small area and compactness
•Vk1<Vk2<…..<Vk4 fix the crossover points
•Fixed slopes at mask level by transistors Ma size
UCL- June 2001
43
Fuzzy Controller Test Results
Fuzzy Logic Controller
Measured
Technology:
CMOS-2.4
Complexity:
25-Rules;
2-inputs; 1-output
Power Supply:
5V
Power
Consumption:
4.4mW
Area:
RMSE:
Analog: 2.9 mm2
Digital: 1.1 mm2
4.5%
Input/Output Delay S. Signal: 380ns
(90% Steady State): L. Signal: 900ns
Target
UCL- June 2001
44
Fuzzy Controller: Improvement
Vs
R1
R3
R2
R4
R5
R6
R7
R8
R9
R10
R11
Vt
•Use Tree Partition for the input space to minimize rules set  ONLY 11 Rules
•Input Vs Compact 5-Label Fuzzy partition circuit
•Input Vt Six individual Membership Functions
UCL- June 2001
45
Amplitude-Boosting Gm-C Filter
Bi-Quad Filter:
Vout
A)
Amplitude
gm3
gm4
Vin
gm5
gm2
gm1
C2
C1
Phase
•gm1=gm3=gm5=gmmaxfix
•gm2=gm4tunable up to gmmax
Symmetric Zeros at:
 gmmax 
z1, z2   Kz 
 ; with
 C1C2 
Kz 
gm4
gmmax
Theoretical Frequency Response
UCL- June 2001
46
New Full Electrically Tunable Triode Transconductor [9]
V
dd
B
1
:
M
6
1
M
15 M
14
z
I
o
Iut
-
M
7
M
8
V
dd
1:
B
M
9
M
1
M
10
out
I
+
M
13
M
7
M
5
M
4
V
ni
M
12
M
1
V
b1
V
bo
M
4
V
b1
V
bo
M
1
M
2
M
3
V
n+
i
V
ni
+
gm
- +
V
dd
V
dd
o
I
o
I
V
C
M
M
e1 M
e2
out
I
+
V
bi
asal
M
al
1
M
al
3
o
I
M
al
4
a)
[9] Dualibe, Jespers Verleysen
IEEE ISCAS’2001
M
3
V
out
•Phase error < 2°
CMFB with adaptive Bias Io [10]
Improved common-mode
voltage stability upon tuning.
M
e7
M
e5
V
C
M
cnt
M
al
2
•Linear tuningIz
V
out
+
M
e3 M
e4
V
out
+
o
I
o
I
1 k B Iz
2 (Vb1 - Vbo)
Divider:
b)
V
out
-
V
out
-
gm 
1:
1:
k
Transconductor:
a)
IL
M
6
M
5
k:
1:
1:
k
out
I
-
M
9
N
I
+
I
V
n+
i
M
2
Transconductance:
D
I
M
6
I
M
8
CMFB
M
e8
M
e6
b)
UCL- June 2001
47
[10] DeLima, Dualibe, IEEE ISCAS’2000
Equalizing Filter Test Results
BiQuad Gm-C filter
Technology:
CMOS-2.4
Power Supply:
5.5V
Power
Consumption:
22.6mW (nominal)
(Iz=25 A )
Area:
5.3mm2
Max. Boost :
30dB (@7Mhz.)
Tuning range:
15A< Iz < 35A
Measured AC Response
UCL- June 2001
48
Cable Equalization (simulations)
A1)
a) b)
Signals for L=360m
Fs = 5Mb/s
A2)
B1)
Kz evolution for
L=120, 240, 360m
B2)
Eye Pattern: before and after the equalizer
Cable: CAT5 UTP
UCL- June 2001
49
Adaptation Performance for Noisy Channels
Kz Evolution during adaptation
a)
b)
Our Approach
Widrow [85]
Noise: Mean=0 -Variance=0.03
UCL- June 2001
50
Self-Adaptive Equalization: Conclusions
Fuzzy Logic
Controller
•Robust Adaptive Equalization: Area Tolerance
filters out noise, ringing, etc.
•Fuzzy Logic Allows easily the Analog
Implementation of highly non-linear control
functions.
Equalizing Filter
•Time-Domain Signal Analysis using Fuzzy
Reasoning = On-Chip ‘Oscilloscope’ 
Applications beyond Channel Equalization topic:
………detection, on-chip analog testing, etc
UCL- June 2001
51
CONCLUSIONS: Fuzzy Logic & Non-Linear Analogue Design
•Systematic Approach for Analogue Non-Linear Synthesis.
•Very Easy to Understand!
•Available Optimization and Design Tools (i.e.: ANFIS).
•Invariant Network Structure independent on the function to
synthesize (i.e: “if-then rules”).
•Possibility of programmable devices built by standard blocks
(Fuzzifiers, Inference Operators and Defuzzifiers).

Fuzzy Logic must take a place in the Toolbox of Analogue
Designers for the synthesis of non-linear circuits!!
UCL- June 2001
52