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The Threshold Voltage The voltage applied between the gate and the source which causes the beginning of the channel surface strong inversion. Threshold voltage Vt is a function of : » Vfb = flatband voltage; depends on difference in work function between gate and substrate and on fixed surface charge. » Fs = surface potential (FD). » Gate oxide thickness. » Charge in the channel area. » Additional ion implantation. n Typical values: 0.2V to 1.0V for NMOS and -0.2 to 1.0V for PMOS VLSI Design/ RMC Devices-2 © D. Al-Khalili 1 Threshold Adjust An effective mean to adjust the threshold is to change the doping concentration through an ion implantation dose. Ion Implantation (dopant) S NMOS transistors implanted with n-type dopant results in a decrease in threshold voltage NMOS transistors implanted with p-type dopant results in an increase in the threshold voltage. VLSI Design/ RMC D channel p Substrate VTO’=VTO + (q.DI/Cox) DI = dose of dopant in the channel area(atoms/cm2) Cox = gate oxide capacitance per unit area Devices-2 © D. Al-Khalili 2 Threshold Adjust D VT = VTO – S + VS B – G S B S Threshold voltage is a function of source to substrate voltage VSB. Body factor is the coefficient for the VSB dependence factor. VSB Fs is the surface potential ~ -0.6V for NMOS is the body factor ~ 0.6 to 1.2 V1/2 VLSI Design/ RMC Devices-2 © D. Al-Khalili 3 TOH’S MODEL In the Saturation region, In the Linear region, for V I D kVsat CoxW (Vgs Vt ) I D nCox 2 W V [Vgs ds ] L 2 ds for V ds Vdsat Vdsat In the Saturation region, Vdsat = (1-K )(Vgs-Vt ) 1 1 Esat L 1 1 Esat E (Vgs Vt ) 2V E sat sat n K VLSI Design/ RMC Devices-2 , © D. Al-Khalili 4 Models for manual analysis NMOS Transistor 2 1 IDS N = KN VGSN – VTN VDSN – ---VDSN 2 2 1 IDSN = ---KN VGSN – VTN 1 + VDSN 2 VDSN <VGSN-VTN VDSN >VGSN-VTN KN=(W/L)K’N PMOS Transistor 2 1 I D SP = –K P VGS P – V TPV D SP – --- VD SP 2 VDSP > VGSP -VTP 2 1 ID SP = – -- Kp VGS P – VTP 1 – VDS P 2 VDSP < VGSP-VTP KP=(W/L)K’P VLSI Design/ RMC Devices-2 © D. Al-Khalili 5 Dynamic Behavior of MOS Transistor G CGS CGD D S CGB CSB CDB B VLSI Design/ RMC Devices-2 © D. Al-Khalili 6 Prentice Hall/Rabaey Diffusion Capacitance VLSI Design/ RMC Devices-2 © D. Al-Khalili 7 Prentice Hall/Rabaey SPICE MODELS Level 1: Long Channel Equations - Very Simple Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical - Based on curve fitting to measured devices Level 4 (BSIM): Emperical - Simple and Popular VLSI Design/ RMC Devices-2 © D. Al-Khalili 8 MAIN MOS SPICE PARAMETERS VLSI Design/ RMC Devices-2 © D. Al-Khalili 9 Prentice Hall/Rabaey SPICE Parameters for Parasitics VLSI Design/ RMC Devices-2 © D. Al-Khalili 10 Prentice Hall/Rabaey SPICE Transistors Parameters VLSI Design/ RMC Devices-2 © D. Al-Khalili 11 Prentice Hall/Rabaey