Download Design of a Restartable Clock Generator for Use in GALS

Design of a Restartable Clock Generator
for Use in GALS SoCs
Masters Thesis Defense
Hu Wang
August 6, 2008
IC Design and Research Laboratory
ECE Department Southern Illinois University of Edwardsville
Design Team
Southern Illinois University Edwardsville
Dr. George Engel
‰ Hu Wang
‰
Blendics Integrated Circuit Systems, LLC
‰
President. Jerry Cox
ECE Department Southern Illinois University of Edwardsville
Background
¾ Verification occupies 60% to 80% of the engineering hours expended on
the design of complex integrated circuits (ICs).
¾ Module reuse along with elimination of the global verification
component of chip design has the potential to cut the design time of
future ICs.
¾ Develop a novel methodology that blends clockless and clocked systems
and eliminates the need for global verification. It is a special case of the
Globally Asynchronous, Locally Synchronous (GALS) design approach.
ECE Department Southern Illinois University of Edwardsville
Blended Design methodology
Any size clocked domain
PB
Clk
ClkBB
AABB
B
B1i
BB1c
FIFO A1i
A1i
A1c
BB<<==AA A1c
BB2c
BB2ii
A2c
A2c
A2i
A2i
FIFO
FIFO
BB==>>AA
AAAA
Clk
ClkA
PPAA
Clockless sequencing network
Pair of processing elements communicating using clockless
sequencing network
¾ The clock generator serves as a local
clock to the data processing
subsystem.
¾ A clockless sequencing network
between the two subsystems to
initiate the operation of the data
processing subsystem’s local clock,
and to signal an acknowledgment of
the completion of that action.
¾ Avoids synchronizer failures by
stopping the clock and then
restarting it when data is valid.
ECE Department Southern Illinois University of Edwardsville
Clock Generator
The operation of the clock generator is based on the simple
trigonometric identity, sin ω (t − u) = sin ωt ⋅ cos ωu − cos ωt ⋅ sin ωu
ECE Department Southern Illinois University of Edwardsville
Clock generator
¾ Constructed from a pair of fully-differential analog multipliers, a
comparator, a quad track-and-hold (T/H) circuit, a pair of SR
latches, and an OR gate.
¾ The restartable clock can be stopped and then restarted at an
arbitrary phase of the source.
¾ Can be connected to an external crystal oscillator or a local allsilicon, MEMS-based oscillator as input sources.
ECE Department Southern Illinois University of Edwardsville
Initial Analog Multiplier
First presented by Hsiao
and Wu in their paper “
A parallel structure for
CMOS four-quadrant
analog multiplier and its
application to a 2-GHz
RF down-conversion
mixer” in 1998.
ECE Department Southern Illinois University of Edwardsville
Initial Analog Multiplier
¾ Consist of six combiners which has a symmetrical
structures because they combine the input signals to form
the output.
¾ VB is the DC pedestal on which the input signals rest.
¾ Multiplication of two signals, v1 and v2 is achieved
through the use of the quarter-square principle shown
below
x⋅ y =
1
[( x + y ) 2 − ( x − y ) 2 ]
4
ECE Department Southern Illinois University of Edwardsville
Original Combiner Design
VDD
¾ The Square Law characteristic of a MOS transistor
iDS =
R
Vout
¾ One of the voltage outputs of the “first stage” combiner
vout =
VGS1
M1
M2
VGS2
1
⋅ K pn ⋅ S n ⋅ (vGS − VTN ) 2
2n
−R
−R
⋅ Kpn ⋅ Sn (VB + v1 −VTN )2 + ⋅ Kpn ⋅ Sn (VB + v2 −VTN )2 +VDD
2n
2n
Original combiner circuit
ECE Department Southern Illinois University of Edwardsville
The Output Current of the Multiplier
¾ The output currents iop and iom
iop =
iom =
S n ⋅ K pn
2n
S n ⋅ K pn
2n
[va2 + vb2 − 2VTN ⋅ (va + vb ) + 2VTN 2 ]
[vc2 + vd2 − 2VTN ⋅ (vc + vd ) + 2VTN 2 ]
¾ The differential output current of the multiplier, iout
iout = K mult ⋅ v1 ⋅ v2
where K mult
⎡⎛ S ⋅ K
n
pn
= 4 ⎢⎜⎜
⎢⎝
n
⎣
3
⎤
⎞
2
2⎥
⎟⎟ ⋅ R ⋅ (VB − VTN )
⎥
⎠
⎦
ECE Department Southern Illinois University of Edwardsville
Improved Analog Multiplier
¾ The real resistor is replaced by a PFET transistor
working in resistive region.
Req =
n
K pp ⋅ S p ⋅ (VDD − Vctrl − | VTP |)
¾ Re-written expression of Kmult
K mult
Improved combiner circuit
⎡ 2VR
⎤
=⎢
⎥
⎣ (VB − VTN ) ⎦
2
⎛ Sn ⋅ K pn
⎜⎜
n
⎝
⎞
⎟⎟
⎠
¾ By adjusting the control voltage, Vctrl, the resistance
can be altered in order that the DC voltage, VR, across
device M3 is tuned to the desired value.
ECE Department Southern Illinois University of Edwardsville
Automatic gain control circuit for resistive PFET
+VDD
¾ Voltage divider M20 & M21
M21
M20
IBias
Vctrl
¾ Symmetric Miller type – Operational
IB
- OTA
+
M19
Transconductance Amplifier (OTA)
¾ Negative feedback loop to generate the
VB
M17 M18
VB
control voltage Vctrl
ECE Department Southern Illinois University of Edwardsville
Sensitivity Analysis
Estimated and simulated results in multipliers
Initial analog multiplier
Process
Corners
Improved analog
multiplier
ΔI out _ est
ΔI out _ sim
ΔI out _ est
ΔI out _ sim
I out _ est
I out _ sim
I out _ est
I out _ sim
0
Typical
0
Best
54%
26%
-6.5%
0.5%
Worst
-48%
-57%
17.6%
-3.1%
¾ For initial multiplier:
ΔK pn
ΔI out ΔK mult
VTN
ΔV
ΔR
=
= 2⋅
+ 3⋅
− 2⋅
⋅ TN
I out
K mult
R
K pn
VB − VTN VTN
¾ For improved multiplier:
ΔI out ΔK mult ΔK pn
2 ⋅ VTN ΔVTN
=
=
+
⋅
I out
K mult
K pn VB − VTN VTN
ECE Department Southern Illinois University of Edwardsville
High-Speed Comparator
¾ Current Mirror
¾ High-Speed NFET latch
¾ Self-biased differential amplifier
¾ Push-pull output drivers
ECE Department Southern Illinois University of Edwardsville
Non Ideal Effects
¾ Channel length modulation
¾ Mismatch and offset analysis
ECE Department Southern Illinois University of Edwardsville
Channel length Modulation
¾ The I-V characteristic of a FET does not fit in the ideal
square law.
iDS =
1
⋅ K pn ⋅ Sn ⋅ (vGS − VTN ) 2
2n
¾ Factor (1 + λvDS) should be considered. λ represents the channel
length modulation factor which is inversely proportional to the
length of the device, L.
¾ The multiplier gain
K mult
⎡
⎤
2VR
=⎢
⎥
−
+
⋅
−
(
)[1
(
)]
λ
V
V
V
V
B
TN
DD
R
⎣
⎦
2
⎛ Sn ⋅ K pn
⎜⎜
n
⎝
⎞
⎟⎟
⎠
ECE Department Southern Illinois University of Edwardsville
Comparison of simulation results
Mathcad
With λ
Without λ
Electrical
Simulation
Output of the
multiplier’s
first-stage
combiner
IReq
680 μA
604 μA
706 μA
VBO1
0.5 V
0.5 V
0.49 V
Peak-to-peak
output
Iout
1.49mA
1.59mA
1.53mA
Note: IReq is DC drain-to-source current of PFET M3 in the multiplier’s first-stage combiners.
VBO1 is the DC output voltage for the first-stage combiners.
Iout is the peak-to-peak differential current transferred to the NMOS latch in the comparator
If λ is included, the analytical predictions agree closely (within 5%)
with the results obtained from electrical simulations.
ECE Department Southern Illinois University of Edwardsville
Mismatch and offset analysis
¾ Random offsets due to mismatch in transistor
parameters will result in the clock’s duty cycle
differing from the ideal fifty percent.
¾ In fact, if the offset current becomes larger than
the peak differential output current, the clock
becomes stuck at one logic level.
¾ The standard deviation of the offset current was
computed as 15 µA. The 6σ value, 90µA is well
below the upper limit of 190 µA which was
needed to ensure a reasonable duty cycle for the
output clock.
ECE Department Southern Illinois University of Edwardsville
Variance computed at each stage
¾ For NFET in the “first stage” combiner
2
σ I DS 1 =
g m12
2
⋅ σ VTN +
I DS 12
⎛σK 2 σ 2 σ 2
W
L
pn
⋅⎜
+ n2 + n2
2
⎜ K pn
Wn
Ln
⎝
⎞
⎟ = (2.5μ A) 2
⎟
⎠
¾ For the resistive PFET of the “first stage” combiner
σ Req
2
⎛ σ 2 σ K 2 σW 2 σ L 2
V
pp
p
p
= R 2 ⋅ ⎜ TP 2 +
+
+
2
2
⎜ VSAT
K pp
Wp
Lp2
⎝
⎞
⎟ = (4.3Ω) 2
⎟
⎠
¾ For the output of the “first stage” combiner
σ VO1 2 = 2 Req 2σ I DS 1 2 + ( 2 I DS1 ) σ Req 2 = (3.8mV ) 2
2
¾ For the differential current output delivered to the NMOS latch
σ Iout
2
⎛σK 2 σ 2 σ 2
Wn
Ln
pn
= 8 ⋅ g m 22 ⋅ (σ VTN 2 + σ VO1 2 ) + 8 ⋅ I DS 2 2 ⋅ ⎜
+
+
⎜ K pn 2 Wn 2
Ln 2
⎝
⎞
⎟ = (15μ A) 2
⎟
⎠
ECE Department Southern Illinois University of Edwardsville
Simulation results
VB = 570mV
Amp = 200mV
Freq = 1GHz
Duty cycle ≈ 50%
ECE Department Southern Illinois University of Edwardsville
Simulation result (cont.)
¾ Delay in restarting
clock is less than 1.5 ns.
¾ The peak-to-peak
variation in the time
required to restart the
clock is 120 psec.
ECE Department Southern Illinois University of Edwardsville
Summary
¾ The restartable clock generator is implemented in 90nm CMOS
process.
¾ Completely transistor design without resistors existing in the circuit.
¾ Up to 1GHz, clock frequency can be achieved across different process
corners.
¾ Only a single 1V supply is required with 10mW power consumption.
¾ The duty cycle of the clock output is near 50%.
¾ The delay in restarting the clock is small, less than 1.5ns.
ECE Department Southern Illinois University of Edwardsville
Conclusion
¾ The restartable clock can be stopped and then restarted at
an arbitrary phase of the source, like a delay based clock.
¾ Completely eliminates metastability hazards.
¾ Can be connected to an external crystal oscillator or a
local all-silicon, MEMS-based oscillator as input sources.
ECE Department Southern Illinois University of Edwardsville
Further work
¾ A small systematic offset should be added into the
comparator to ensure that the clock always restart from
low to high.
¾ Monte Carlo simulations to confirm the results presented
in thesis predicting the likely offset current will be
performed in the future.
¾ Efficiently generate the quadrature input signals from an
external crystal oscillator or MEMS-based clock.
ECE Department Southern Illinois University of Edwardsville
Acknowledgement
‰
‰
‰
‰
‰
‰
Dr. George Engel, SIUE
President. Jerry Cox, Blendics, LLC
Mr. Sasi K. Tallapragada
Mr. Dinesh Dasari
Mr. Nagendra S. Valluru
NSF-STTR and Blendics, LLC
ECE Department Southern Illinois University of Edwardsville
Thank You !
Hu Wang
Graduate student
Email: [email protected]
IC Design Research Laboratory
Electrical and Computer Engineering Department
Southern Illinois University Edwardsville