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Download Z-PACK HS3 6 Row ELECTRICAL PERFORMANCE REPORT Literature Number 1308505
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ELECTRICAL PERFORMANCE REPORT Z-PACK HS3 6 Row Vertical Plug to Right Angle Receptacle Literature Number 1308505 Issued September, 2000 Copyright, Tyco Electronics Corporation All Rights reserved Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle EPR 1308505 Issued: 09-2000 TABLE OF CONTENTS INTRODUCTION.................................................................................................................................iii What is an EPR?................................................................................................................................iii Why use this EPR? ............................................................................................................................iii HOW TO USE AN EPR ....................................................................................................................... iv The Simulation Page........................................................................................................................... v Simulation Graphs .............................................................................................................................. v Input Voltage .................................................................................................................................. v Near & Far End Noise Values ......................................................................................................vii MODEL OVERVIEW ........................................................................................................................viii The Single Line Model (SLM) ........................................................................................................viii The Multi Line Model (MLM)........................................................................................................viii The Footprint Via Matrix (FVM) Model .......................................................................................... ix SIMULATION DATA ........................................................................................................................... 1 Z-PACK HS3 6 Row .......................................................................................................................... 1 HS3, 6 Row, Vertical Plug to Right Angle Receptacle Electrical Interconnection Performance Information ......................................................................................................................................... 2 MODEL WIRING PATTERNS............................................................................................................. 3 SIMULATION LOOK-UP TABLE....................................................................................................... 4 Specifications subject to change. Consult AMP for latest design specifications. Copyright 2000 by AMP Incorporated All Rights Reserved. AMP is a registered trademark. ii Contents Printed on Recycled Paper Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle EPR 1308505 Issued: 09-2000 INTRODUCTION The first several pages of this Electrical Performance Report (EPR) are intended to give an overview of the AMP EPR. By understanding how to apply information from an AMP EPR, system designers will be able to select the best AMP product for their application. What is an EPR? EPRs (Electrical Performance Reports) are technical documents composed of electrical simulations of connector models. Each of these simulations varies in several system parameters. EPRs are used to assist system design engineers in the selection of potential connector solutions for their particular application. While there are several non-technical issues that enter into the connector selection decision, these electrical performance criteria are becoming very important. Why use this EPR? The EPR provides system designers with fundamental data relating to the electrical performance of a connector. This data, in turn, allows the system designer to decide if the connector under analysis is the proper interconnection device for his or her application. Criteria that impact the electrical performance of a connector include wiring patterns, edge rates, system impedances and logic families. The EPR permutes these criteria one step at a time, while holding all other parameters constant. This approach reveals the effects that each change may or may not cause. If used properly, an EPR can facilitate in choosing the proper connector for an application. Furthermore, the EPR can help in selecting wiring patterns, edge rates, system impedances, and logic families within an application. For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 iii Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle EPR 1308505 Issued: 09-2000 HOW TO USE AN EPR Following a systematic method, pertinent information can be derived from the various EPR simulations. The parametric nature of simulations can best be explained by recognizing that various factors affect coupled noise: • • • • • • Wiring Pattern Logic Family (excitation) System Impedance (Zo) Signal Risetime Voltage Swing Connection Capacitance SIMULATION LOOK-UP TABLE Consolidates all simulations in the EPR to quickly find pertinent simulation(s). SIMULATION LEGEND AND NOTES Defines Simulation Look-up Table fields. Can include graphics to relate. MODEL PATTERNS Wiring patterns used for the simulations. Single-ended and differential patterns are simulated, where applicable. Select a representative model pattern that is similar to your application setup. Find the rows in the Simulation Look-Up Table that correspond to this wiring (model) pattern. In the table, you will see several parameters that vary given this model pattern. Note the simulation filename of interest, and go to that page to find graphs of electrical simulation data. For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 iv Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle EPR 1308505 Issued: 09-2000 The Simulation Page The simulation page shows the graphical results of a simulation on a connector under defined system parameters. Referring to the figure below, it can be seen that the several parameters that effect the electro-dynamics of the connector are shown. MODEL PATTERN Shows the connections to the connector model. SIMULATION GRAPHS Provide voltage versus time information. Graphs include Input Voltage, Near and Far End Noise Voltages. MODEL PATTERN LEGEND Defines connections to the connector model. SIMULATION Defines logic family, voltage swing, and rise time used in this simulation. INTERCONNECTION Shows the simulation's system impedance, and the PAD (in the case of SMT) or plated through-hole capacitance. Simulation Graphs The value of the EPR is realized when voltage values are found on the simulation graphs. The plots of voltage versus time reveal both absolute values of voltage levels and where they occur in time. These values can help in determining the contribution or impact of the connector/connection on the system noise budget. In some occurrences, where multiple lines are monitored, a rough estimate of skew can be determined. The total noise tolerance should be determined, understanding that it is different for different logic families. Input Voltage The Input Voltage graph shows the incident and far end voltage of the connector including the connection effects (PAD or plated through hole capacitance). Overall symmetry (in the case of differential signals) can be seen. Refer to the following graph for more information: For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 v Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle EPR 1308505 Issued: 09-2000 INPUT voltage graphs. In this case, a differential system, the INPUT voltages (VIA3 & VIA4) are plotted with the output voltages (VOA3 & VOA4) versus time. Input Voltage [94103187] VIA3 VIA4 VOA3 VOA4 2.4 VOA4 (Output voltage, pin A4) 2.2 VIA3 (Input voltage, pin A3) 2.0 VOLTAGE(mv) 1.8 1.6 1.4 1.2 VOA3 (Output voltage, pin A3) 1.0 0.8 VIA4 (Input voltage, pin A4) 0.6 0.4 0.0 0.4 0.8 1.2 1.6 2.0 TIME(ns) The voltage response (refer to the voltage swing in following figure) of the connector should approach that of the logic family as defined in the simulation area of the EPR graph pages. The propagation delay of the connector can be determined as the difference in time that the incident and far end graphs cross the same voltage level. In the case below, the propagation delay would be: propagation delay: ∆ t = t 2 − t1 Input Voltage [94103187] VIA3 VIA4 VOA3 VOA4 2.4 2.2 VIA3 (Input voltage, pin A3) 2.0 VOLTAGE(mv) 1.8 1.6 1.4 Voltage Swing 1.2 VOA3 (Output voltage, pin A3) 1.0 0.8 0.6 0.4 0.0 0.4 0.8 1.2 1.6 TIME(ns) Propagation delay of connector t1 t2 For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 vi 2.0 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle EPR 1308505 Issued: 09-2000 Near & Far End Noise Values Near and far end noise values include the effects of the return path in their determination. Simulated values are absolute and can be included in their percent contribution to the total noise budget as determined by the system designer. In the following Near End Noise Voltage figure, the effects of adjacent pairs that are out-of-phase can be seen (the +/- of two differentially driven lines). Note that similar techniques are used with the Far End Noise voltage graphs. NEAR END NOISE VOLTAGE vna4b4 vnf4 60.00 vna4b4 Differential Voltage between pins a4 and b4 50.00 Voltage (mV) 40.00 30.00 vnf4 Near End Noise Voltage of pin f4 20.00 10.00 0.00 -10.00 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 Time(ns) To summarize, the EPR arms the system designer with simulation information from the simulation setups that closely match his or her design. This information can be effectively used to focus on follow-up simulations, and it is of great aid in selecting connector and wiring pattern candidates. For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 vii Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle EPR 1308505 Issued: 09-2000 MODEL OVERVIEW The Single Line Model (SLM) The SLM is used to evaluate the effects of a single set of connector pins. A SLM is representative of a well referenced connector. A simulation with the SLM can show the following effects: PROPAGATION DELAY DRIVE POWER ATTENUATION TIMING REFLECTIONS Single Line Model IMPEDANCE The SLM for the connector found in this EPR is listed on the next page. Note: A SLM was NOT used to generate simulation data in this EPR. (FOR CROSSTALK, A MULTI-LINE MODEL MUST BE USED.) The Multi Line Model (MLM) The MLM (Multi-Line Model) is used in all the simulations found in this EPR. The MLM accounts for the electrostatic and electromagnetic coupling (crosstalk) as well as the common impedance noise found in a connector. Its structure couples, in three dimensions, all pins to one another. This results in a complex model that uses series resistance, inductance, coupling capacitance and inductive coupling coefficients so arranged to allow connections at both the input and output. This modeling technique effectively shows coupled noise at the expense of CPU runtime. Simulations done using the MLM will show the following information: PROPAGATION DELAY DRIVE POWER CROSSTALK ELECTROSTATIC COUPLING ATTENUATION TIMING COMMON MODE NOISE ELECTROMAGNETIC COUPLING Multi Line Model - The Fundamental Structure REFLECTIONS IMPEDANCE The fundamental MLM varies in the number of pins (rows & columns) and the number of sections. Note that faster rise times require multiple sections. To learn more about AMP Simulation capabilities, e-mail us: [email protected] URL: www.amp.com/simulation For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 viii Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle EPR 1308505 Issued: 09-2000 The Footprint Via Matrix (FVM) Model With increasing data rates, the rise-time of the signals are becoming fast enough that the footprint of a connector will significantly affect the electrical performance of an interconnect. While the structure of the connector is fixed and can be readily specified for its insertion loss characteristics in a given line environment, the connection is highly variable due to the influence of the footprint. The approach of representing the footprint with only series capacitance may no longer suffice. A challenge posed to the design engineer is how to better represent the connector footprint in a system simulation. One practical approach is to use a Footprint Via Matrix (FVM) Model. The structure of the FVM model is similar to that of the connector’s matrix model; containing series Resistance and Inductance, along with inter-via mutual capacitance and inductance matrices. The inter-via matrices represent the coupling between plated through holes. In addition, the FVM model structure includes a via-to-plane capacitance matrix. The via-to-plane capacitance matrix represents the coupling between each plated through hole and its adjacent planes and traces. The FVM model values are a function of the following: (1) (2) (3) (4) (5) PCB thickness (length) PCB material (Dielectric Constant and Dissipation Factor) Pad and anti-pad dimensions Stack-up (number of planes and spacing) Trace connection location (a) a high-connected signal trace (via in full stub configuration; presenting maximum low impedance condition) (b) a mid-connected signal trace (via in half-stub, half series configuration) (c) a low-connected signal trace (via in full series configuration; presenting minimum low impedance condition) NOTE : THE FOOTPRINT VIA MATRIX MODEL IS A PRACTICAL ENGINEERING TOOL COVERING A GENERIC PCB SPECIFICATION. YOUR PARTICULAR BOARD STACKUP MAY OR MAY NOT BE FAITHFULLY MODELED BY THE EXAMPLE MODEL. Via-to-Plane Structure (Side View of VIA) Inter-VIA Structure Top-Connected Trace GND GND Mid-Connected Trace GND GND Bottom-Connected Trace For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 ix Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle EPR 1308505 Issued: 09-2000 SIMULATION DATA Z-PACK HS3 6 Row Vertical Plug to Right Angle Receptacle For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 1 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle EPR 1308505 Issued: 09-2000 HS3, 6 Row, Vertical Plug to Right Angle Receptacle Electrical Interconnection Performance Information a This document contains abstracts of the results of various computer simulations of electrical interconnection performance. The HS3 6 Row connector evaluated in this report is an impedance controlled board to board connector that is ideal for high-end server, mass storage, and networking applications. a The Model Pattern Orientation in this set of data represents a board to board interconnection. The simulations are run on the three column model, as shown in Section a-a, which is adequate for most wiring patterns. Gr2 B C Gr3 D E F Model Pattern Orientation (Section a-a) As shown in the “Simulation Circuit Abstract” figure to the right, the simulation model is a validated matrix circuit model (AMP MLM P/N 1999-3681-051) which provides for the series resistance and inductance elements of each line, the electrostatic coupling between lines, and the electromagnetic coupling between lines. The model for this connector has multiple sections and is useful for digital signals with edge rates as fast as 125 ps. CONNECTOR MODEL RC driven line(s) RS VS LC CP CP near end ref RC reference line(s) RT C M CP RT far end ref LC quiet line(s) RC L M CP RT LC Simulation Circuit Abstract signal The model is configured so that any position in the matrix may be assigned as a driven line, a quiet line, or a reference line. Each line can be terminated (RT) as desired, pad capacitances (CP) can be assigned as desired, with driving functions (VS) and source impedances (RS) assigned as desired. The near end and far end references are isolated to allow observation of common impedance effects of the connector. coupled region Vs Vb Vf Backward crosstalk Forward crosstalk Electrostatic and Electromagnetic Crosstalk signal driven line The simulation model outputs include both the electrostatic (E) and magnetic (M) crosstalk and the common mode noise contributions. This sum is reported as Near End Noise Voltage and/or Far End Noise Voltage. For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 Gr1 A i (-) (+) Zc (-) (+) noise (+) (-) Common Impedance Noise 2 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle EPR 1308505 Issued: 09-2000 MODEL WIRING PATTERNS A B All Signal 1 - - 2 - - 3 - - a Q a F gr3 X X Dif f erent ial (Vertical Pairs) Ground t owards Out side Rows (Rows D and E monit ored) 1 - - E aI Q aI gr3 D a A a E gr2 X X aI AI aI gr2 B a Q a C X X aI A aI gr1 X 1 - a F gr3 X E D gr2 2 - - X a X X X a Q a X X X C X X X B a A a gr1 A X X a X Q a X a aI gr3 3 - - X X X X X A a D I I aI a X A X X C a Q a B I Q aI a X X X A X X a gr1 X X 2 - - E gr2 X AI X X X X 2:1 Signal to Ground F Dif f erent ial (Vertical) Pairs Ground t owards Inside Rows Ground t owards Inside Rows (Rows E and F monit ored) (Rows A and B monitored) 1 - - 2 - - 3 - - a Q a F X aI Dif f erent ial (Vertical) Pairs 3 - - Q a A 1 - F gr3 2:1 Signal to Ground E 2:1 Signal to Ground X X (Rows B and C monitored) X Q aI Ground t owards Out side Rows X Q a A D X aI Dif f erent ial (Vertical Pairs) 3 - - X a B X Q X D X C gr1 X F X 2 - - 2:1 Signal to Ground C 2:1 Signal to Ground X X X 1 - - 2 - - 3 - - a A a F gr3 X X X E I a Q I a E I a A I aI D X X X D X X X gr2 X X X gr2 X X X C X X X C X X X B a A a B a Q a gr1 A X X I a X A I gr1 I a A X X I a X Q aI LEGEND X Ground Line a Active (Driven) Line A Monitored Active (Driven) Line aI Active (Inverted) Line AI Monitored Active (Inverted) Line q Passive Line Q Monitored Passive Line For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 3 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle EPR 1308505 Issued: 09-2000 SIMULATION LOOK-UP TABLE (Indexed by S/G Ratio, then by Logic Family, then by Tr) Table Legend: Cp DH DV GI GO Logic: S/G Ratio Tr Vf Vo VMM Zo: Pad or Plated Through Hole capacitance Differential signal (horizontal pairs) Differential signal (vertical pairs) Grounded Lines Towards Inside Rows Grounded Lines Towards Outside Rows Logic family simulated Ratio of signal lines to reference (ground) lines Rise time of source Source final voltage Source initial voltage Via Matrix Model Characteristic Impedance Multi-Line Model Used: HSC6313 (Connector) H6FP_PKG (Footprint) Simulation Tool: HSPICE v99.2 Simulation Filename 2000091801 2000091802 2000091803 2000091804 2000091805 S/G Page Ratio 5 All SignalDV (A) 6 7 8 9 Driver Type(1) PECL Tr Vo Vf Zo Cp (ns) (Volts) (Volts) (Ohms) (pf) 0.3 1.5 2.4 50 FVM(2) All SignalDV (A) Fibre-channel 0.15 2:1 DV:GO (B) 2:1 DV:GO (B) 2:1 DV:GO (C) 2:1 DV:GO (C) 1.8 2.5 50 FVM 0.3 1.5 2.4 50 FVM Fibre-channel 0.15 1.8 2.5 50 FVM 0.3 1.5 2.4 50 FVM Fibre-channel 0.15 1.8 2.5 50 FVM PECL PECL 2000091806 10 2000091807 11 2:1 (D) CMOS 0.5 0 3.3 65 FVM 2000091808 12 2:1 (D) CMOS 1.0 0 3.3 65 FVM 13 2:1 DV:GI (E) PECL 0.3 1.5 2.4 50 FVM 2:1 DV:GI (E) Fibre-channel 0.15 1.8 2.5 50 FVM 2:1 DV:GI (F) 0.3 1.5 2.4 50 FVM 2:1 DV:GI (F) Fibre-channel 0.15 1.8 2.5 50 FVM 2000091809 2000091810 2000091811 2000091812 14 15 16 PECL (1) DRIVER TYPE: Piece-wise linear voltage sources are used to simulate the drivers. The PWL sources are developed based on voltage swing and rise time (the dv/dt values are linear between the 10%-90% or 20%-80% points, depending on the logic’s specification). (2) FVM (Footprint Via Matrix – reference page ix): The FVM used for all simulations herein represents vias with mid-connected traces) for a .200” thick backplane and .100” thick load card. Plane spacing was designed to maintain 50 ohm stripline traces using 8 mil trace widths in FR4 material. 0.052” diameter circular antipads were included in the modeling. For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 4 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle SIMULATION FILENAME: EPR 1308505 Issued: 09-2000 2000091801 INPUT VOLTAGE MODEL PATTERN vid2 vod2 vic2 All Signal voc2 Tim e (ns) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 3.00 gr3 2.50 2.00 Voltage (V) 1 - - 2 - - 3 - - a Q a F 1.00 X E a Q aI D a A a X X X C I a A I aI B a Q a gr1 0.50 X I gr2 1.50 X X X I A a X aI Q 0.00 NEAR END NOISE VOLTAGE vnb2a2 LEGEND vnf2e2 Tim e (ns) 0.00 2.00 0.20 0.40 0.60 0.80 1.00 1.20 X Ground Line a Active (Driven) Line 0.00 A Monitored Active (Driven) Line -2.00 aI Active (Inverted) Line Voltage (mV) -4.00 AI Monitored Active (Inverted) Line -6.00 q Passive Line -8.00 Q Monitored Passive Line -10.00 -12.00 DRIVER TYP -14.00 ∆ 1.5 -16.00 PECL V to 2.4 V PWL Ramp FAR END NOISE VOLTAGE vfb2a2 vff2e2 Tr (ns): 0.3 (20%-80%) Time (ns) 0.00 3.00 0.20 0.40 0.60 0.80 1.00 1.20 INTERCONNECTION 50 Ohm Lines 2.00 FVM* used for Cp Voltage (mV) 1.00 * NOTE: FVM=Footprint Via Matrix (reference page ix) 0.00 GRAPH NOTES -1.00 VI - Input Voltage -2.00 VO - Output Voltage VN - Near End Noise Voltage -3.00 VF - Far End Noise Voltage -4.00 PWL - Piece Wise Linear For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 Page 5 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle SIMULATION FILENAME: MODEL PATTERN 2 - - a gr3 X 3 - - X X a Q aI D a A a X X X I I C a A B a Q vod2 vid2 100.0 200.0 300.0 400.0 500.0 600.0 2.50 E I gr2 voc2 Time (ps) 0.0 a Q vic2 3.00 I 2.00 Voltage (V) F 2000091802 INPUT VOLTAGE All Signal 1 - - EPR 1308505 Issued: 09-2000 1.50 a 1.00 gr1 A X X a X I Q a 0.50 I a 0.00 LEGEND X NEAR END NOISE VOLTAGE vnb2a2 vnf2e2 Time (ps) Ground Line 0.00 5.00 100.00 200.00 300.00 400.00 500.00 600.00 a Active (Driven) Line A Monitored Active (Driven) Line 0.00 aI Active (Inverted) Line A Monitored Active (Inverted) Line q Passive Line -5.00 Voltage (mV) I Q Monitored Passive Line DRIVER TYPE: -10.00 -15.00 -20.00 Fibre-channel -25.00 ∆ 1.8 V to 2.5 V PWL Ramp FAR END NOISE VOLTAGE vfb2a2 vff2e2 Tr (ns): 0.15 (10%-90%) Tim e (ps) 0.00 8.00 INTERCONNECTION 50 Ohm Lines VI - Input Voltage VO - Output Voltage 4.00 Voltage (mV) GRAPH NOTES 200.00 6.00 FVM* used for Cp * NOTE: FVM=Footprint Via Matrix (reference page ix) 100.00 2.00 0.00 -2.00 VN - Near End Noise Voltage -4.00 VF - Far End Noise Voltage PWL - Piece Wise Linear -6.00 For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 Page 6 300.00 400.00 500.00 600.00 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle SIMULATION FILENAME: EPR 1308505 Issued: 09-2000 2000091803 INPUT VOLTAGE MODEL PATTERN vic2 voc2 vib2 2:1 Signal to Ground vob2 Dif f erent ial (Vert ical Pairs) Ground t owards Out side Rows (Rows D and E monit ored) Tim e (ns) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 3.00 1 - - 2 - - 3 - - X X X F 2.50 gr3 Voltage (V) X E a Q a I Q aI a gr2 X X X C a A a B I I aI 1.00 a gr1 0.50 X D 2.00 1.50 X X A X X A X X X 0.00 NEAR END NOISE VOLTAGE LEGEND vne2d2 Tim e (ns) 0.00 2.00 0.20 0.40 0.60 0.80 1.00 1.20 X Ground Line a Active (Driven) Line 0.00 A Monitored Active (Driven) Line -2.00 aI Active (Inverted) Line Voltage (mV) -4.00 AI Monitored Active (Inverted) Line -6.00 q Passive Line -8.00 Q Monitored Passive Line -10.00 -12.00 DRIVER TYP -14.00 ∆ 1.5 -16.00 PECL V to 2.4 V PWL Ramp FAR END NOISE VOLTAGE vfe2d2 Tr (ns): 0.3 (20%-80%) Time (ns) 0.00 4.00 0.20 0.40 0.60 0.80 1.00 1.20 INTERCONNECTION 50 Ohm Lines 3.00 FVM* used for Cp Voltage (mV) 2.00 * NOTE: FVM=Footprint Via Matrix (reference page ix) 1.00 GRAPH NOTES 0.00 VI - Input Voltage -1.00 VO - Output Voltage VN - Near End Noise Voltage -2.00 VF - Far End Noise Voltage -3.00 PWL - Piece Wise Linear For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 Page 7 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle SIMULATION FILENAME: MODEL PATTERN vic2 Differential (Vertical Pairs) Ground towards Outside Rows 2 - - 3 - - X X X a D I a X Q a Q I a X C a A a B I I aI gr1 A X A X X 100.0 200.0 300.0 400.0 500.0 600.0 2.50 2.00 0.50 X X 1.50 1.00 X 0.00 LEGEND X vob2 X X a vib2 3.00 Voltage (V) X E gr2 0.0 1 - - X voc2 Time (ps) (Rows D and E monitored) gr3 2000091804 INPUT VOLTAGE 2:1 Signal to Ground F EPR 1308505 Issued: 09-2000 NEAR END NOISE VOLTAGE vne2d2 Time (ps) Ground Line 0.00 5.00 100.00 200.00 300.00 400.00 500.00 600.00 a Active (Driven) Line A Monitored Active (Driven) Line 0.00 aI Active (Inverted) Line A Monitored Active (Inverted) Line q Passive Line -5.00 Voltage (mV) I Q Monitored Passive Line DRIVER TYPE: -10.00 -15.00 -20.00 Fibre-channel -25.00 ∆ 1.8 V to 2.5 V PWL Ramp FAR END NOISE VOLTAGE vfe2d2 Tr (ns): 0.15 (10%-90%) Time (ps) 0.00 10.00 INTERCONNECTION 50 Ohm Lines 6.00 4.00 Voltage (mV) GRAPH NOTES 200.00 8.00 FVM* used for Cp * NOTE: FVM=Footprint Via Matrix (reference page ix) 100.00 2.00 0.00 VI - Input Voltage VO - Output Voltage -2.00 VN - Near End Noise Voltage -4.00 VF - Far End Noise Voltage PWL - Piece Wise Linear -6.00 For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 Page 8 300.00 400.00 500.00 600.00 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle SIMULATION FILENAME: EPR 1308505 Issued: 09-2000 2000091805 INPUT VOLTAGE MODEL PATTERN vie2 voe2 vid2 2:1 Signal to Ground vod2 Diff erent ial (Vert ical Pairs) Ground t owards Out side Rows Tim e (ns) 0.0 0.2 0.4 0.6 0.8 1.0 (Rows B and C monitored) 1.2 3.00 1 - - 2 - - 3 - - X X X F 2.50 gr3 Voltage (V) X X a A a D I I aI 2.00 1.50 X E a gr2 X A X X C a Q a B I Q aI 1.00 a gr1 0.50 X X X A X X X 0.00 NEAR END NOISE VOLTAGE LEGEND vnc2b2 Tim e (ns) 0.00 2.00 0.20 0.40 0.60 0.80 1.00 1.20 X Ground Line a Active (Driven) Line 0.00 A Monitored Active (Driven) Line -2.00 aI Active (Inverted) Line Voltage (mV) -4.00 AI Monitored Active (Inverted) Line -6.00 q Passive Line -8.00 Q Monitored Passive Line -10.00 DRIVER TYP -12.00 ∆ 1.5 -14.00 PECL V to 2.4 V PWL Ramp FAR END NOISE VOLTAGE vfc2b2 Tr (ns): 0.3 (20%-80%) Time (ns) 0.00 4.00 0.20 0.40 0.60 0.80 1.00 1.20 INTERCONNECTION 50 Ohm Lines 3.00 FVM* used for Cp Voltage (mV) 2.00 * NOTE: FVM=Footprint Via Matrix (reference page ix) 1.00 GRAPH NOTES 0.00 VI - Input Voltage -1.00 VO - Output Voltage VN - Near End Noise Voltage -2.00 VF - Far End Noise Voltage -3.00 PWL - Piece Wise Linear For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 Page 9 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle SIMULATION FILENAME: MODEL PATTERN EPR 1308505 Issued: 09-2000 2000091806 INPUT VOLTAGE 2:1 Signal to Ground vie2 voe2 vid2 vod2 Differential (Vertical Pairs) Ground towards Outside Rows (Rows B and C monitored) 1 - - 2 - - 3 - - X X X X X E a A a D I I I a gr2 X A X a X C a Q a B I Q aI a gr1 A X X X 200.0 300.0 400.0 500.0 600.0 2.50 2.00 X X 1.50 1.00 0.50 X 0.00 LEGEND X 100.0 X Voltage (V) F gr3 Time (ps) 0.0 3.00 NEAR END NOISE VOLTAGE vnc2b2 Time (ps) Ground Line 0.00 5.00 100.00 200.00 300.00 400.00 500.00 600.00 a Active (Driven) Line A Monitored Active (Driven) Line 0.00 I AI Monitored Active (Inverted) Line q Passive Line Voltage (mV) a Active (Inverted) Line -5.00 -10.00 Q Monitored Passive Line -15.00 DRIVER TYPE: Fibre-channel -20.00 ∆ 1.8 V to 2.5 V PWL Ramp FAR END NOISE VOLTAGE vfc2b2 Tr (ns): 0.15 (10%-90%) Tim e (ps) 0.00 6.00 INTERCONNECTION 50 Ohm Lines 100.00 200.00 4.00 FVM* used for Cp GRAPH NOTES VI - Input Voltage VO - Output Voltage VN - Near End Noise Voltage VF - Far End Noise Voltage PWL - Piece Wise Linear 2.00 Voltage (mV) * NOTE: FVM=Footprint Via Matrix (reference page ix) 0.00 -2.00 -4.00 -6.00 For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 Page 10 300.00 400.00 500.00 600.00 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle EPR 1308505 Issued: 09-2000 2000091807 SIMULATION FILENAME: MODEL PATTERN INPUT VOLTAGE vib2 2:1 Signal to Ground vob2 Tim e (ns) Voltage (V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1 - - 2 - - 3 - - a Q a 3.50 F 3.00 gr3 2.50 E X X X 2.00 D a Q a gr2 1.50 X X X X X X C X X X B a A a 1.00 0.50 gr1 X X X 0.00 a A a Q -0.50 NEAR END NOISE VOLTAGE vna2 vnd2 LEGEND vnf2 Time (ns) 0.00 100.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 X Ground Line a Active (Driven) Line 90.00 A Monitored Active (Driven) Line 80.00 aI Active (Inverted) Line 70.00 Voltage (mV) 60.00 AI Monitored Active (Inverted) Line 50.00 q Passive Line 40.00 Q Monitored Passive Line 30.00 20.00 10.00 DRIVER TYP CMOS 0.00 ∆ 0 -10.00 V to 3.3 V PWL Ramp FAR END NOISE VOLTAGE vfa2 vfd2 vff2 Tr (ns): 0.5 (10%-90%) T im e (ns) 0.00 25.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 2.00 INTERCONNECTION 65 Ohm Lines 20.00 FVM* used for Cp 15.00 10.00 * NOTE: FVM=Footprint Via Matrix (reference page ix) 5.00 Voltage (mV) 1.80 0.00 GRAPH NOTES -5.00 -10.00 VI - Input Voltage -15.00 VO - Output Voltage -20.00 VN - Near End Noise Voltage -25.00 VF - Far End Noise Voltage -30.00 PWL - Piece Wise Linear For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 Page 11 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle INPUT VOLTAGE 2:1 Signal to Ground 2 - - a F gr3 X X X X D a Q a X X C X X X B a A a gr1 X X a A 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.00 X X 0.0 X E gr2 vob2 3.50 a Q vib2 T im e (ns) 3 - - 2.50 2.00 Voltage (V) 1 - - 2000091808 SIMULATION FILENAME: MODEL PATTERN EPR 1308505 Issued: 09-2000 1.50 1.00 0.50 X 0.00 a Q -0.50 LEGEND X NEAR END NOISE VOLTAGE vna2 vnd2 vnf2 T im e (ns) Ground Line 0.00 50.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 a Active (Driven) Line A Monitored Active (Driven) Line 40.00 aI Active (Inverted) Line A Monitored Active (Inverted) Line q Passive Line 30.00 Voltage (mV) I Q Monitored Passive Line DRIVER TYPE: ∆ 0 20.00 10.00 0.00 CMOS -10.00 V to 3.3 V PWL Ramp FAR END NOISE VOLTAGE vfa2 vfd2 vff2 Tr (ns): 1.0 (10%-90%) Tim e (ns) 0.00 10.00 INTERCONNECTION 0.50 1.00 1.50 8.00 65 Ohm Lines 6.00 FVM* used for Cp GRAPH NOTES VI - Input Voltage VO - Output Voltage VN - Near End Noise Voltage VF - Far End Noise Voltage PWL - Piece Wise Linear Voltage (mV) 4.00 * NOTE: FVM=Footprint Via Matrix (reference page ix) 2.00 0.00 -2.00 -4.00 -6.00 -8.00 -10.00 For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 Page 12 2.00 2.50 3.00 3.50 4.00 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle SIMULATION FILENAME: EPR 1308505 Issued: 09-2000 2000091809 INPUT VOLTAGE MODEL PATTERN vib2 vob2 via2 2:1 Signal to Ground voa2 Dif f erent ial (Vert ical) Pairs Ground t owards Inside Rows (Rows E and F monit ored) Tim e (ns) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 3.00 1 - - 2 - - 3 - - a Q a F 2.50 gr3 Voltage (V) X E a Q aI D X X X gr2 X X X C X X X B a A a 1.00 gr1 0.50 X I 2.00 1.50 X X X I A a X A I aI 0.00 NEAR END NOISE VOLTAGE LEGEND vnf2e2 Time (ns) 0.00 20.00 0.20 0.40 0.60 0.80 1.00 1.20 X Ground Line a Active (Driven) Line 18.00 A Monitored Active (Driven) Line 16.00 aI Active (Inverted) Line 14.00 Voltage (mV) 12.00 AI Monitored Active (Inverted) Line 10.00 q Passive Line 8.00 Q Monitored Passive Line 6.00 4.00 2.00 DRIVER TYP PECL 0.00 ∆ 1.5 -2.00 V to 2.4 V PWL Ramp FAR END NOISE VOLTAGE vff2e2 Tr (ns): 0.3 (20%-80%) T im e (ns) 0.00 4.00 0.20 0.40 0.60 0.80 1.00 1.20 INTERCONNECTION 50 Ohm Lines 2.00 FVM* used for Cp Voltage (mV) 0.00 * NOTE: FVM=Footprint Via Matrix (reference page ix) -2.00 GRAPH NOTES -4.00 VI - Input Voltage -6.00 VO - Output Voltage VN - Near End Noise Voltage -8.00 VF - Far End Noise Voltage -10.00 PWL - Piece Wise Linear For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 Page 13 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle MODEL PATTERN SIMULATION FILENAME: 2000091810 INPUT VOLTAGE 2:1 Signal to Ground vib2 Differential (Vertical) Pairs Ground towards Inside Rows vob2 via2 voa2 Time (ps) (Rows E and F monitored) 0.0 1 - - 2 - - 3 - - a Q a F EPR 1308505 Issued: 09-2000 100.0 200.0 300.0 400.0 500.0 600.0 3.00 2.50 X X X E aI Q aI D X X X gr2 X X X C X X X B a A a gr1 A X X aI 2.00 Voltage (V) gr3 1.00 0.50 X AI aI 0.00 LEGEND X 1.50 NEAR END NOISE VOLTAGE vnf2e2 Time (ps) Ground Line 0.00 25.00 100.00 200.00 300.00 400.00 500.00 600.00 a Active (Driven) Line A Monitored Active (Driven) Line 20.00 aI Active (Inverted) Line A Monitored Active (Inverted) Line q Passive Line 15.00 Voltage (mV) I Q Monitored Passive Line DRIVER TYPE: 10.00 5.00 0.00 Fibre-channel -5.00 ∆ 1.8 V to 2.5 V PWL Ramp FAR END NOISE VOLTAGE vff2e2 Tr (ns): 0.15 (10%-90%) Time (ps) 0.00 5.00 INTERCONNECTION 100.00 200.00 50 Ohm Lines 0.00 * NOTE: FVM=Footprint Via Matrix (reference page ix) GRAPH NOTES VI - Input Voltage VO - Output Voltage Voltage (mV) FVM* used for Cp -5.00 -10.00 -15.00 VN - Near End Noise Voltage VF - Far End Noise Voltage PWL - Piece Wise Linear -20.00 For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 Page 14 300.00 400.00 500.00 600.00 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle SIMULATION FILENAME: EPR 1308505 Issued: 09-2000 2000091811 INPUT VOLTAGE MODEL PATTERN vif2 vof2 vie2 2:1 Signal to Ground voe2 Dif f erent ial (Vert ical) Pairs Ground t owards Inside Rows (Rows A and B monit ored) Tim e (ns) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 3.00 1 - - 2 - - 3 - - a A a F 2.50 gr3 Voltage (V) X E a A I aI D X X X gr2 X X X C X X X B a Q a 1.00 gr1 0.50 X I 2.00 1.50 X X X I A X aI Q a 0.00 NEAR END NOISE VOLTAGE LEGEND vnb2a2 Tim e (ns) 0.00 25.00 0.20 0.40 0.60 0.80 1.00 1.20 X Ground Line a Active (Driven) Line A Monitored Active (Driven) Line 20.00 aI Active (Inverted) Line Voltage (mV) 15.00 AI Monitored Active (Inverted) Line 10.00 q Passive Line Q Monitored Passive Line 5.00 0.00 DRIVER TYP ∆ 1.5 -5.00 PECL V to 2.4 V PWL Ramp FAR END NOISE VOLTAGE vfb2a2 Tr (ns): 0.3 (20%-80%) T im e (ns) 0.00 4.00 0.20 0.40 0.60 0.80 1.00 1.20 INTERCONNECTION 50 Ohm Lines 2.00 FVM* used for Cp Voltage (mV) 0.00 * NOTE: FVM=Footprint Via Matrix (reference page ix) -2.00 GRAPH NOTES -4.00 VI - Input Voltage -6.00 VO - Output Voltage VN - Near End Noise Voltage -8.00 VF - Far End Noise Voltage -10.00 PWL - Piece Wise Linear For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 Page 15 Electrical Performance Report – Z-PACK HS3, 6 Row, Vertical Plug to Right Angle Receptacle MODEL PATTERN SIMULATION FILENAME: 2000091812 INPUT VOLTAGE 2:1 Signal to Ground vif2 Differential (Vertical) Pairs Ground towards Inside Rows vof2 vie2 voe2 Time (ps) (Rows A and B monitored) 0.0 1 - - 2 - - 3 - - a A a F EPR 1308505 Issued: 09-2000 100.0 200.0 300.0 400.0 500.0 600.0 3.00 2.50 X X X E aI AI aI D X X X gr2 X X X C X X X B a Q a gr1 A X X aI 2.00 Voltage (V) gr3 1.00 0.50 X Q aI 0.00 LEGEND X 1.50 NEAR END NOISE VOLTAGE vnb2a2 Time (ps) Ground Line 0.00 35.00 100.00 200.00 300.00 400.00 500.00 600.00 a Active (Driven) Line 30.00 A Monitored Active (Driven) Line 25.00 aI Active (Inverted) Line A Monitored Active (Inverted) Line q Passive Line 20.00 Voltage (mV) I Q Monitored Passive Line 15.00 10.00 5.00 0.00 DRIVER TYPE: Fibre-channel -5.00 -10.00 ∆ 1.8 V to 2.5 V PWL Ramp FAR END NOISE VOLTAGE vfb2a2 Tr (ns): 0.15 (10%-90%) Time (ps) 0.00 15.00 INTERCONNECTION 50 Ohm Lines VI - Input Voltage VO - Output Voltage 5.00 Voltage (mV) GRAPH NOTES 200.00 10.00 FVM* used for Cp * NOTE: FVM=Footprint Via Matrix (reference page ix) 100.00 0.00 -5.00 -10.00 VN - Near End Noise Voltage -15.00 VF - Far End Noise Voltage PWL - Piece Wise Linear -20.00 For drawings, technical data, or samples, contact your AMP Sales Engineer or call the AMP Product Information Center: 1-800-522-6752 Page 16 300.00 400.00 500.00 600.00 1308505-250-AMP-AMP-09/2000