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EE4271 VLSI Design Dr. Shiyan Hu Office: EERC 518 The Wires Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. EE141 Integrated © Digital Circuits2nd Wires 1 Modern Interconnect receivers transmitters EE141 Integrated © Digital Circuits2nd Wires 2 Modern Interconnect - II EE141 Integrated © Digital Circuits2nd Wires 3 Interconnect Delay Dominates Delay (psec) 300 250 Interconnect delay 200 150 100 Transistor/Gate delay 50 0 0.8 0.5 0.35 0.25 Technology generation (m) Source: Gordon Moore, Chairman Emeritus, Intel Corp. EE141 Integrated © Digital Circuits2nd Wires 4 Wire Model EE141 Integrated © Digital Circuits2nd Wires 5 Capacitor A capacitor is a device that can store an electric charge by applying a voltage The capacitance is measured by the ratio of the charge stored to the applied voltage Capacitance is measured in Farads EE141 Integrated Circuits2nd © Digital Wires 3D Parasitic Capacitance Given a set of conductors, compute the capacitance between all pairs of conductors. - + + + - EE141 Integrated Circuits2nd © Digital 1V + + - - - C=Q/V - Wires Simplified Model Area capacitance (Parallel plate): area overlap between adjacent layers/substrate Fringing/coupling capacitance: between side-walls on the same layer between side-wall and adjacent layers/substrate EE141 Integrated Circuits2nd © Digital m3 m2 m2 m2 m1 Wires The Parallel Plate Model (Area Capacitance) c di t di Current flow WL L Electrical-field lines W H tdi Dielectric Substrate Capacitance is proportional to the overlap between the conductors and inversely proportional to their separation EE141 Integrated © Digital Circuits2nd Wires 9 Wire Capacitance More difficult due to multiple layers, different dielectric =8.0 multiple dielectric m3 =4.0 m2 =3.9 m2 m2 =4.1 m1 EE141 Integrated Circuits2nd © Digital Wires Simple Estimation Methods - I C = Ca*(overlap area) +Cc*(length of parallel run) +Cf*(perimeter) Coefficients Ca, Cc and Cf are given by the fab Cadence Dracula Fast but inaccurate EE141 Integrated Circuits2nd © Digital Wires Simple Estimation Methods - II Consider interaction between layer i and layers i+1, i+2, i–1 and i–2 Cadence Silicon Ensemble Accuracy 50% EE141 Integrated Circuits2nd © Digital Wires Library Based Methods Build a library of tens of thousands of patterns and compute capacitance for each pattern Partition layout into blocks, and match with the library Accuracy 20% EE141 Integrated Circuits2nd © Digital Wires Accurate Methods In Industry Finite difference/finite element method Most accurate, slowest Raphael Boundary element method FastCap, Hicap EE141 Integrated Circuits2nd © Digital Wires Fringing versus Parallel Plate Coupling capacitance dominates. (from [Bakoglu89]) EE141 Integrated © Digital Circuits2nd 15 Wires Wire Resistance Basic formula R=(/h)(l/w) l h w : resistivity h: thickness, fixed for a given technology and layer number l: conductor length w: conductor width EE141 Integrated Circuits2nd © Digital Wires Sheet Resistance Simply R=(/h)(l/w)=Rs(l/w) l w Rs: sheet resistance Ohms/square, where h is the metal thickness for that metal layer. Given a technology, h is fixed at each layer. l: conductor length w: conductor width EE141 Integrated Circuits2nd © Digital Wires Typical Rs (Ohm/sq) Min Typical Max M1, M2 0.05 0.07 0.1 M3, M4 0.03 0.04 0.05 Poly 15 20 30 Diffusion 10 25 100 N-well 2000 5000 EE141 Integrated Circuits2nd © Digital 1000 Wires Contact and Via Contact: link metal with diffusion (active) Link metal with gate poly Via: Link wire with wire EE141 Integrated © Digital Circuits2nd 19 Wires Interconnect Delay EE141 Integrated © Digital Circuits2nd 20 Wires Analysis of Simple RC Circuit i(t) R R i (t ) v(t ) vT (t ) vT(t) ± C d (Cv(t )) dv(t ) i (t ) C dt dt dv(t ) RC v(t ) vT (t ) dt state variable Input waveform EE141 Integrated Circuits2nd © Digital Wires v(t) Analysis of Simple RC Circuit Step-input response: v0 v0u(t) v0(1-e-t/RC)u(t) dv(t ) v(t ) v0u (t ) dt t v(t ) Ke RC v0u(t ) RC match initial state: v(0) 0 K v0u (t ) 0 K v0 0 output response for step-input: v(t ) v0 (1 e EE141 Integrated Circuits2nd © Digital t RC )u(t ) Wires 0.69RC v(t) = v0(1 - e-t/RC) -- waveform under step input v0u(t) v(t)=0.5v0 t = 0.69RC i.e., delay = 0.69RC (50% delay) v(t)=0.1v0 t = 0.1RC v(t)=0.9v0 t = 2.3RC i.e., rise time = 2.2RC (if defined as time from 10% to 90% of Vdd) For simplicity, industry uses TD = RC (= Elmore delay) We use both RC and 0.69RC in this course. In textbook, it always uses 0.69RC. EE141 Integrated Circuits2nd © Digital Wires Elmore Delay Delay EE141 Integrated Circuits2nd © Digital 1. 50%-50% point delay 2. Delay=RC (Precisely, 0.69RC) Wires Elmore Delay - III What is the delay of a wire? EE141 Integrated © Digital Circuits2nd 25 Wires Elmore Delay – IV Assume: Wire modeled by N equal-length segments For large values of N: Precisely, should be 0.69RC/2 EE141 Integrated © Digital Circuits2nd 26 Wires Elmore Delay - V n2 n1 n1 n2 C/2 R C/2 R=unit wire resistance*length C=unit wire capacitance*length EE141 Integrated © Digital Circuits2nd 27 Wires RC Tree Delay 4 4 2 2 7 7 2 24+4*2=32 1 1 Unit wire cap=1, unit wire res=1 3.5 2*(1+3.5+3.5+2+2)=24 RC Tree Delay=max{32,48.5}=48.5 EE141 Integrated © Digital Circuits2nd 3.5 2 24+7*3.5=48.5 Precisely, 0.69*48.5 28 Wires More Accurate RLC Delay Model I=V/R at t=0 is not right since you assume that you can see R with 0 time At time t=0, switch is on. This effect is not felt everywhere instantaneously. Rather, the effect is propagated with a speed u. Denote by c0 the speed of light, epsilon the permittivity and mu the permeability of the dielectric of the medium which the wire is in, L and C the unit wire inductance and capacitance, respectively. According to Maxwell’s law, EE141 Integrated © Digital Circuits2nd 29 Wires RLC Delay - II Voltage and Current at time t1 and t2 R0 is the resistance you can really see at t1. R cannot be seen yet. EE141 Integrated © Digital Circuits2nd 30 Wires RLC Delay - III What is R0? The front of the voltage travels from 0 to l. Suppose that the distance it moves is dx, the capacitance to be charged is Cdx. The charge is thus dQ=CdxV. Current I=dQ/dt=CVdx/dt=CVu where is called characteristic impedance. EE141 Integrated Circuits2nd © Digital Wires RLC Delay - IV R0 is a function of the medium For Printed Circuit Board (PCB), it is about 50-75 ohm For any x between 0 and l, we always have Ix=Vx/R0,Il=Vl/R0 when x=l Note that there is a resistor R. We should have Il=Vl/R What happens if R!= R0? EE141 Integrated Circuits2nd © Digital Wires RLC Delay - V At load, the wave will be reflected back to the source. The amplitude and polarity of this reflected wave are such that the total voltage, the sum of incident voltage and reflected voltage, satisfies Il=Vl/R If the incident voltage is V, denote by pV the reflected voltage, where p is called the reflection coefficient. If incident current is V/R0, then reflected current is –pV/R0 Thus, (V+pV)/(V/R0–pV/R0)=R. p=(R/R0-1)/(R/R0+1) R=R0, p=0, no reflection R=infty, p=1, wire is unterminated R=0, p=-1, wire is short-circuited There can be multiple rounds of reflections. EE141 Integrated Circuits2nd © Digital Wires RLC Delay Example Consider a wire of length l, R0=100 ohm, R=900 ohm driven by the source resistance (transistor equivalent resistance) Rs= 14 ohm. Source voltage is 12V as a step input at time t=0. We want to compute the waveform at the end of l. Rs=14 Reflection coefficient At t=0, V1=12*R0/(R0+Rs)=10V since it cannot see R yet At t=td=l/u, wave V1 arrives at the end and is reflected as V2=pRV1=8V. The total voltage at the end is V1+V2 =18V At time t=2td, wave V2 arrives at the source and reflected as V3=pSV2=-0.75*8=-6V At time t=3td, wave V3 arrives at the end and is reflected as V4=PRV3=-4.8V, so the total voltage at the end is V1+V2+V3+V4=7.2V Continues this process. Next total voltage at the end is 13.7V. The total voltage at l will converge to 12*R/(R+Rs)=11.7V EE141 Integrated Circuits2nd © Digital Wires RLC Delay Example - II Voltage at the end of l EE141 Integrated © Digital Circuits2nd 35 Wires When To Use RLC Model v0 v0u(t) v0(1-e-t/RC)u(t) RC Model, V0=12 The voltages at first few td have large magnitudes and are quite different from RC model. This is because Rs<R0. When Rs>>R0, V1 is small and is the reflected voltage V2. The total voltage at the end of the wire will gradually increase to 11.7V, which is the same as predicted by RC model. Thus, RLC model should only be used when Rs is small (see also Figure 4-21 in the textbook) since RLC model is expensive to compute. RLC model can be used when the switching is fast enough since signal transition time is proportional to Rs. EE141 Integrated Circuits2nd © Digital Wires Summary Wire capacitance Fringing/coupling capacitance dominates area capacitance Wire resistance RC Elmore delay model for wire For single wire, 0.69RC/2 RC tree RLC model for wire Reflection When to use EE141 Integrated Circuits2nd © Digital Wires