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EE415 VLSI Design
The Devices:
MOS Transistor
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
EE415 VLSI Design
The MOS Transistor
Polysilicon
EE415 VLSI Design
Aluminum
MOS Transistor Cross Section
MOS transistor
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The MOS Transistor
Gate Oxyde
Gate
Source
Polysilicon
n+
Drain
n+
p-substrate
Bulk Contact
CROSS-SECTION of NMOS Transistor
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Field-Oxyde
(SiO2)
p+ stopper
Switch Model of NMOS Transistor
| VGS |
Source
(of carriers)
Open (off) (Gate = ‘0’)
Gate
Drain
(of
carriers)
Closed (on) (Gate = ‘1’)
Ron
| VGS | < | VT |
EE415 VLSI Design
| VGS | > | VT |
Switch Model of PMOS Transistor
| VGS |
Source
(of carriers)
Open (off) (Gate = ‘1’)
Gate
Drain
(of carriers)
Closed (on) (Gate = ‘0’)
Ron
| VGS | > | VDD – | VT | |
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| VGS | < | VDD – |VT| |
MOS transistors Symbols
D
D
G
G
S
S
NMOS Enhancement NMOS Depletion
D
G
G
S
PMOS Enhancement
EE415 VLSI Design
D
B
S
NMOS with
Bulk Contact
Channel
MOSFET Static Behavior
VGS =0
Mobile electrons
Depletion Region
With drain and source grounded, and VGS = 0, both back-to-back (subsource, sub-drain) junctions have 0V bias and are OFF
EE415 VLSI Design
MOSFET Static Behavior
Positive voltage applied to the gate (VGS > 0)
•The gate and substrate form the plates of a capacitor.
•Negative charges accumulate on the substrate side (repels mobile holes)
•A depletion region is formed under the gate (like pn junction diode)
+
S
VGS
-
D
G
n+
n+
n-channel
Depletion
Region
p-substrate
EE415 VLSI Design
B
Inversion
As the VGS increases, the surface under the gate undergoes inversion to ntype material. This is the beginning of a phenomenon called strong
inversion.
Further increases in VGS do not change the width of the depletion layer,
but result in more electrons in the thin inversion layer, producing a
continuous channel from source to drain
EE415 VLSI Design
The Threshold Voltage
The value of VGS where strong inversion occurs is called the Threshold
Voltage, VT , and has several components:
•The flat-band voltage, VFB , is the built-in voltage offset across the MOS
structure and depends on fixed charge and implanted impurities charge
on the oxide-silicon interface
•VB represents the voltage drop across the depletion layer at inversion and
equals to minus twice the Fermi potential ~(0.6V)
•Vox represents the potential drop
across the gate oxide
VT  VFB  VB  Vox
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The Threshold Voltage
Where:
F is the Fermi potential ( ~ -0.3V for ptype substrates
Cox is the gate oxide capacitance
VSB is the substrate bias voltage
VT0 is VT at VSB = 0
Note:
VT is positive for NMOS transistors and
negative for PMOS
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Body-Bias

The body-bias factor
1
(

n
Cox

2q 
Na
S
[V 1/2]
i
and the adjusted threshold voltage
VTn  VT0n  (
( 2
NFVSB  2 
NF
)
n


Typical values: the body bias (n.0.4 [V1/2], Fermi
potential NF . -0.3 [V],
gate oxide xox . 0.01 [µm].
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The Body Effect
0.9
0.85
0.8
0.75
VT (V)
0.7
0.65
0.6
0.55
0.5
0.45
0.4
-2.5
-2
-1
-1.5
V
BS
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(V)
-0.5
0
Current-Voltage Relations
Assume VGS > VT
•A voltage difference VDS will cause ID to flow from drain to source
•At a point x along the channel, the voltage is V(x), and the gate-tochannel voltage is VGS - V(x)
•For channel to be present from drain to source, VGS - V(x) > VT,
i.e. VGS - VDS > VT for channel to exist from drain to source
VGS
VDS
S
G
n+
–
V(x)
ID
D
n+
+
L
x
p-substrate
B
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MOS transistor and its bias conditions
Linear (triode) Region
•When VGS - VDS > VT , the channel exists from drain to source
•Transistor behaves like voltage controlled resistor
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Saturation Region
•When VGS - VDS  VT , the channel is pinched off
•Electrons are injected into depletion region and accelerated
towards drain by electric field
•Transistor behaves like voltage-controlled current source
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Pinch-off
Current-Voltage Relations
Long-Channel Device
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Current-Voltage Relations
Long Channel transistor
6
x 10
-4
VGS= 2.5 V
5
VDS = VGS - VT
Resistive
Saturation
4
ID (A)
VGS= 2.0 V
3
Quadratic
Relationship
VDS = VGS - VT
2
VGS= 1.5 V
cut-off
1
0
VGS= 1.0 V
0
0.5
1
1.5
2
2.5
VDS (V)
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
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A model for manual analysis
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Dynamic Behavior of MOS Transistor
•MOSFET is a majority carrier device
(unlike pn junction diode)
•Delays depend on the time to (dis)charge
the capacitances between MOS terminals
•Capacitances originate from three sources:
•basic MOS structure (layout)
•charge present in the channel
S
•depletion regions of the reverse-biased
pn-junctions of drain and source
•Capacitances are non-linear and vary with
the applied voltage
EE415 VLSI Design
G
CGS
CGD
D
CGB
CSB
B
CDB
MOS Structure Capacitances
Gate Capacitance
•Gate isolated from channel by gate oxide
Cox   ox / tox
•tox small as possible
•Results in gate capacitance Cg
C g  CoxWL
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Gate Capacitance
Gate Oxide
Gate
Source
Polysilicon
n+
Drain
n+
p-substrate
Bulk Contact
CROSS-SECTION of NMOS Transistor
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Field-Oxide
(SiO2)
p+ stopper
The Gate Capacitance
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The Gate Capacitance
Gate Capacitance depends on
•channel charge (non-linear)
•topology
Capacitance due to topology
•Source and drain extend below the gate oxide by xd
(lateral diffusion)
•Effective length of the channel Leff is shorter than the
drawn length by factor of 2xd
•Cause of parasitic overlap capacitance, CgsO, between
gate and source (drain)
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The Gate Capacitance
Overlap Capacitance
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Channel Capacitance
The Channel Capacitance
Channel Capacitance has three components
•capacitance between gate and source, Cgs
•capacitance between gate and drain, Cgd
•capacitance between gate and bulk region, Cgb
Channel Capacitance values
•non-linear, depends on operating region
•averaged to simplify analysis
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The Channel Capacitance
Different distributions of gate capacitance for varying
operating conditions
Most important regions in digital design: saturation and cut-off
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Diffusion Capacitance
Bottom Plate Capacitance
Junction Depth
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Capacitive Device Model
G
CGS = Cgs+ CgsO
CGS
CGD = Cgd+ CgdO
CGB = Cgb
CSB = CSdiff
CGD
D
S
CGB
CSB
CDB = CDdiff
B
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CDB
The Sub-Micron MOS Transistor
•Actual transistor deviates substantially from model
•Channel length becomes comparable to other device
parameters. Ex: depth of drain and source junctions
•Referred to as a short-channel device
•Influenced heavily by secondary effects
•Latchup problems
EE415 VLSI Design
The Sub-Micron MOS Transistor
Secondary Effects:
•Threshold Variations
•Parasitic Resistances
•Velocity Saturation and Mobility Degradation
•Sub-threshold Conduction
EE415 VLSI Design
Threshold Variations
Part of the region below gate is depleted by source and
drain fields, which reduce the threshold voltage for short
channel. Similar effect is caused by increase in Vds, so
threshold is smaller with larger Vds
VT
VT
Long-channel threshold
L
Threshold as a function of
the length (for low VDS)
EE415 VLSI Design
Low VDS threshold
Vds
Drain-induced barrier lowering
(for low L)
Parasitic Resistances
Polysilicon gate
increase W
G
LD
Drain
contact
D
S
RS
RS , D 
W
VGS,eff
RD
LS , D
W
RSQ  RC
Drain
RSQ is the resistance per square
RC is the contact resistance
Silicide the bulk region
EE415 VLSI Design
Variations in I-V Characteristics
•The velocity of the carriers is proportional to the electric field up to
a point. When electric field reaches a critical value, Esat, the velocity
saturates.
•When the channel length decreases, only a small VDS is needed for
saturation
•Causes a linear dependence of the saturation current wrt the gate
voltage (in contrast to squared dependence of long-channel device)
•Current drive cannot be increased by decreasing L
•Reduced L decreases the mobility of the carriers due to the vertical
component of the electric field (decreases ID)
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u n (m/s)
Velocity Saturation
usat = 105
Constant velocity
Constant mobility (slope = µ)
xc = 1.5
EE415 VLSI Design
x (V/µm)
Voltage-Current Relation:
Velocity Saturation
For short channel devices
 Linear: When VDS  VGS – VT
ID = (VDS) k’n W/L [(VGS – VT)VDS – VDS2/2]
where
(V) = 1/(1 + (V/xcL)) is a measure of the degree of
velocity saturation

Saturation: When VDS = VDSAT  VGS – VT
IDSat = (VDSAT) k’n W/L [(VGS – VT)VDSAT – VDSAT2/2]
EE415 VLSI Design
Velocity Saturation Effects
10
For short channel devices
and large enough VGS – VT
VDSAT < VGS – VT so
the device enters
saturation before VDS
reaches VGS – VT and
operates more often in
saturation

0
IDSAT has a linear dependence wrt VGS so a reduced
amount of current is delivered for a given control voltage

EE415 VLSI Design
Velocity Saturation
1.5
0.5
VGS = 3
0.5
VGS = 2
VGS = 1
0.0
1.0
2.0
VDS
3.0
(V)
4.0
(a) I D as a function of VDS
5.0
ID (mA)
VGS = 4
I D (mA)
1.0
Linea r Dependence
VGS = 5
0
0.0
1.0
2.0
VGS (V)
(b) ID as a function of VGS
(for VDS = 5 V).
Linear Dependence on VGS
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3.0
Sub-Threshold Conduction
The Slope Factor
-2
10
Linear
-4
I D ~ I 0e
10
-6
Quadratic
, n  1
-8
10
-10
Exponential
-12
VT
10
10
0
0.5
1
1.5
VGS (V)
EE415 VLSI Design
CD
Cox
S is DVGS for ID2/ID1 =10
ID (A)
10
qVGS
nkT
2
2.5
Typical values for S:
60 .. 100 mV/decade
Short Channel I-V Plot (NMOS)
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
2,5
X 10-4
Early Velocity
Saturation
VGS = 2.5V
2
VGS = 2.0V
1,5
Linear
1
Saturation
VGS = 1.5V
VGS = 1.0V
0,5
0
0
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0,5
1
1,5
VDS (V)
2
2,5
Sub-Threshold ID vs VGS
I D  I 0e
qVGS
nkT
qV
 DS

1  e kT






VDS from 0 to 0.5V
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Sub-Threshold ID vs VDS
I D  I 0e
qVGS
nkT
VGS from 0 to 0.3V
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qV
 DS

1  e kT



1    VDS 


ID versus VGS
-4
6
x 10
-4
x 10
2.5
5
2
4
linear
quadratic
ID (A)
ID (A)
1.5
3
1
2
0.5
1
0
0
quadratic
0.5
1
1.5
VGS(V)
Long Channel
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2
2.5
0
0
0.5
1
1.5
VGS(V)
Short Channel
2
2.5
ID versus VDS
-4
6
-4
x 10
VGS= 2.5 V
x 10
2.5
VGS= 2.5 V
5
2
Resistive Saturation
ID (A)
VGS= 2.0 V
3
VDS = VGS - VT
2
1
VGS= 1.5 V
0.5
VGS= 1.0 V
VGS= 1.5 V
1
0
0
VGS= 2.0 V
1.5
ID (A)
4
VGS= 1.0 V
0.5
1
1.5
VDS(V)
Long Channel
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2
2.5
0
0
0.5
1
1.5
VDS(V)
Short Channel
2
2.5
A unified model
for manual analysis
G
S
D
B
VT0(V)
(V0.5)
VDSAT(V)
k’(A/V2)
(V-1)
NMOS
0.43
0.4
0.63
115 x 10-6
0.06
PMOS
-0.4
-0.4
-1
-30 x 10-6
-0.1
EE415 VLSI Design
A PMOS Transistor
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V
-4
0
x 10
-0.2
ID (A)
-0.4
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
Assume all variables
negative!
-0.6
VGS = -2.5V
-0.8
-1
-2.5
-2
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-1.5
-1
VDS (V)
-0.5
0
The Transistor as a Switch
VGS  V T
Ron
S
ID
V GS = VD D
D
Rmid
R0
V DS
VDD/2
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VDD
The Transistor as a Switch
VGS  VT
7
x105
6
S
Resistance inversely
proportional to W/L (doubling W
halves Ron)

Ron
D
5
3
For VDD>>VT+VDSAT/2, Ron
independent of VDD
2


4
1
Once VDD approaches VT, Ron
increases dramatically
VDD (V)
0
0,5
1
1,5
2
(for VGS = VDD,
VDS = VDD VDD/2)
2,5
VDD(V)
1
1.5
2
2.5
NMOS(k)
35
19
15
13
PMOS (k)
115
55
38
31
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Ron (for W/L = 1)
For larger devices
divide Req by W/L
The Transistor as a Switch
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Summary of MOSFET
Operating Regions

Strong Inversion VGS > VT
» Linear (Resistive) VDS < VDSAT
» Saturated (Constant Current) VDS  VDSAT

Weak Inversion (Sub-Threshold) VGS  VT
» Exponential in VGS with linear VDS dependence
EE415 VLSI Design
Latchup
VD D
VDD
p
+
n
+
+
n
+
p
+
+
p
n-well
p-source
n
Rnwell
Rpsubs
n-source
p-substrate
(a) Origin of latchup
EE415 VLSI Design
Rnwell
Rpsubs
(b) Equivalent circuit
Fitting level-1 model
to short channel characteristics
Region of
matching
ID
Short-channel
I-V curve
VGS = 5 V
Long-channel
approximation
VDS = 5 V
VDS
Select k’ and  such that best matching is obtained @ Vgs= Vds = VDD
EE415 VLSI Design
SPICE MODELS
Level 1: Long Channel Equations - Very Simple
Level 2: Physical Model - Includes Velocity
Saturation and Threshold Variations
Level 3: Semi-Emperical - Based on curve fitting
to measured devices
Level 4 (BSIM): Emperical - Simple and Popular
Berkeley Short-Channel IGFET Model
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MAIN MOS SPICE PARAMETERS
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SPICE Parameters for Parasitics
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SPICE Transistors Parameters
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Simple Model versus SPICE
2.5
x 10
-4
VDS=VDSAT
2
Velocity
Saturated
ID (A)
1.5
Linear
1
VDSAT=VGT
0.5
VDS=VGT
0
0
0.5
Saturated
1
1.5
VDS (V)
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2
2.5
Technology Evolution
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Process Variations
Devices parameters vary between runs and even on
the same die!
Variations in the process parameters, such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by nonuniform conditions during the deposition and/or the diffusion of the
impurities. This introduces variations in the sheet resistances and transistor parameters such as the threshold voltage.
Variations in the dimensions of the devices, mainly resulting from the
limited resolution of the photolithographic process. This causes (W/L)
variations in MOS transistors and mismatches in the emitter areas of
bipolar devices.
EE415 VLSI Design
Impact of Device Variations
2.10
2.10
Delay (nsec)
Delay (nsec)
1.90
1.90
1.70
1.70
1.50
1.10 1.20 1.30 1.40 1.50 1.60
Leff (in mm)
1.50
–0.90
–0.80
–0.70
–0.60 –0.50
VTp (V)
Delay of Adder circuit as a function of variations in L and VT
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Future Perspectives
25 nm FINFET MOS transistor
EE415 VLSI Design