Download CMP16_spec

Presented by
Nikolay Bondar.
Fermilab. 09/08/00
Anode Front-End Electronics
current status
Anode Amplifier Discriminator chip (CMP16_F) specification
Specified for design
Implemented in ACD16_F
Used technology
-
Amplifier input noise
0.5fC@Cin=0 pF
0.7fC@Cin=0 pF
1.7fC@Cin=200 pF
1.5fC@Cin=180 pF
30 ns
40 ns
Semi-gaussian with two exponent tail cancellation
5 mV/fC
9 mV/fC
Shaper peaking time
Shaped waveform
Transfer function (gain)
AMI 1.5u BiCMOS
Two threshold discriminator
High threshold used as ENABLE.
Low threshold zero-crossing discriminator
driven by a constant fraction shaped pulse
High level threshold
Adjustable 0 - 500 mV
Adjustable 0 - 100 fC
Output pulse width
Input pulse over the threshold
~ 80 ns (average)
Discriminator slewing time
<3 ns
<3 ns
Initial delay
100 ns
Dead time
350 ns
Minimum stable threshold
5 fC (on bench)
Threshold temperature variation
-0.5fC/degree C (preliminary)
Delay temperature variation
0.2 ns/degree C (preliminary)
Operational voltage
Power consumption
Package
200 mW/channel
4.5 - 5.5 V
35 mW/ch
QFP 80 - (Plastic Quad Flat Pack)
14 mm x 20 mm , 80 pins,
0.8 mm pin pitch
Anode Amplifier Discriminator chip (CMP16_F) current status
CMP16_F chip received in April 11.
90 chips was received in that time and 160 chips more in May. Total - 250 chips.
First 90 chips was assembled on AD16 boards and carefully tested with the Test Stand.
All results are placed on CMU web pages.
Statistic: -initially broken chips - 2 out of 90
-most of chips match specification
-the chip parameters are pretty consistent
Resume - 1.5 u rules more stable and reliable than previous 1.2 u.
These chips used for: - supplied 3 FAST sites with AD16 boards
- Rad. test
- broken during test on chamber
- spare
-72
- 10
-3
-2
Additional 160 chips - assembled on AD16 board. Just received from company, not tested yet.
100 chips - for steady state test
60 chips spare .
CMP16_F chip problem
CMS16 Chip corresponds to the initial specification.
Only one problem - after switching to the new design rules (1.5u)
the chip became slower the output pulse waveform overshooting
increased from 5% up to 30% . Dead time increased from 180ns to 350ns.
The reason of this changes - increased parasitic capacitance (factor 2)
That is an easy correctable problem.
According simulation there is possibility to go back to initial waveform.
Anode Front-End Board (AFEB) AD-16 specification
Board dimension
Input connector
Inputs
Input signal
min. detectable charge
max. detectable charge
max. allowed charge
2.8’ x 3.075” x 0.625”
strip socket, two rows, 34 contacts
DC isolated
Negative current pulse
5 fC
1000 fC
10 uC
Output connector
Outputs
40-pin header with polarized key
current source LVDS compatible (1.5 mA)
Threshold control voltage
0 - 1.7 V
0 V- corresponds to maximum threshold
negative, 0 to -2 V
20 ns rise time
> 2 us pulse width
0.25 fC/mV transfer function
110 Ohm termination
Input test pulse:
Power supply voltage
Current
Power consumption
Remote power switch
+5.5 V
+6.0 V maximum
0.09 A @+5.5~V
495 mW total
31 mW per channel
TTL level high -on / low -off
Anode Front-End Board integration issues
AD16 is designed for direct connection to a protection board on the
chamber. The board sticks out of the side of chamber via a slot in the CSC
side panel. A special bracket is attached to the panel next to the slot to fix the
board and provide additional grounding between the board and the chamber.
All AD16 boards on the chamber will be covered by an aluminum cover for
additional shielding and mechanical protection. All mechanical drawings are
made by Vladislav Razmyslovich.
The AFEB - ALCT cables (halogen free) are grouped into sets of
different lengths to accommodate the different distances between sets of
AD16 boards (3 boards per column) and the ALCT. They have strain relief on
both ends. Each type of CSC has its own cable layout and individual cable
sets. First issue of drawings for the cable assembly is ready thanks of TD
help. Galogen free cable have been received. First samples of new cables are
ready.
CMP16_F chip and AD16 board reliability test.
(Proposal)
Problem to solve:
-estimate burn-in test time duration (Mil. Spec.- 360 hours @ 125°C)
-estimate long term reliability for AD16 board (Mil. Spec. - 1000 hour @125°C)
Test performance and setup:
100 AD16 boards powered and pulsed and placed in an oven
under 100°C for long term running 2000 -7000 (?) hours.
Test procedure:
Weekly the board must be taken out and tested.
A regression curve will be plotted.
Test will be finished when we get 50% of dead channels.
Equipment:
Heavy duty oven
Power supply +5.5V 10A
Pulse generator
Delay chip DEL16 specification
Used technology
Input signal level
Output signal
Output pulse width
Delay minimum
Delay step DT
Number of delay steps N
Delay function
Delay nonlinearity
AMI 0.5u CMOS
LVDS standard
3.3 V CMOS
40 ns (adjustable with an external current)
20 ns
2 ns (adjustable with an external current)
15 maximum
20 ns+N*DT
DT/2
Delay control interface
serial
Control interface signal specifications:
CLRB
Set delay to zero
ChSB
Select chip to download delay data.
Data is fixed inside the chip at the end of the ChSB pulse.
CLC
Clock pulses
D_IN
Input data
D_OUT
Output data pattern
Power supply voltage
Chip package
3.3 V
QFP 64 10 x 10 (Plastic Quad Flat Pack)
10 mm x10 mm, 64 pins, 0.5 mm pin pitch