Download Floating-Gate Systems

Preliminary stuff
Prof. Paul Hasler
Capacitor Circuits
C2
Q
I
Vout(t)
GND
Capacitor Circuits
C2
dQ(t)
dt
Q
= Iin

C2
dVout(t)
dt = - Iin
I
Vout(t)
GND
We get an integration….
Capacitor Circuits
C2
dQ(t)
dt
Q
= Iin

C2
dVout(t)
dt = - Iin
I
Vout(t)
GND
For constant I, we get
Vout(t) = Vstart -
Iin
C2
t
We get an integration….
Capacitor Circuits
C2
dQ(t)
dt
Q
= Iin

C2
dVout(t)
dt = - Iin
I
Vout(t)
GND
We get an integration….
Vout(t)
For constant I, we get
Vout(t) = Vstart -
Iin
C2
t
t
Capacitor Circuits
Vtun
C
Vdd
Vd
Vref
Vout
Vout(t)
Injection
Tunneling
t
Floating-Gate Systems
Prof. Paul Hasler
Floating-Gate Devices
• Digital Memory (EEPROMs)
• Analog Memory
• Floating-Gate Circuits
• Floating-Gate Systems
• Floating-Gate Adaptation
• Information Storage
• Floating-Gate Transistor
• Modifying Floating-Gate Charge
- UV photo-injection
- Electron tunneling
- Hot-electron injection
All of this in a standard
CMOS process
Floating-Gate Circuits
Capacitor-Based Circuits
Charge Modification
• Decrease Floating-Gate
charge by hot-electron
injection
• Increase Floating-Gate
charge by electron
tunneling
• Resistors and Inductors define
the circuit dynamics
• Capacitors are the natural elements
on silicon ICs
Electron Tunneling
(oxide voltage)-1
Increasing the applied voltage decreases the effective barrier width
The range of tunneling currents span many orders of magnitude.
pFET Hot-Electron Injection
The injected electrons are generated
by hole impact ionizations.
**Injection current is proportional
to source current, and is an
exponential function of Fdc.
Vinj = 430mV
Offset elimination
Huge Linear Range
Small Linear Range
Differential Output Current (nA)
80
Direction of offset due to
hot-electron injection onto
the floating gatedevices.
0
-80
-3
0
Differential Input Voltage
Offset is less than 1 mV.
3
Tunable Voltage Sources
Tunnel
Select
Cf
Tunneling
Circuitry
VOLTMETER
Inject
SELECT
UP
DOWN
Output Voltage: (if selected)
• Decreased by Tunneling
• Increased by Injection
Select
Injection
Circuitry
Vref
Arrays of Prog.Voltage Sources
•EPot elements are arranged in a linear array with
a shift register selecting one element at a time
tunnel
inject
select
E
Vout
E
Vout
E
Vout
tunnel
inject
select
tunnel
inject
select
Speed used: ~1V/ms
( range is 100V/ms to very very slow)
Translinear Element using
Floating-Gate Devices
Vdd
Vdd
I1
I2
Iout
GND
GND
GND
A Single-Ended Gm-C filter
using Floating-Gate Devices
Vdd
Vdd
I1
I2
C
C
-1
Vin
C
GND
C
GND
Vout
Programming / Selectivity in FG Array
V1
V2
V3
V4
100
Tunneling Phase
Injection Phase
Non-selected Synap se
10
Selected Synapse
1
2 conditions for injection
• channel current
(Gate voltage)
•Large Source to drain voltage
(high field for hot electrons)
0.1
0
50
100
150
200
Half-second pulse steps
250
300
350
400
Programming a
Floating-gate Device
• Tunneling
– Remove charge from
floating-gate
– Less control per device
– Used as “global” erase
– Decrease current for a
given threshold
V
tun
+
V
in
• Hot-electron injection
– Add electrons to the
floating-gate
– Isolate devices well
– Program accurately
– Increase current for a given
gate voltage
+
I
Basic Programming Structure
V1
V2
V3
V4
Injection
 Both:
Gate:
Columnisolation
Device
isolation
 Source-Drain:
Row isolation
Programming a FG
Bring chip up to program voltage
Bring drain up to match Vds(run)
Set Gate volt to read current
Read Current through device
Calculate next pulse on drain
Pulse Drain voltage
Rinse and repeat
V
tun
+
V
in
A
+
-
Offchip
Basic Programming Structure
Input Signals / Circuitry
S
S
S
S
S
S
S
S
Gate Pin
S
S
S
S
DECODER
Column
(M. Kucic, P. Smith, P. Hasler, 2000-2001)
Programming Board Interface
Progr ammin g Bo ard
Current
Monitor
Block
Testing Board
To
Drain
SPI
To
Gate
DAC
Selection Logic
Level
Shifters
Regu lator
Additional
User
Circuits
Programming Board, v0.1
Answers to Typical Questions
Is storing analog charge levels on a floating-gate reliable?
Yes, we have seen little to no movement over months
(like 0.01mV in EPots)
Isn’t floating-gate programming is slow?
We are currently programming in ms times,
should get to 1-10ms times as in EEPROM,
and the process can operate in parallel.
Does this require specialized processes?
Can be built in either Double Poly or Single Poly
(i.e. digital) processes
Automatic Floating-Gate Programming
(NSF ITR)
START
Get in Range
Programming Results
Select Next Element
Measure Current
Yes
< target
Compute Drain V
Inject Element
No
Floating-Gate Bias Current (nA)
Programming Algorithm
12
10
cosine
8
6
4
-cosine
2
0
0
10
20
30
40
50
Position along the Array
60
70
Array Programming
Vg2
Vt
Vtun
Vfg1
Vtun
M2
M1
I
+
I
To Circuit
Vfg2
To Circuit
-
V d2
Applications of Floating-Gate
Circuits in Systems
• Programmable Filters / Adaptive Filters
• Auditory / Accoustical Signal Processing
• Image Processing
• ADCs, DACs, etc.
Single-Transistor pFET Synapses
1. Store a weight value
2. Input x stored W
3. dW/dt = correlation of the
f( input , a given error signal)
Vdd
Vb
M2
Vtun1
Vg
M1
C1
Programmable and Adaptive
Analog Processing
Vd
(NSF CAREER)
Fourier-Based Programmable Filters
Vin
Bandpass Filters,
Exp Spaced
(Hard in DSP)
W11
W12
W13
W14
W15
W1n
Iout1
W21
W22
W23
W24
W25
W2n
Iout2
FG tuning of bandpass filters as well as coefficients…
(M. Kucic, P. Hasler, et. al. 1999-2001)
Analog Speech Front-End Blocks
Analog Cepstrum
VQ Classifier
Digital Signal
Processing
VQ
HMM
Cepstrum
Microphone
Analog HMM Classifier
Outputs
Image Sensor
Basis Functions
Time basis m
Time basis 1
Time basis 2
Time basis 3
Time basis 4
Digital
Control
Transform Imager
Vin
Iout
Floating-Gate
Element
Image Elements
Analog
Computing
Array
Our approach allows for
• Bio-inspired (Retina)
computation
• A programmable
architecture
• High-fill factor (~50%)
pixels like
CMOS imagers.
Can build in other
neuromorphic designs
into this structure
Transformed Output Image
Layout of Imager Cell
• Fill Factor ~ 50%
• Fabricated in 0.5mm CMOS
39l = 11.7mm
0.5mm
Photo
0.25mm
8mmx6mm 3.2mmx2.4mm
Array 128 x 128 512 x 512
(Size) (1.72mm2) (4.4mm2)
30l = 9mm
Adaptive Floating-Gate Circuits
• Full range of floating-gate circuits abilities
• Continuously programming (tunneling / injecting)
therefore, circuits at a slower timescale
Equilibrium point: Tunneling current = Injection current
Fundamental operation for adaptive systems:
Adaptive Filters, Neural Networks, Neuromorphic Models of Learning
AFGA Behavior
4.5
V in
C1
V dd
4
V fg
Vout
Vt
Output voltage (V)
V tun 1
3.5
Sine Wave + Voltage Step Input
3
2.5
Voltage Step Input
2
1.5
0
2
4
6
8
10
Input voltage (V)
12
14
16
Autozeroing Floating-Gate
Amplifier (AFGA)
Adaptive Diff-Pair
Vdd
Vt
Vtun
Vtun
I1
I2
Vdd
V1
V2
Vout1
Vout2
VtCM
Vtn
Common Mode Feedback
Can be directly extended to:
• Multipliers / Mixers
• “Bump” Circuits
Translinear Element using
Floating-Gate Devices
Vdd
Iin
Iout
C
V1
C
GND
V2
GND