Survey
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Ultra-low power and ultra-low cost wireless sensor nodes An integrated perspective Jan M. Rabaey EECS Dept. Univ. of California, Berkeley PicoRadio’s ─ The Original Mission Meso-scale low-cost radio’s for ubiquitous wireless data acquisition that • are fully integrated –Size smaller than 1 cm3 • minimize power/energy dissipation – Limiting power dissipation to 100 mW enables energy scavenging • and form self-configuring ad-hoc networks containing 100’s to 1000’s of nodes Still valid, but pushing the limits ever further The Incredibly Shrinking Radio OSC1 MOD1 OSC2 PA Test MOD2 4 mm LNA Test TX1 Passive Test Structures Receiver Env Det Test TX2 RF Amp Test fclock RF Filter Diff Osc RF Filter Env Det RF Filter Env Det LNA fclock RX RX On: On:33mW mW Off: Off:00mW mW Preamp PA Matching Network TX TX On: On:44mW mW Stby: Stby:11mW mW Off: Off:00mW mW • Technology: 0.13 mm CMOS combined with off-chip FBARs • Carrier frequency: 1.9 GHz • 0 dBm OOK • Two Channels • Channel Spacing ~ 50MHz • 40 kbps/channel • Total area < 8 mm2 Wireless Sensor Network Protocol Processor 64K memory Neighbor List Locationing Engine Base Band Voltage Conv GPIO Serial Interface Interface DW8051 μc System Supervisor Network Queues DLL In fab (Jan 04) Technology 0.13μ CMOS Chip Size 3mm x 2.75mm = 8.2 mm2 Transistor Count 3.2M Gate Count 62.5K gates Clocks Freqs 16MHz(Main), 1MHz(BB) On Chip memory 68Kbytes Core Supply Voltages 1V(High) –0.3V(Low) On_Power < 1 mW Standby Power mWs Integrates all digital protocol and applications functions of wireless sensor node Runs reliable and energy-optimized protocol stack (from application level down) The Road towards a First Integrated PicoNode Digital Network Processor 16kB CODE Flash Storage 4kB XDATA 256 DATA Chip Supervisor DW8051 20MHz Clock Source Serial Powertrain Solar Cell sfrbus or membus? FlashIF SIF ADC MAC Voltage Voltage Supply Voltage Supply Supply SIF LocalHW Serial GPIO ADC PHY Sensor1 Sensor2 User Interface PrgThresh0 PrgThresh1 OOK Receiver Tx0 Tx2 RF Transceiver OOK Transmitter SIF = sensor interface Energy-Scavenging becoming a Reality • Demonstrate a self contained 1.9GHz transmitter - powered only by Solar & Vibrational scavenged energy • Push integration limits - limited by dimensions of solar cell Front Front regulator cap Tx COB Light Level Low Indoor Light Fluorescent Indoor Light Partly Cloudy Outdoor Light Bright Indoor Lamp High Light Conditions Vibration Level 2.2m/s2 5.7m/s2 Duty Cycle 0.36% 0.53% 5.6% 11% 100% Duty Cycle 1.6% 2.6% Perspectives: Where are we heading? • Extrapolating towards the future: how far can we push cost, size, and power? – Ultra-dense sensor networks (“smart surfaces”) enabled by sub 10 mW nodes. – Cutting RF power by at least another factor of 5 (if not more) – Pushing the boundaries on voltage scaling • Focus on the application perspective – A Service-based Application Interface for Sensor Networks – Focus on issues such as portability, universality , scalability, and ad-hoc deployment An Application Perspective to Sensor Networks A plethora of implementation strategies emerging, some of them being translated into standards TinyOs/TinyDB The juggernaut is rolling … but is it the right approach? • Bottom-up definition without perspective on interoperability and portability • Little reflection on how this translates into applications A Quest: A Universal Application Interface (AI) for Sensor Networks • • • • Supports essential services such as queries, commands, time synchronization, localization, and concepts repository Similar in concept to the socket interface in the internet Provides a single point for providing interoperability Independent of implementation architecture and hardware platform – Allows for alternative PHY, MAC, and Network approaches and keeps the door open for innovation Application Application Interface Query/Command Service Layer Naming SNSP Time/Synchronization Network Layer Location SNSP Status (joint project with GSRC (ASV) and TU Berlin) • White paper completed and in feedback gathering mode (http://bwrc.eecs.berkeley.edu/research/picoradio/...) • Very positive support so far (both from industry and academia) • Next targets: – Further evolve document (start working group) – Demonstrate feasibility by implementation on at least two test beds – Address number of issues left open for research (e.g. implementation approaches for naming, synchronization, localization, and concept repository services) • Currently in process of acquiring funding (NSF, European Commission, CEC, …) Extrapolation of the low-power theme: Ultra-dense sensor networks • How to get nodes substantially smaller and cheaper (“real” mm3 nodes): get them closer, use lots of them, and make their energy consumption absolutely minimal (this is < 10 mW). • “Smart surfaces”: plane wings, smart construction materials, intelligent walls • How to get there? Go absolutely non-traditional! – Use non-tuned mostly passive radio’s – center carrier frequency randomly distributed – Use statistical distribution to ensure reliable data propagation On the Road: Reducing RF power by another factor of 5 • Providing gain at minimal current: The Super-regenerative Receiver 1500mm • 400mA when active (~200mW with 50% quench duty cycle) 1200mm • Fully Integrated Back from fab any day Realizing sub-50 mW receivers Example: sub-threshold RF oscillator using integrated LCs (in fab) Simulated Performance Supply voltage 0.5 – 1.2V Current consumption 150μA Oscillation frequency 1.5GHz Differential output swing 150mV (Vdd=500mV) Phase noise -100dBc/Hz @1MHz offset Next step: mostly untuned radio’s and lots of them Combine with purely statistical routing (in collaboration with Kannan) Ultra-Low Voltage (ULV) Digital Design • Aggressive voltage scaling the premier way of reducing power consumption; Performance not an issue • Our goals: design at 250 mV or below • Challenges: – Wide variation in gate performance due to variability of thresholds and device dimensions – Sensitivity to dynamic errors due to noise and particle-caused upsets (soft errors) Explore circuit and architecture techniques that deal with performance variations and are (somewhat) resilient to errors! TM TM Tcl TM Tcl’ asynch. TM Time reference Chip Supervisor synch. Idea: Self-adapting approach to ULV Status: White paper