Download ATLAS-CMS Electronics Workshop

• Why this
workshop?
1) To review the ATLAS and CMS upgrade
strategies and plans.
2) Explore areas of technology where
common approaches can be adopted.
3) Plan for potential common Research
and Development.
SLHC (~2014) peak luminosity upto 1.5●1035 cm-2 sec-1
(10X of LHC)
nominal
25 ns
new upgrade bunch structures
ultimate
& 25-ns upgrade
25 ns
50-ns upgrade,
no collisions @S-LHCb!
50 ns
50 ns
50-ns upgrade with 25ns collisions in LHCb
25 ns
Summary of the machine upgrade.
• two scenarios of L~1035 cm-2s-1 for which heat load
and #events/crossing are acceptable
• 25-ns option: pushes b*; requires slim magnets
inside detector, crab cavities, & Nb3Sn quadrupoles
and/or Q0 doublet; attractive if total beam current
is limited; transformed to a 50-ns spacing by
keeping only 1/2 the number of bunches
• 50-ns option: has fewer longer bunches of higher
charge ; can be realized with NbTi technology if
needed ; compatible with LHCb ; open issues are
SPS & beam-beam effects at large Piwinski angle;
luminosity leveling may be done via bunch length
and via b*
Changes required in ATLAS (Nigel Hessey).
Beampipe .
- Currently central part of ATLAS beampipe is Beryllium (Be), rest is Stainless Steel (SS)
- SS gives large backgrounds, especially to muon system
- SS gets activated
- Change to Al for ~2009
- Change to all Be for SLHC
- Be is expensive compared to SS, but cheap compared to muon chambers!
It gives a big reduction in background in critical areas of muon system (factor 2 or better).
Radiation damage, pile-up problem, power budget,
material budget are important issues.
Muon chamber .
If at low end and Be beampipe, most of MDT system can remain
At higher end, large fraction of MDT system needs replaced
Occupancy makes efficiency reduce to 50 %
MDT Electronics needs upgrading
For radiation damage
For data rates
Also considering reading out only regions with a trigger.
Changes required in ATLAS (Nigel Hessey).
Inner Detector
-TRT straws cannot cope with the rate
-Silicon Strips will be suffering from radiation damage and have too high occupancy
-Pixel (renewed) b-layer and the other 2 layers will be radiation damaged
All Inner Tracker to be replaced !!!
- All silicon tracker
Pixels + short strips (SS) + long strips (LS)
“Strawman” layout decided on (a straw man is easy to change)
4 pixel layers
3 short strip (SS) layers
2 long strip (LS) layers
FARTHOUAT, Philippe (CERN)
On-detector power dissipation.
Power IN → cables (material).
Power OUT → cooling pipes (material ).
CMS
Tracker
ATLAS
Power
Current
Pixel
3 kW
1.5 kA
Si Strips
31 kW
15 kA
116 kW
46 kA
EM Calorimeters ECAL
Pixel
Si Strips
TRT
Larg*
Power
Current
6 kW
18 kW
22 kW
140 kW
3.7 kA
6 kA
6.5 kA
27 kA
* Including the hadronic end-cap
Power dissipated by the front-end electronics
Marc Weber, RAL
Serial powering.
SCT| SLHC
8V| 2V
4V| 1V
Current source
(external power
4V| 1V
supply)
0V| 0V
Chain of modules at different voltages; “recycle” current
Chips on a module are connected in parallel (as usual)
Analog ground, digital ground and HV ground are tied together for each module (as usual) 
floating HV supplies
AC-coupled read-out !!!
F.Faccio (CERN)
100m
Important considerations:
Magnetic field, Radiation
and Material Budget, Noise, plus
EMI if inductor-based DC/DC
24 or 48 V
PP
0.5-2m
1.5 or 3 V
Module
DC/DC
(with DC/DC)
AC/DC
Inductor-based DC-DC converter.
Low voltage vs
High current
High voltage vs
Low current =
Low power loss
P = I2●R long wire
• Aiming at demonstrating the feasibility of a fully integrated
(except L and passive components) DC-DC buck converter
air core inductor
high-V CMOS
technology with
radiation tolerant
design
Vin=12-24 V
Vout=1.5-3V
I=1-2A
Switching noise
Controller architecture
8
Switched Capacitor DC-DC converters.
Maurice Garcia-Sciveres (Lawrence Berkeley National Laboratory)
Vd
+
-
+
-
Phase 1 - Charge
+
-
-Same 50V 0.35mm HV CMOS
•
process
-Sized for 1A output. 4.3 x 4.9 mm
Vd
- Contains auxiliary circuits.
- All capacitors external
- All clocks external
1
+
-
+
-
Load
1
+
-
• Phase 2 - Discharge
1
+
-
+
-
+
-
+
-
Load
+
-
1
+
-
Load
VLSI technology choice.
- IBM 130 nm CMOS has been found suitable for SHLC
upgrade.
-It is radiation hard enough therefore we can use
commercial libraries for the most of the digital blocks.
- Moreover, this technology has a lot of attractive
desing features.
- CERN has signed a long-term contract with IBM
covering both 130nm and 90 nm technologies.
- MIC group of CERN is ready to organize MPW runs if
there will be sufficient participants in high-energy
physics community.
- Some ATLAS group are about to start redesign of their
present front-end chips into IBM CMOS 130nm
technology. These are:
1) ATLAS Pixel Detector Front-end chip
(K. Einsweiler, LBNL).
2) ATLAS Strip Detector Front-end chip ABC-N
(W. Dabrowski , Krakow).
Common IP blocks in the Design Library.
•
Digital
–
–
–
–
–
•
Analog
–
–
–
–
–
•
Memories (SEU tolerant), serializers
PLL, DLL frequency multipliers
Slow control protocol (target low power + SEU tolerance)
LVDS drivers : customized for minimal power / standard ?
Codecs :
Bandgap,
we are involved
voltage regulators,
DAC, temperature monitoring
ADCs : what power/#bits/speed ?
For when the Universal preamp, tunable by slow control ??
Consensus to carefully minimize power
–
Is it compatible with « standard » cells?
• Based on IBM 0.13 µm. Portability to other technologies ?
•
IP documentation, responsibility, maintenance ??
–
Regular workshops
3D and SOI Technology
for Future Pixel Detectors
Ray Yarema
Fermilab
Common ATLAS CMS Electronics Workshop
At CERN
March 19-21, 2007
Monolithic Active
Pixel Sensors
(MAPS)
Sensing Diode
Active Pixel Sensor in SOI
0.15mm Fully-Depleted SOI CMOS process,
Metal layers
Polysilicon
1 Poly, 5 Metal layers (OKI Electric Industry Co. Ltd.).
- +
- +
3 NMOS trans. in pixel
N+ Well
P+ Well
- +
- +
+
5-20 um
- +
P- epi
- +
- +
P++ substrate
- +
N+
PMOS and
NMOS
transistors
Particle
Pixel Cross Section (not to scale)
Pixel reset
Buried oxide
200 nm
Charge released
along track
Detector signal
Is proportional
To substrate thickness
Pixel output
Diode
sensor
Pixel row sel
Advantages:
3 NMOS transistors in Pixel
* 100% fill factor
* NMOS + PMOS transistors
* Large signal
* Faster charge collection
Thin top layer has silicon islands in which PMOS and NMOS transistors are built.
A buried oxide layer (BOX) separates the top layer from the substrate.
The high resistivity substrate forms the detector volume.
The diode implants are formed beneath the BOX and connected by vias.
ASI Process
0.18mm partially-Depleted dual gate SOI CMOS
process,Dual gate transistor (Flexfet),
No poly, 5 metal (American Semicondutor / Cypress
Semiconductor.)
• ASI process based on dual gate transistor called a Flexfet.4
– Flexfet has a top and bottom gate.
– Bottom gate shields the transistor channel from charge build up in the
BOX caused by radiation.
– Bottom gate also shields the transistor channel from voltage on the
substrate and thus removes the back gate voltage problem.
Vertical Scale Integration (3D)
– Increased circuit density due to multiple tiers of
electronics
– Independent control of substrate materials for each of the
tiers.
– Ability to mate various technologies in a monolithic
assembly
• DEPFET + CMOS or SOI
• CCD + CMOS or SOI
• MAPS + CMOS or SOI
Optical In
Power In
Opto Electronics
and/or Voltage Regulation
Optical Out
Digital Layer
Reduce R, L, C for higher speed
Reduce chip I/O pads
Provide increased functionality
Reduce interconnect power and
crosstalk
Analog Layer
50 um
Sensor Layer
Physicist’s Dream
15
3D Stack with Vias
Pixel cell:
*175 transistors
in 20 µm pixel.
*Unlimited use
of PMOS and
NMOS.
*Allows 100 % diode
fill factor.
Vias: 1.5 um dia
by 7.3 um long
Via using
oxide etch
process
(Lincoln
Labs)
20 um
20 um
Tier 3
Tier 2
Tier 1
Typical diameters are 1-2 microns
High resistivity substrate
BOX
Two Different 3D Approaches for HEP
• Die to Wafer bonding
– Permits use of different size wafers
– Lends itself to using KGD (Known Good Die) for higher
yields
• Wafer to Wafer bonding
– Must have same size wafers
– Less material handling but lower overall yield
KGD
Die to wafer bonding
Dice/test
Wafer to wafer bonding
Key Technologies
2) Wafer thinning
Through wafer vias typically have an 8 to 1 aspect ratio. In order to
keep the area associated with the via as small as possible, the wafers
should be thinned as much as possible. Thinning is typically done by a
combination of grinding, lapping, and chemical or plasma etching.
Photos from
MIT LL
Six inch wafer thinned to 6 microns and mounted to 3 mil kapton.