Download Detailed Design Review Presentation (SD I)

Detailed Design Review
MSD Project 10236
Configurable Control Platform
for Unmanned Vehicles
Joe Pinzone
Alex Mykyta
Roberto Stolfa
Robert Ghilduta
Jason Stanislawski
System Overview
System Overview
Control Code Processor (CCP)
Gumstix: TEXAS INSTRUMENTS
OMAP3530
• ARM Cortex-A8 GP CPU
• C64x DSP
• Store/execute Simulink control code
• 256MB flash (OS / Control Code)
• 256MB RAM
• Power management IC
• High-speed serial bus to I/O Controller
System Overview
Input/Output Controller (IOC)
XILINX SPARTAN 3E FPGA w/ PLASMA uC CORE
•Arbitrates sensor and actuator input/output
•Provides sensor data to CCP in common
format through shared, dual-port memory
•Provides analog and digital I/O interface
connectors, broken out on I/O Breakout Board
System Overview
I/O Breakout Board (IOB)
• The only vehicle-specific hardware
•Breaks out IOC header to individual
sensors and actuators
• Physically separate package from
Controller Platform
• Generally no processing done here
System Overview
Power, Control Code Processor, I/O Controller are physically:
–
–
–
separable
stacked
enclosed
System Overview
Power, IOC, CCP = Vehicle Controller Platform, separate from IOB
Power
*All values are worst case
Power
Rail
Current Required
Power Required
1.2 V
0.088 A
0.106 W
2.5 V
0.045 A
0.113 W
3.3 V
0.322 A
1.060 W
4V
0.400 A
1.600 W
5V
0.129 A
0.643 W
*All values are worst case
Power
TPS43000-Based
5V/0.25A
IOB, ADC, DAC
4V/0.5A
CCP
SW-MODE PSU
OUTPUT 5V/1.5A
3.3V/0.5A
Battery Pack
IOC
2.5V/0.1A
1.2V/0.1A
Power
FRONT END CONDITIONING
TEXAS INSTRUMENTS TPS43000
• SEPIC (buck/boost) configuration
• 1.8 – 9V Input
• 6A output with proper FET switches
• Synchronous Rectification (+eff)
TPS43000 (PSU FRONT END)
Power
SECONDARY STAGE
LINEAR REGULATORS
LM317 ADJ. LDO
• Low-drop-out
• Vout 1.25 –> 5+ volts
• Use for 5V, 4V
• Up to 1.5A output
TLV70012 for 1.2V/200mA
TLV70025 for 2.5V/200mA
TPS73733 for 3.3V/0.50A
Power Summary
Max
Nom
Units
Total Useful Pwr
3.524
2.890
Watts
Total Current
0.984
0.792
Amps
Power to LDOs
4.918
3.958
Watts
Efficiency of SM
0.900
0.900
Total Reqd. Pwr
5.464
4.398
Watts
Supply Voltage
4.800
4.800
Volts
Supply Current
1.138
0.916
Amps
Battery Capacity
2.700
2.700+
A-h
Est. Time
2.372
2.947
Hours
Est Efficiency
0.645
0.657
Nomenclature
Firmware:
– Program code that runs on the embedded processors. This does not
include the Control Code, which will always be referred to specifically.
Rigidware:
– The HDL containing the “image” of the FPGA gate configuration. This
may contain RAM/ROM initialization images and basic boot loader to
initialize and load the stored firmware. This term generally pertains only
to the IOC, since it is the only programmable-logic device in the system.
Software:
– Any program that runs on the user PC for the purpose of programming,
configuring, compiling, or monitoring the embedded system.
IO Controller Module
• Arbitrates IO from the CCP
• Physically separable from CCP
– Can be used as independent data logger or used
in future projects.
• Implemented using a Xilinx Spartan 3E FPGA
(XCS500E-PQ208)
FPGA Selection
• FPGA chosen for highest gate & largest pin count
• BGA is not desirable due to board routing complexity
Package
Device
VQ100
CP132
TQ144
XC3S100E
X
X
X
XC3S250E
X
X
X
XC3S500E
X
X
XC3S1200E
XC3S1600E
PQ208
FT256
FG320
FG400
X
X
X
X
X
X
X
X
X
X
FG484
X
IOC Rigidware
SPI Bus:
PM Storage & SD Card
To CCP
High Speed Serial
IRQ
IRQ
Tx
DO
Serial
Controller
Rx
CK
DI
CE
A
Dedicated
UART
D
Dual Port RAM
1kB
~40kB RAM
NOTE: All IO Ports, ADC Controller, Dedicated UART and
SD/PM SPI module are capable of generating interrupts.
SPI Master
System Clock
Counter
D
A
Plasma Core
CK
SO
SI
ADC
Controller
CS-ADC
CS-DAC
PWM Reader
8
PWM
Generator
8
IO Port
8
IO Port
8
IO Port
8
IO Port
8
Main RAM
SPI Bus:
PM Storage & SD Card
RQ
IRQ
DO
CK
DI
CE
~40kB RAM
SPI Master
D
A
Plasma Core
System Clock
Counter
• XC3S500E has 45KB of
Block Memory
• Approximately 40 KB
will be used for Plasma
CPU
• RAM preloaded with
boot loader
SPI FLASH & MMC
• Application code is
stored on SPI Flash
SPI Bus:
PM Storage & SD Card
– Boot loader loads
application into RAM
RQ
IRQ
DO
CK
• Same SPI bus is used for
an SD card for logging
DI
CE
~40kB RAM
SPI Master
D
A
Plasma Core
System Clock
Counter
– All typical SD cards
support standard MMC
protocol
System Clock Counter
SPI Bus:
PM Storage & SD Card
RQ
IRQ
DO
CK
DI
CE
~40kB RAM
SPI Master
D
A
Plasma Core
System Clock
Counter
• Provides timing
information
• Sourced from 50 MHz
clock which allows for
integer division to
decade increments of
time.
Dedicated UART
To CCP
High Speed Serial
IRQ
IRQ
Tx
Rx
Serial
Controller
A
Dedicated
UART
D
Dual Port RAM
1kB
All IO Ports, ADC Controller, Dedicated UART and
SPI module are capable of generating interrupts.
• Hardwired
to USB-UART
SPI Bus:
PM Storage & SD Card
transceiver
• Load new application
code
DO
• Debug system
CK
DI during
CE
operation
~40kB RAM
D
SPI Master
System Clock
Counter
CCP Communication
To CCP
High Speed Serial
IRQ
IRQ
Tx
Rx
Serial
Controller
A
Dedicated
UART
D
Dual Port RAM
1kB
All IO Ports, ADC Controller, Dedicated UART and
SPI module are capable of generating interrupts.
• Dual port
ram allows for
SPI Bus:
PM Storage & SD Card
independent
operation
• High speed serial
interface used
to access
DO
shared RAM
CK
DI
CE
• Interrupt
signals
provided to and from
System Clock
~40kB RAM
SPI
Master
CCP
Counter
D
Dedicated
UART
Dual Port RAM
1kB
~40kB RAM
SPI Master
System Clock
Counter
Analog Controller
NOTE: All IO Ports, ADC Controller, Dedicated UART and
SD/PM SPI module are capable of generating interrupts.
D
• Finite state machine
responsible for
acquiring analog data
from ADC
A
Plasma Core
CK
SO
SI
ADC
Controller
CS-ADC
CS-DAC
PWM Reader
8
PWM
Generator
8
– Data available for direct
access from CPU address
IO Port
IO Port
space IO Port
• Configures reference
voltage DAC
8
8
8
Dedicated
UART
Dual Port RAM
1kB
~40kB RAM
SPI Master
System Clock
Counter
PWM Controller
NOTE: All IO Ports, ADC Controller, Dedicated UART and
SD/PM SPI module are capable of generating interrupts.
D
• FSM that arbitrates
servo PWM generation
and reading
• Generator is
configurable to provide
servo format or full
range duty cycles
A
Plasma Core
CK
SO
SI
ADC
Controller
CS-ADC
CS-DAC
PWM Reader
8
PWM
Generator
8
IO Port
8
IO Port
8
IO Port
8
Configurable IO Ports
A
D
A
I2C
Core
SPI Core
CE
CK
DO
D
DI
SDA SCL
A
D
UART
Tx
Rx
A
D
GPIO
8
Special Function
Select
• Each pin can be
configured as input,
output, or special
function
• Special functions
include configurable
SPI, I2C and UART
modules
• IP provided by
OpenCores
d
D
A
Configurable IO Ports
Plasma Core
• MAV peripheral set only
requires 1 port
• Preliminary logic estimates show that 5 ports should
be possible
WM
nerator
8
IO Port
8
IO Port
8
IO Port
8
IO Port
8
IOC Hardware
Header to CCP
High Speed
Serial
(or future GPMC)
Rx Tx
USBàDual
UART
FT2232
USB
USB Mini-B
JTAG Header
EEPROM
AT93C46E
IRQ
IRQ
Rx
SD/MMC
Card
socket
SPI FLASH
PM Storage
SST25VF032B
Tx
SPI
JTAG
JTAG
FPGA Config. IC
XCF02S
JTAG
Config.
14.7456 MHz Clock
Xilinx Spartan 3E
XC3S500E-4
PQ208
50.0000 MHz Clock
SPI
8 Channel 16-bit
ADC
ADS1178
[-]
Voltage
Reference
DAC
TLV5623C
IO Ports
Bidirectional
Voltage
Translator
TXB0108
[+]
8
8
PWM In
8
Analog Header
Bidirectional
Voltage
Translator
TXB0108
Bidirectional
Voltage
Translator
TXB0108
Bidirectional
Voltage
Translator
TXB0108
PWM Out
8
8
Bank
Vref
8
Bank
Vref
Digital IO Header
8
Bank
Vref
8
Bank
Vref
Programming Interface
• USBàUART converter does most of the work for us
• PM FLASH is programmed from UART
• Second UART is provided for CCP configuration
Header to CCP
Rx Tx
USBàDual
UART
FT2232
USB
USB Mini-B
EEPROM
AT93C46E
AG Header
High Speed
Serial
(or future GPMC)
SPI FLASH
PM Storage
SST25VF032B
IRQ
IRQ
Rx
Tx
SD/MMC
Card
socket
SPI
JTAG
JTAG
FPGA Config. IC
JTAG
14.7456 MHz Clock
FLASH & SD Card
• SST’s 4MB FLASH stores application program
• Shares SPI Bus with SD Card for data logging and
removable storage
Header to CCP
Rx Tx
USBàDual
UART
FT2232
USB
USB Mini-B
EEPROM
AT93C46E
AG Header
High Speed
Serial
(or future GPMC)
SPI FLASH
PM Storage
SST25VF032B
IRQ
IRQ
Rx
Tx
SD/MMC
Card
socket
SPI
JTAG
JTAG
FPGA Config. IC
JTAG
14.7456 MHz Clock
CCP Interface
• High speed serial interface to CCP along with
interrupt requests
• Pins on FPGA and header are reserved specifically for
implementing GPMC in the future
Header to CCP
Rx Tx
USBàDual
UART
FT2232
USB
USB Mini-B
EEPROM
AT93C46E
AG Header
High Speed
Serial
(or future GPMC)
SPI FLASH
PM Storage
SST25VF032B
IRQ
IRQ
Rx
Tx
SD/MMC
Card
socket
SPI
JTAG
JTAG
FPGA Config. IC
JTAG
14.7456 MHz Clock
(or future GPMC)
USBàDual
UART
FT2232
FPGA Configuration
USB
USB Mini-B
JTAG Header
EEPROM
AT93C46E
IRQ
IRQ
Rx
Tx
JTAG
JTAG
FPGA Config. IC
XCF02S
JTAG
Config.
Xilinx Spartan 3E
XC3S500E-4
PQ208
• On power-up, FPGA is automaticallySPIconfigured by
the XCF02S which stores rigidware.
Voltage
8 Channel 16-bit
Reference
IO Ports
• Rigidware can be changed
interface
ADC via JTAG
DAC
ADS1178
TLV5623C
Bidirectional
G
USBàDual
UART
FT2232
USB
EEPROM
AT93C46E
IRQ
IRQ
Rx
Tx
Analog to Digital Converter
JTAG
FPGA Config. IC
XCF02S
JTAG
Config.
Xilinx Spartan 3E
XC3S500E-4
PQ208
SPI
8 Channel 16-bit
ADC
ADS1178
[-]
Voltage
Reference
DAC
TLV5623C
IO Ports
Bidirectional
Voltage
Translator
TXB0108
[+]
8
SPI
8
PWM In
8
Analog Header
14.7456 MHz Clock
• Simultaneous samples of 8
channels
• Supports differential inputs
• Adjustable sampling range
50.0000 MHz Clock
– Range is digitally controlled
Bidirectional
Bidirectional
Bidirectional
by adjacent
Voltage
Voltage DACVoltage
Translator
TXB0108
Translator
TXB0108
Translator
TXB0108
PWM Out
8
8
Bank
Vref
8
Bank
Vref
Digital IO Header
8
Bank
Vref
8
Bank
Vref
onfig. IC
02S
JTAG
Config.
14.7456 MHz Clock
Xilinx Spartan 3E
XC3S500E-4
PQ208
Digital IO
50.0000 MHz Clock
SPI
el 16-bit
DC
1178
Voltage
Reference
DAC
TLV5623C
IO Ports
Bidirectional
Voltage
Translator
TXB0108
[+]
8
Header
• PWM signals connected
directly to IOB (3.3v levels)
• Configurable IO Ports have
adjustable logic levels.
PWM In
8
Bidirectional
Voltage
Translator
TXB0108
PWM Out
8
8
Bank
Vref
8
Bank
Vref
– User supplies voltage
Bidirectional
Bidirectional
reference
Voltage
Voltage
Translator
Translator of
– TXB0108
detects direction
TXB0108
TXB0108
communication without the
need for direction control
Digital IO Header
8
Bank
Vref
8
Bank
Vref
Logic Cost Analysis
LUTs
Plasma Core
3306
CCP Interface
300
PWM IO Controller
300
Analog Controller
230
Configurable IO Port
710
Number of IO Ports:
5
Total LUTs Used: 7686
Available LUTs
9312
Remaining LUTs 1626
• Design with 5 IO ports
uses approximately 80%
of available logic
– 20% for uncertainty in
estimates and potential
overhead for PAR of
large designs.
Throughput Estimation
• Dummy DAQ program written for MAV set of
peripherals
– Single sample can be executed in ~420 clock cycles
@ 25 MHz
– Assuming SPI communication to IMU is done
without interrupts, CPU must stall for duration of
transfer (~200 cycles @ 2 MHz)
– Results in theoretical sample rate of 30 kHz
I/O Breakout Board
I/O Breakout Board
DEVICE LIST FOR UAV IOB
Analog Devices IMU
Tyco Electronics GPS
Airspeed Differential Pressure Sensor
Altimeter Absolute Pressure Sensor
Thermistor
I/O Breakout Board
TI ADS1178
Diff V_IN max.
V_IN max.
V_IN min.
( V+) - ( V-)
V+ or VV+ or V-
+/- 3.1 V
5.1 V
- 0.1V
Sensor
Vout Max
Vout Min
V-
Vref
Airspeed
4.7
0.2
2.45
2.25
Altitude
4.5
0.5
2.5
2.0
Temperature
4.986
0.229
2.493
2.38
V- Calculation
Airspeed Sensor:
(4.7V + .2V)/2 = 2.45V
Altitude Sensor:
( 4.5V + .5V)/2 = 2.5V
Temperature Sensor:
(4.986V + .229V) / 2 = 2.493V
Vref Calculation
Airspeed Sensor:
(4.7V - .2V)/2 = 2.25V
Altitude Sensor:
( 4.5V - .5V)/2 = 2.0V
Temperature Sensor:
(4.986V -.229V) / 2 = 2.38V
I/O Breakout Board
Digital Peripherals:
Tyco Electronics GPS – UART (NMEA)
Analog Devices IMU – SPI
Telemetry (P10231) – I2C, SPI, UART
I/O Breakout Board
MUX IC Manual Override:
2 – Quad 2 to 1 multiplexers
I/O Breakout Board
Molex 24 position connector
Pitot-Static Probe (Airspeed)
Ram Air Pressure
Stagnation (Static)
Standard DSUB Connectors
Control Code Processor
CCP Overview
• OMAP
– ARM
• Linux
– Fixed point TI DSP
• DSP/BIOS
– running RT workshop Control System
• Sensor data is memory mapped with DMA
from the IO controller over a dedicated link
Incremental Design
• Gumstix (target for MSD 2)
– Ready-to-run system on a module
– Self-sustained (low to no dependency count)
– Readily available, non-existent lead time
• Topedo SOM
– Smaller + lower power consumption than Gumstix
– Higher throughput achievable
• Custom Board
– Cheapest, fastest, most efficient yet most complicated
solution
• An implementation meeting every need marked
“HIGH” has to be met before proceeding
Gumstix
•
•
•
•
Board requires nothing power
2 expansion slots breakout McBSP and GPMC
Board lacks DMA support for GPMC
Implementation will use DMA with McBSP
– DMA will be configured to routinely read data from
McBSP and copy to a location in memory without
interrupts
– Slower than GPMC, uses less pins
• Interface is well known
• Target development time: 4 weeks
Torpedo
• Second revision
– Motivations: smaller board, GPMC with DMA
becomes possible
• Uses OMAP3530 (just as the Gumstix)
• Product comes with verified schematics and
layouts
• Release date - late December
• Expected price - $150
• Target development time: 4 weeks
Custom board
• Reasons to improve on Torpedo
– OMAP3525 is cheaper than the 3530
– TPS65920 consumes less power, requires less
layout area (fewer discrete components are
required)
• Development time
– Software and interface overlaps with Torpedo
– Schematics and layout can mostly be reused
McBSP with DMA
McBSP cont’d
• Multi-channel Buffered Serial Port
– (High speed serial)
– Asynchronous Synchronous supported
• DMA would be used to limit the use of the
ARM processor
• Maximum clock speed (bit speed) can use L4
clock (96MHz)
– FPGA may not be able to reach this
• Bit speed may need to be halved and channel count
double
GPMC
GPMC cont’d
• General Purpose Memory Controller (Interface)
– Typical SRAM interface
• Asynchronous/Synchronous supported
• Allows external memory devices to be mapped
into OMAP’s memory address space
• Burst speeds (where Row address is latched) of
400MB/s supported
– in reality speed is limited by FPGA’s IO buffers
• Gumstix cannot use this interface because DMA
pins that would be used to notify L2 Memory of
outdated data are not accessible
Control Code Processor - Software
•
Matlab Integration


End User Workflow
Software Required:




Matlab/Simulink
Real-time Workshop
TI C6x DSP Toolchain
Code Sourcery
ARM Toolchain
Vehicle Profiler
Control Code Uploader
Control Code Processor OS

Linux


OpenEmbedded
Framework
TI DSP-Bridge
Control Code Loader Daemon
Control Code Wrapper
Budget
Controller Platform
ITEM
Power Controller
Linear Regulators
Switching Components
Spartan 3E FPGA
FPGA Config IC
FLASH Boot Memory
Oscillator
Oscillator
USB to dual RS232
EEPROM for FT2232
8ch 16-bit ADC
Bidirectional Voltage
Translator
8-bit DAC
Gumstix
Gumstix Dev Board
Board to Board Conex
Misc Passives
External Connectors
Enclosures
PCB FAB
Control Platform Total
PRODUCT COST
EST
$4.50
$2.80
$7.00
$24.90
$4.25
$2.56
$2.63
$2.63
$6.99
$0.37
$25.42
$2.00
$2.48
$170.00
$0.00
$25.00
$30.00
$50.00
$20.00
$116.00
$499.53
OUR COST EST
$0.00
$0.00
$7.00
$24.90
$4.25
$0.00
$2.63
$2.63
$6.99
$0.37
$0.00
$0.00
$0.00
$170.00
$50.00
$25.00
$30.00
$50.00
$20.00
$248.00
$641.77
Budget
UAV I/O Breakout
24 pin, 0.1" Header Pins
Dual Flip-Flop
Quad 2 to 1 Multiplexer
10k POT
Airspeed Sensor
Altitude Sensor
Temperature Sensor
Analog Devices IMU
GPS
Pitot Static Probe
Mounting Chuck
6.84
1.00
0.40
6.68
11.70
5.80
34.00
$527.44
61.50
160.00
35.00
$6.84
1.00
0.40
$6.68
$0.00
$0.00
$0.00
$0.00
$0.00
$0.00
$0.00
UAV IOB Total
$527.44
$13.52
Budget
Total
Final Product
This Project
$1,026.97
$655.29