Survey
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Multidimensional empirical mode decomposition wikipedia , lookup
Time-to-digital converter wikipedia , lookup
Dynamic range compression wikipedia , lookup
Pulse-width modulation wikipedia , lookup
Immunity-aware programming wikipedia , lookup
Rectiverter wikipedia , lookup
Mod5282 Hardware Design Notes Application Note Revision 1.0 January 27, 2004 Document Status: Release Table of Contents Introduction......................................................................................................................... 3 Interrupt Signals.................................................................................................................. 3 QSPI.................................................................................................................................... 3 Analog to Digital Inputs...................................................................................................... 4 Chip Selects ........................................................................................................................ 4 Reset Signals....................................................................................................................... 4 Bus Control Signals ............................................................................................................ 5 TIP Signal and External Data Bus Connections ............................................................. 5 System Clock Signal ........................................................................................................... 6 UARTS ............................................................................................................................... 6 CAN Interface..................................................................................................................... 6 Introduction This document provides hardware design information, tips and guidelines for using the Mod5282 with external hardware. This document uses the following terminology: Output: indicates an output from the microprocessor. Please reference the electrical characteristics for the specific signal in the Motorola ColdFire 5282 User’s Manual. Input: indicates an input to the Mod5282. Most inputs will have a pull-up resistor as indicated. Asserted: The asserted state of a signal depends upon the signal description. If a signal is active low as defined by the ‘*’ character preceding the signal name, then the asserted state is low. If a signal is active high, then the asserted state is high. Negated: The negated state of a signal depends upon the signal description. If a signal is active low as defined by the ‘*’ character preceding the signal name, then the negated state is high. If a signal is active high, then the negated state is low. Interrupt Signals Four interrupt signals are available on connector J2: *IRQ1, *IRQ3, *IRQ5 and *IRQ7. These signals are inputs pulled to 3.3V through individual 4.7K resistors. QSPI The QSPI signals are configured as show in the table below. Signal SPI_CLK SPI_DIN SPI_DOUT *SPI_CS0 *SPI_CS1 *SPI_CS2 *SPI_CS3 Description Output. Serial clock Floating Input. Serial data input Output. Serial data output. Output. Peripheral chip select. Output. Peripheral chip select. Output. Peripheral chip select. Output. Peripheral chip select. Analog to Digital Inputs The Mod5282 has 8 ADC inputs. These signals go direct to the processor – there is no filtering circuitry on the module. The ADVCC reference input signal on the Mod5282 is tied to 3 inputs on the processor: VDDH, VDDA and VRH as shown below. Note that the diagram below shows the circuitry on the Mod5282, not the development board. If you do not connect a reference voltage to ADVCC, then the reference will run from the 3.3V rail through the diode. Alternatively, you can connect your own reference of up to 5VDC to ADVCC. ADVCC VCC3V CR1 DIODE + C12 0.1uf C32 10uF GND GND AN0 AN1 AN2 AN3 AN5 2 AN5 3 AN5 5 AN5 6 GND GND P2 R5 P4 T5 T3 R2 T2 R1 R4 T4 P3 R3 P5 T1 VDDH VDDA VRH VRL AN0 AN1 AN2 AN3 AN5 2 AN5 3 AN5 5 AN5 6 VSSA VSSA ColdFire 5282 Chip Selects The chip selects *CS1, *CS2 and *CS3 are outputs. Reset Signals Signal *RSTI Description Reset Input *RST0 Reset Output Implementation Input with 4.7k pull-up to 3.3V. Asserted to enter reset exception processing. Output from processor. Automatically asserted with *RSTI. Negation indicates that the PLL has regained it’s lock. Bus Control Signals Signal R/*W Description Read/Write *OE Output Enable *BS2, *BS3 *TIP Byte strobes Transfer in Progress *TA Transfer Ack *TEA Transfer Error Ack Implementation Output. Indicates the direction of the data transfer on the bus. Output. Indicates when an external device can drive data on the bus. Output. Defines the byte lane of data on the data bus. Output. Asserted to indicate a bus transfer is in progress. Negated during idle bus cycles. Input with 4.7k pull-up to 3.3V. Indicates that the external data transfer is complete and should be asserted for one clock. Input with 4.7k pull-up to 3.3V. Indicates than an error condition exists for the bus transfer. TIP Signal and External Data Bus Connections The *TIP signal can used to control an external data bus buffer for the data bus signals. An example circuit design can be found on the Module Development Board schematic. An external data bus buffer is recommended for any designs that use data bus signals D16 - D31 VCC3V 42 D31 D29 D30 D27 D28 D25 D26 D23 2 3 5 6 8 9 11 12 VCC3V 31 V+ V+ G Y1 DIR Y2 Y3 A1 Y4 A2 Y5 A3 Y6 A4 Y7 A5 Y8 A6 A7 A8 U9A PI74LPT16245 7 48 1 47 46 44 43 41 40 38 37 TIP R/W DB31 DB29 DB30 DB27 DB28 DB25 DB26 DB23 D24 D21 D22 D19 D20 D17 D18 D16 13 14 16 17 19 20 22 23 18 V+ V+ G Y1 DIR Y2 Y3 A1 Y4 A2 Y5 A3 Y6 A4 Y7 A5 Y8 A6 A7 A8 U9B PI74LPT16245 25 24 36 35 33 32 30 29 27 26 TIP R/W DB24 DB21 DB22 DB19 DB20 DB17 DB18 DB16 System Clock Signal The system clock pin provides an output of 66.355 MHz. The system clock on the Mod5282 is derived from a 3.6864 MHz crystal, which is fed into the ColdFire 5282 PLL. UARTS The Mod5282 has 3 UARTs, designated as UART 0, UART 1 and UART 2. All the UART signals go direct to the 5282 processor. It is recommended that you include a pull-up resistor of 10k ohms for any UART RX signals that are not used (either as UARTs or an alternate function). The third UART interface, designated as UART 2, can be configured by the 5282 processor to use either the I2C pins, or the CAN pins. The NNDK Module Development Board has 330 ohm resistors in series with the UART RX lines. This was done to make the development board compatible with the ColdFire 5282, which has a maximum current specification of 25mA if the input voltage is above 3.3VDC. The resistors are not required for the ColdFire 5272. The resistors are present on board revisions 1.1 and later. If you are designing exclusively with the Mod5282, then the use of a 3.3V transceiver is recommended. CAN Interface The CAN signals are routed directly from the 5282 processor.