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Electronic Circuits Laboratory EE462G Lab #7 Using NMOS Transistors to Build Logic Gates Kevin D. Donohue, University of Kentucky 1 Logic Device Nomenclature 5-Volt Positive logic: Logic gate circuitry where a 5V level corresponds to logic 1 and 0V level corresponds to logic 0. Truth Table: Input-output description of gate in terms of logic symbols. VIL: Highest input voltage guaranteed to be accepted as a logic 0. VIH: Lowest input voltage guaranteed to be accepted as a logic 1. VOL: Highest logic-0 output voltage produced (given inputs are consistent with VIL and VIH). VOH: Lowest logic-1 output voltage produced (given inputs are consistent with VIL and VIH). Kevin D. Donohue, University of Kentucky 2 FET Operation as a Logic Device Input values will change between 0 volts (VGS < Vtr) and 5 volts (VGS> VDS+Vtr). Thus, the NMOS transistor will operate primarily in the cutoff and triode regions. The circuit below represents a logic inverter. VDD RD Three Regions of Operation: D RG + Vin - Cutoff region (VGS Vtr) + G Vout S - Load Triode region (VDS VGS - Vtr ) Saturation (VGS - Vtr VDS ) Kevin D. Donohue, University of Kentucky 3 Transfer Characteristic Obtain relationship between Vin to Vout in cutoff region. Vin VGS Vtr I D 0 VDD RD I D VDS VDD VDS Vout Vout VDD RD ID D RG + Vin - VDD=VOH + What would VIL be in this case? G Vout S Load - Kevin D. Donohue, University of Kentucky Vtr Vin 4 Transfer Characteristic Obtain relationship between Vin to Vout in Triode region. Vin VGS VDS Vtr I D KpVGS Vtr VDS VDD RD I D VDS VDD VDD D RG + Vin - where 1 KpVGS Vtr VDD=VOH What would VIH be in this case? + G Vout ron RD VDD VDS 1 Vout VOL RD ron 1 ron Vout RD ID V DS ron Load VOL S - Vtr Kevin D. Donohue, University of Kentucky Vin 5 Truth Table The truth table with logic input-output relationships are shown below: Input Output Vin Vout VIL < Vtr VOH VDD Vout VDD=VOH 0 1 1 0 VIH > Vtr VOL Vtr VDD VOL RD 1 r on Vin Kevin D. Donohue, University of Kentucky 6 Transition Between States The stray capacitance in the NMOS device limits the speed of the transition between states of the inverter. Capacitive effects between the drain and source, and gate and source create delays (propagation delay) between input and output transitions, and nonzero rise times and fall times of the output transitions. These quantities are defined below: Vin 50% tfdelay trdelay turn off turn on 50% t Vout 90% 50% 10% trise t PD 90% 50% 10% tfall Kevin D. Donohue, University of Kentucky Propagation delay is taken as the average between the 2 edge delays trdelay tfdelay 2 t 7 Transition Low to High The equivalent circuit below represents the NMOS inverter going into a logic 1 output state. Circuit equations are: V V CR V Vout (0 ) VOL DD VDD C VGS <Vtr D out t Vout (t ) VDD (VDD VOL ) exp RDC RD RON out + Vout - What critical parameter affects the rise time? What effects would VDD have on the rise time? Kevin D. Donohue, University of Kentucky 8 Transition High to Low The equivalent circuit below represents the NMOS inverter going into a logic 0 output state. RON R R Circuit equations are: VDD Vout D ON CVout RON RD Vout (0 ) VOH RD VDD VGS >Vtr C RON RON RD VOL VDD RON RON RD t Vout (t ) VOL (VOL VOH ) exp RON RD C R R + D ON Vout - What critical parameter affects the fall time? What effects would VDD have on the fall time (note this ends in the triode region)? Kevin D. Donohue, University of Kentucky 9 SPICE Analysis The logic circuit can be analyzed in SPICE. For this lab use the MOSFET (Level 1 NMOS) component model. This is a generic model where parameters such as Kp and Vtr can be set. Stray capacitance values can also be set; however, this lab does not request this. R2 5K V2 5 M1 R1 10K IVm1 V1 0 IVm2 The transient simulation can be run, using V2 as VDD and V1 as a square wave (pulse setting in SPICE). The input and output voltages can be observed simultaneously. Kevin D. Donohue, University of Kentucky 10 SPICE Results Using a 10kHz square wave input, Kp=.225 and Vtr = 2.1: Cirex-Trans ient-5 (V) +6.000 0.0 +20.000u +40.000u +60.000u Time (s) +80.000u +100.000u +120.000u +4.000 +2.000 0.0 TIME +35.560u V(IVM1) +1.533m V(IVM2) +5.000 D(TIME) 0.0 D(V(IVM1)) 0.0 Kevin D. Donohue, University of Kentucky 11 SPICE Results Using a 10kHz square wave input, Kp=.225 and Vtr = 2.1 and Drain-Body and Source-Body capacitance of 1nF each: Cirex-Trans ient-6 (V) +6.000 0.0 +20.000u +40.000u +60.000u Time (s) +80.000u +100.000u +120.000u +4.000 +2.000 0.0 TIME -1.000 V(IVM1) -1.000 V(IVM2) -1.000 D(TIME) -1.000 D(V(IVM2)) -1.002 Kevin D. Donohue, University of Kentucky 12