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Transcript
Using Digital Technology to Optimize
Efficiency of Power Converters
Agenda

What is power efficiency?

Factors affecting efficiency

Why is efficiency imperative?

Ways to digitally improve efficiency of power converters

Digital Power Management

Processor Power Saving Options
2
What is power efficiency?

Efficiency in power converters

The classical definition of efficiency is the ratio of power utilized
by the load to the power consumed from the source, usually
expressed as a percentage

In case of multiple power stages, the cumulative efficiency is the
product of individual stage efficiencies

Efficiency consideration from power-converter perspective:
 Power requirement from the source
 Nature of power conversion
 Effect on upstream systems
 Overall power management
3
Factors Affecting Efficiency

Component selection



Topology of power converter




Higher rated components
Higher rated harmonic filters
Filter design


Switching frequency
Number of stages in the power converter
Line harmonics – voltage and current


Internal resistance of active and passive components
Switching component losses
Larger inductors and capacitors
Controller selection


Operating clock frequency
Device currents
4
Why is Efficiency Imperative?
Why is efficiency imperative?
Density
Density
Loss
Density
Density
Heat
Battery
Battery
Life
Life
Battery
Battery
Life
Life
Battery
Green
Life
Environment
Cost
Cost
Noise
Cost
Cost
Regulations
Density
Density
Density
Battery
Life
Battery
Life
Harmonics
Cost
Cost
Cost
6
Why is efficiency imperative?

Lower Losses Will Lead to





Higher Power Density



Reduction in the cost of the system
Lesser space requirements
Meeting Standards and Regulatory Needs



Lower heat dissipation
lesser cooling requirements, like fans, heat sinks etc.
Lower acoustic noise due to lesser cooling requirements
longer battery life in battery-operated systems
Reduction in cost
Greener environment due to lesser harmonics
Contribution to Greener Environment
7
Heat and Power Loss





DCR in inductors
ESR in capacitors
Driver losses
Loss due to poor PF



Switching loss in MOSFETs
Conduction loss in MOSFETs
Diode/Rectifier losses
Loss in passive components


Loss
Loss in switching elements


Heat
Operation at higher RMS and peak current
More reactive energy returned to grid
Transmission and distribution losses
8
Higher Power Density

Higher level of integration

S/W noise filters

RC time constant using S/W blanking

S/W dead-time configurations

Power control and communication

S/W protections / Fault handling

S/W-based output sequencing

On-chip clock, analog comparators and amplifiers

S/W-based feedback compensation
Density
9
Meeting Standards and
Regulatory needs
Regulations
Regulatory bodies across regions impose standards

EN 61000-3-2 (IEC 1000-3-2)





Equipment with <= 16A per phase, 230V line voltage
4 Equipment categories:
 Class A : General
 Class B : Portable Tools
 Class C : Lighting
 Class D : Equipment With Special Line-Current Shape
Up to 40 harmonic currents are imposed limits
 Class A : Absolute Limits
 Class B : Absolute Limits
 Class C : Relative Limits
 Class D : Both Relative and Absolute Limits
Based on IEC 555 (EN60555)
IEEE 519 - Recommended practices and requirements from IEEE for
harmonic control in electrical power systems
10
Battery Life

Low Power is required for battery-operated applications, such
as

Portable and Handheld devices





Hand Drill
Electric Shaver
Mobile Phones
Toys
Handheld Medical Applications



Battery
Life
Glucometer
Pulse Oximeter
Battery life directly depends on






Device ON/OFF state power losses
Power consumed by RTCC
Power for operating internal/external clock
Power for running Watchdog and Timers
Power for driving the display
Power for non-volatile memory operation
11
Going Green

Harmonics Reduction


Harmonics
Improved Total Harmonic Distortion (THD)
Line noise cancellation by operating PWM out of phase
Ripple Reduction

Multiphase Buck


Noise
Single or Multiphase PFC


Going
Green!
Output ripple cancellation by operating PWM out of phase
Switching noise reduction


Soft Switching
EMI Reduction
12
Cost

Cost
Lower PF penalty by energy boards


Higher reactive energy consumption
Poor THD

Cost due to higher harmonics
 Components with higher rating needed for sustaining
high harmonic peak currents

Higher power losses result in overheating and
premature failure of components and equipment

Cost due to higher cooling requirements
13
Ways to Improve Efficiency in
Power Converters
Efficiency Improvement
Techniques
Ways to digitally improve efficiency of power converters








Interleaving power stages
Phase Angle control
Phase Shedding
Resonant Conversion – ZVS and ZCS
Load Sharing
Synchronous Rectification
Motor Control Applications
Digital HID Ballast
15
Advantages of Interleaving Stages

Less ripple current on the output capacitor

Less ripple current in the input, as inductor ripples
cancel

Total inductor volume can be reduced

Each phase is rated for less power

Semiconductor devices have lower current rating

Smaller MOSFETs usually means better switching speed
16
Interleaving Power Stages - PFC
IIN
IL1
ID1
ILoa
PWM1
d
90 -265V AC
Is1
IL2
ID2
PWM2
Is2
PWM2
IC
PFC output
PWM1
IL1
IL2
(IL1 + IL2)
t
When duty cycle is = 50%
17
Interleaved PFC Operation
IL1
PWM1
90 -265V AC
Is1
IL2
PWM1
ILoad
ID1
ID2
PWM2
Is2
PWM2
IC
PFC output
IIN
IL1
IL2
(IL1 + IL2)
t
When duty cycle is > 50%
18
Interleaving Power Stages - Buck
Converter
3.3V
Output
12V Input
Q1
Q2
Drive Signals
are Phase
Shifted by 120°
120° 120° 120°
Q1
Q3
Q4
Q3
Q5
Q5
Q6
GND
19
Load Balance

Without Load Balancing



Component and wiring differences cause some modules to work
harder than others
The heavily loaded modules get hotter and reliability drops
causing failures – domino effect
With Load Balancing


Share the load equally between the converters
Reliability improvement by ensuring equal stresses
Buck
Phase 1
Load Equalization
Routine
Buck
Phase 2
Load
Buck
Phase 3
20
Phase Shedding

Power management : phase shedding
with adaptive control
Reduction in switching losses
 Reduction in reverse-recovery losses
 Reduction in inductor core losses
 Improves light-load efficiency


Phase angle control

Reduction in the ripple
21
Phase Angle Control

In multiphase PFC converters

Phase shedding at light loads should be
accompanied by
Adaptive phase adjustment, depending on number
of phases being shed
 EMI filter size will be minimized

22
Resonant Conversion

Absence of switching losses for the power switches

Operation at higher frequencies

Smaller magnetic components and filter components

Low levels of EMI/EMC emissions

Smaller heat sinks, reduction in size and weight

Higher overall efficiency at a given power
23
ZVS Methodology

Zero Voltage Switching:




Eliminates V*I losses in switching device during
transitions
Reduces noise in the system, hence better EMI
performance
Eliminates MOSFET output capacitor (Coss) loss
during switch turn-on
Preferred in high-voltage, high-power system
24
Zero Voltage Switching
At transition period from one state to another state of the
switch, the voltage is zero, hence no losses
ZVT demonstrated only at Switch turn-ON
Vds
D
Vds(t)
G
Id(t)
S
Id
ZVS
t
PWM
t
25
ZCS Methodology

Zero Current Switching:




Eliminates V*I losses in switching device during
transitions
Reduces noise in the system, hence better EMI
performance
Can be implemented at switch turn on as well as turn
off
RMS current through switch increases; therefore,
higher conduction losses
26
Zero Current Switching
 At transition period from one state to another state of the
switch, current is zero, hence no losses
 ZCS demonstrated only at Switch Turn-OFF
Ir(t)
D
Vds(t)
G
Vds
S
ZCS
t
PWM
t
27
Synchronous Rectification
 MOSFET’s RdsON will be less than diode forward voltage drop
 MOSFETs can be paralleled to have less conduction losses
 Sync FETs can be turned OFF to improve light load efficiency
 Drive is required for the MOSFETs
28
Motor Control Applications
Efficiency Improvement in Motor Control:

Center-Aligned Mode of PWM
 Reduces EMI problems
 Activation of PWM outputs such that centers of active periods
are aligned

Sensorless Control
 Eliminates mechanical feedback sensors
 Velocity and position information derived from motor currents

Single-Shunt Current Sensing
 Eliminates up to two shunt resistors
 Derives current information from precise PWM switching
29
Digital HID Ballast

Improve performance, such as lamp life, color property and lumen
maintenance


Improve precision and dynamic from startup


centralized real-time control loop algorithm
High efficiency


Centralized control, advanced algorithm, precise power control
High frequency, variable frequency, quasi resonant
Flexibility

Topology, protection

Insure IP protection

Reduce aging and temperature drift caused by components
30
Digital Power Management
Digital Power
SMPS Digital Power Conversion
Power control:
Controlling the power flow in the converter by digitally adjusting the
duty cycle, period, dead time, etc.
Power management:
Communicating with external peripherals, fault detection, monitoring,
data logging, etc.
32
Advantages of Digital Power
Management
• Design reusability
• Modular in design
• Redundancy
• On-site parameter changes
• Easy maintenance
• Better thermal management
• Reliability
• Ease in component selection
33
Load Sharing in Digital Power Converters
+
+
DC
Input
ADC1
-
Converter #2
-
ADC2
IZVT
IZVT
ADC0
+
Gate Drive
Converter #1
Q1- Q6
-
IZVT
I Share
IZVT
CMP
PI Control
dPhase
+/High speed PHASE Phase
dI
+ P Control
PWM
IAve
dIL
ADC2
+
ADC0
PI Control
dV
+
ADC1
- Targeted Voltage V *
o
34
Power-Supply Sequencing
sequential
simultaneous
V
5.0v
V
3.3v
5.0v
3.3v
T
T
offset
ratio metric
V
5.0v
V
3.3v
T
5.0v
3.3v
T
35
Dynamic Control of Gains

Change of compensator parameters
based on
Line voltage variations
 Load changes


Optimal dynamic performance in the
entire operating region
No hardware change
 Reduces passive-component size
 Improved step/transient response

36
Highest level of Integration
Vin
DC
Pulsating
AC
Active
PSFB
Push
clamp
Half
Full
Bridge
converter
Pull
Bridge
Gate drive
Sync gate
drive
I
Vo
DC
Vout
(DSC) dsPIC33FJ16GS502
Analog controller
Load share IC
Load
share
Microcontroller
Sync Rect.
Half
wave
Full
Wave
Sync
current
Rectification
doubler
Ext
Remote
Load
Sync
ON/OFF
share
Over
temperature
Aux. PSU
External
External data
communication
communication
37
External Communication

Remote monitoring of system parameters

Efficiency monitoring and degradation notice, prior
to actual failure

Fault data handling and logging

Locating and batch replacement of power supplies, if
required

Synchronization of converters to reduce beat
frequencies
38
No-Load Efficiency Improvement
Techniques

Fan-speed control based on temperature rise, to optimize fan
power consumption

Shutting down of fans in the case of multiple-fan cooling
arrangement

Burst-mode PWM generation to reduce switching loss under
light loads

Dropping individual converters in the multiple-converter
systems, at light loads

Switching-frequency reduction at light loads
39
Non-linear control techniques

Adjustable dead time to improve efficiency

Dead-time insertion in PWM to avoid cross
conduction between the upper and lower
MOSFETs

Adaptive control of dead time to minimize the
freewheeling diode conduction period

Industry claims about 1 to 5% gain in the
efficiency, because of adaptive dead-time
control
40
Processor Power Saving Options

Processor power consumption affects the overall
efficiency

Various Power-Saving Options:

SLEEP MODE



IDLE MODE



Ultimate in power reduction, everything disabled
Both the processor clock and the peripheral clock will be completely
disabled
Processor clock will be disabled
Peripheral clock can be kept active, optionally
DOZE MODE


Best of both worlds
Processor clock can be operated at a fraction of the frequency of
the peripheral clock
41
Design Cycle Optimization

One digital controller can support many topologies

Matlab/Simulink model help in






Simulate the actual system before designing hardware
Predicting system performance
Checking for transient and dynamic performance
Optimizing the system based on simulation results
Overall design cycle time reduction for efficient design
Code reusability is possible
42
References

www.microchip.com

www.ericsson.com

Interleaved PFC:
http://www.microchip.com/stellent/idcplg?IdcService=SS
_GET_PAGE&nodeId=1824&appnote=en544158

Integrated PFC + Motor Control:
http://www.microchip.com/stellent/idcplg?IdcService=SS
_GET_PAGE&nodeId=1824&appnote=en536059

Single Phase PFC:
http://www.microchip.com/stellent/idcplg?IdcService=SS
_GET_PAGE&nodeId=1824&appnote=en531747

AC/DC Power Supply with PFC
http://www.microchip.com/stellent/idcplg?IdcService=SS
_GET_PAGE&nodeId=2840&dDocName=en542591
43
Thank You