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EELE 414 – Introduction to VLSI Design
Module #8 – Miscellaneous & Advanced Topics
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Agenda
1. Latchup
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Announcements
1. Read Chapter 13
EELE 414 – Introduction to VLSI Design
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Latchup
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Latchup
- the various P and N junctions that are used to create the MOSFET structure also
form unwanted, parasitic bi-polar transistors in the silicon substrate
- these parasitic junctions can form a circuit known as a “Silicon Controlled Rectifier” (SCR)
- an SCR is a device that controls current flow just like a thyrister
- the term “SCR” is GE’s trade name for their own type of thyrister
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Latchup
- an SCR is made using 4 alternating material types (P-N-P-N)
- this can be thought of as two bipolar transistors (PNP and NPN) connected as follows:
- the entire SCR device operates as a 3 –terminal device with:
1) An Anode (the outermost P-region)
2) A Cathode (the outermost N-region)
3) A Gate (the inner P-region)
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Latchup
OFF State
- the device restricts current flow when the “Gate-to-Cathode”
voltage is below a threshold
ON State
- when the Gate-to-Cathode voltage exceeds a threshold, it will
turn ON the device and the device will conduct current
- the unique behavior of an SCR is that the device will REMAIN ON even after the
Gate-to-Cathode voltage drops back below the threshold as long as enough
current flows through the device
- the amount of current necessary for the SCR to stay ON after the Gate-to-Cathode
voltage has been removed is called the Holding Current
- to turn the device OFF, the SCR must fall below the Holding Current
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Latchup
- the major problem in MOSFETS is that these SCR circuits are parasitic
- if a spike of noise enters the gate of the SCR, then it will turn ON and remain ON
- this unwanted current path can destroy the IC
- SCR’s are present when using N-well CMOS
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Latchup
SCR Location
SCR Anode:
SCR Gate:
SCR Cathode
P = Source & Drain of PMOS
N = PMOS N-well
P = P-type Substrate
N = Source of NMOS
Q1 Location (PNP)
Emitter:
Base:
Collector:
Gain
P = Source & Drain of PMOS
N = PMOS N-well
P = P-type Substrate
β = 100-200
Q2 Location (NPN)
Collector:
Base:
Emitter:
Gain
N = PMOS N-well
P = P-type Substrate
N = Source & Drain of NMOS
β = 1-10
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Latchup
R-well
- resistance in the N-well material
- Rwell = 1k - 2k ohms
R-sub
- resistance of the substrate
- Rsub = 1-200 ohms
Operation
- since the resistances are high they can be neglected, thus
the SCR is only triggered by an external event
- if the collector current of one transistor is temporarily increased,
a positive feedback loop will occur due to a gain greater than 1:
1  2  1
- this turns on the SCR and current will flow even after the
external event as been removed
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Latchup
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Latchup Triggers
VDD Slew
- Initial turn-on of the IC causes a fast change in the voltage of the supply from 0-to-VDD
- this causes enough charge displacement in the substrate to bias the SCR
Signals Larger than VDD
- if input signals have large amounts of overshoot resulting in voltages larger than VDD or
less than VSS they will cause a bias of the SCR
- this can be due to transmission line reflections or inductive loads
Electro Static Discharge (ESD)
- ESD strikes can put thousands of volts on the IC and provide enough bias to turn on the SCR
Supply Transients
- Large current spikes in the VDD or VSS rails due to simultaneous switching of signals
can provide enough current bias to turn on the SCR
Radiation
- high energy particles that pass through the semiconductor materials can cause electron/hole
pairs. The loose electrons cause voltages as they pass through impedances and can
create enough bias to turn the SCR on
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Latchup
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Avoiding Latchup
Reduce the Gain of the BJT’s
- Gold has been used to dope the substrate in order to lower the minority carrier lifetime
of the substrate without increasing leakage
Guard Bands
- if we put p+ diffusion rings around the NMOS transistors and n+ diffusion rings around the
PMOS transistors, they will break up the PNPN junctions
- they will also reduce the Rwell and Rsub resistances. Lowering these resistances provides
a low resistance path for the bias current to flow instead of it going into the bipolar transistors
Substrate Contacts
- place substrate and N-well contacts close to the transistors in order to reduce
the Rwell and Rsub resistances
Avoid Forward Biasing of S/D Junctions
- using a lightly doped epitaxial layer on top of a heavily doped substrate will shunt
lateral currents from the vertical transistor through the low-resistance substrate
- eliminate overshoot/undershoot using sound design principles for off-chip interfacing
Placement of MOSFETS
- place NMOS’s near the VSS rails to reduce resistances
- place PMOS’s near the VDD rails to reduce resistances
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Latchup
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Avoiding Latchup
Current Chokes on Supply
- During start-up, the total current into the IC can be limited so that if an SCR turns on, it will
not sink enough current to destroy the device. The device can then be safely powered down.
ESD Diodes
- ESD diodes are placed on I/O pads in order to sink any high currents directly into the
substrate upon an ESD strike
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