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Analog to Digital Converters (ADC) 1 Technician Series ADC 1.1 ©Paul Godin Created April 2008 Last Edit Mar 2015 Introduction ◊ Analog to digital conversion is an important aspect of digital electronics. ◊ ADCs allow the use of real-world values with the advantages of digital electronics. ◊ There are many examples of ADC converters used in everyday applications. Name a few examples of ADC applications ADC 1.2 Advantages of Digital Values ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ Relatively less sensitive to distortion (noise and losses) Can be reproduced much more accurately Much easier to reconstruct a signal More storage options Can be processed mathematically and logically Easier to standardize Systems are easier to design (fewer voltage / current issues) Digital systems can be made small (low current) Display options ADC 1.3 Challenges with ADC ◊ Converting an analog value to digital values comes with disadvantages: ◊ It takes time to convert a signal from Analog to Digital, and then to process that signal. May be too slow for some applications. ◊ Never 100% reproduction…always a series of discrete values. ◊ Requires more complex circuit design ◊ More faithful reproduction requires more bit of resolution. ◊ Requires other circuit elements such as oscillators and memory systems. ADC 1.4 ADC FUNDAMENTALS ADC 1.5 Sampling ◊ Voltage signals are comprised of amplitude over time. ◊ The analog signal must be converted to its digital value at specific periods of time. ◊ Sampling is the process of taking a digital value at regular time intervals. ◊ The digital values must be stored if they are to be processed. ADC 1.6 Sampling AC Value Sampling Pulses Time Digital Values at timed intervals ADC 1.7 Sampling ◊ Increasing the number of binary values representing a voltage value improves its voltage resolution. This is called quantization. The greater the number of bits available, the greater the quantization level. ◊ Increasing the sampling frequency improves the time resolution. The more samples taken over time the more accurate the representation of the signal. ADC 1.8 Nyquist ◊ The sampling frequency must be greater than the highest frequency component of the analog signal. ◊ The Nyquist frequency has a value of twice the highest analog frequency. fs ample 2fA(M A X) Where: ◊ fsample is the sampling frequency ◊ fA(MAX) is the maximum analog frequency ADC 1.9 Sampling Issues AC Value Digital Value Properly Sampled Under-sampled ADC 1.10 Sampling Error (animated) ADC 1.11 Sampling Rates ◊ Sampling rates are selected based on: ◊ application ◊ requirements ◊ standards ◊ As an example, an exterior thermometer needn’t be sampled at the same rate as an audio application. ADC 1.12 Audio Application of ADC ◊ When music is digitized for CDs the sampling frequency is 44.1 kHz (48 kHz for professional recording). ◊ According to the Nyquist frequency, 44.1kHz is acceptable for up to 22 kHz. Since most audio equipment functions at less than 20 kHz (and is at the upper limit of human hearing), the 44.1 kHz sampling rate is acceptable. ◊ The bit depth is 16 for CD audio (up to 24 for DVD-Audio). ADC 1.13 Notes on mp3 ◊ MP3 audio files refer to their quality as a bit rate. Typical mp3 bit rates are 128kbps and 192kbps (maximum is 320kbps according to standards). ◊ MP3 is an encoding format used to compress and reduce the file size. The file follows protocols and contains various elements such as headers, file information, the compressed data, bit rate type and other information. ◊ MP3s do not have a bit depth per say, more of a dynamic compression of data based on an analysis of the sound. The result is a high compression rate. ◊ For comparison, bit rate for uncompressed audio (CD) recording is 44.1kHz sampling x 16 bits x 2 channels (1411.2 kbps). ADC 1.14 Digitizing Voice ◊ Human voice for applications such as telephone conversations need not be sampled at a similar rate and bit depth as music. ◊ Typically, 8 bits at 8 kHz sampling rate is used (64kbps). ADC 1.15 ASYNCHRONOUS ADC ADC 1.16 Asynchronous ADC ◊ ADCs can be constructed from comparators. ◊ A comparator is an op amp configuration where the voltages of two inputs are compared. ◊ If the “+” input is greater than the “-” input, the output is a logic high. VDD ADC 1.17 Comparator-Based ADC VDD Analog In Digital Out 2-bit “weighted” ADC ADC 1.18 Flash ADC VDD Analog In Priority Encoder Digital Out Enable 3-bit Flash ADC ADC 1.19 Flash ADC ◊ Flash ADCs are very fast and can convert data at high frequencies. ◊ The major disadvantage to flash ADCs is the complexity of the circuits. ◊ One op amp is required for each output value (minus one for all zero). This means that: ◊ an 8-bit Flash ADC requires 255 op amps ◊ a 12-bit Flash ADC requires 4095 op amps ◊ a 16-bit flash ADC requires 65,535 op amps ADC 1.20 Hold/Store ◊ ADCs need to store measured values between the sampling pulses. ◊ ◊ Converting a stored digital signal back to analog requires a similar clocking frequency (time needs to be reproduced). AD conversion represents a series of values at specific instances of time. The Sample and Hold creates the output “ladder” effect. ADC 1.21 Flash ADC with Sample/Hold VDD Analog In Priority Encoder Latch Circuit Clock Digital Out Digital Out Enable 3-bit Flash ADC ADC 1.22 Basic ADC ◊ A basic ADC contains: ◊ differential analog inputs (VREF) for scaling ◊ Analog signal input (VIN) ◊ Output Enable for tristate-able outputs (OE) ◊ Start of Conversion input (SOC) to trigger the analog signal read cycle. ◊ End of Conversion output (EOC) to indicate that the conversion is complete, the data is on the data bus and a new input may be applied. ◊ Digital output (D0~D7). ADC 1.23 Dual Slope ADC ◊ Also known as Counter-Ramp or Digital Ramp ADC ◊ A dual slope ADC is commonly used in measurement instruments (such as DVM’s). ADC 1.24 Dual Slope VReference Capacitor Cycle Counter Cycle Charge Counts from 0 to max Count Reset Discharge Count Display Count Display Max Count / Restart Count ADC 1.25 Dual Slope Function ◊ The Dual Slope ADC functions in this manner: ◊ When an analog value is applied the capacitor begins to charge in a linear manner and the oscillator passes to the counter. ◊ The counter continues to count until it reaches a predetermined value. Once this value is reached the count stops and the counter is reset. The control logic switches the input to the first comparator to a reference voltage, providing a discharge path for the capacitor. ◊ As the capacitor discharges the counter counts. ◊ When the capacitor voltage reaches the reference voltage the count stops and the value is stored in the register. ADC 1.26 Dual Slope ◊ The Dual Slope method takes time for the conversion to occur. Each additional bit improves resolution but also adds a significant bit to the counter, costing considerable time. This type of ADC is therefore unsuitable for rapidly changing analog input. ◊ Each clocking pulse increments the counter by one. It takes (2N-1) clock cycles times the clock period for an output to be produced. ADC 1.27 Dual Slope ◊ The Dual Slope method is accurate and requires less circuitry than other methods. Since it uses the same clock input for both phases of conversion, a drift in the clocking frequency will not affect the accuracy of the output. ◊ The Dual Slope is best suited for applications where the measured value is relatively stable such as DC voltage measurements. ADC 1.28 Successive-Approximation ADC ◊ The Successive-Approximation ADC is one of the most popular types in use today. It has a relatively simple configuration and an excellent conversion rate. ◊ If an IC such as a microcontroller has an integrated ADC, it is typically this type. ADC 1.29 Successive-Approximation ADC SOC Input Oscillator Voltage Comparator EOC Control Logic Digital to Analog Converter Approximation Register Output Register Digital Output ADC 1.30 Successive-Approximation ADC ◊ The SAC ADC functions in this manner: ◊ ◊ ◊ ◊ The approximation register is reset to all zero. When a voltage is applied to the input the approximation register’s most significant bit is changed from a 1 to a 0. The digital output of the register is converted back to analog through the DAC and is compared to the applied analog voltage. If the value is too low the 1 is left at the MSB. The next MSB is incremented, the output converted to analog and again compared to the analog input. Each bit is successively incremented and the output value compared. If the voltage from the DAC becomes higher than the applied analog value the bit is reset to 0 and the next MSB is incremented and compared. The process continues in this manner until the LSB value is reached. At the LSB, if the applied value makes the DAC output voltage higher the bit is reset to 0. The ADC has completed its process. It stores the value to the output register and provides an EOC output to indicate there is a value in the register. ADC 1.31 SAC ADC Conversion Time ◊ Theoretically each step in the comparison process takes a clock edge. It therefore takes a SAC ADC approximately the same amount of clock edges as the number of bits it handles. If a SAC ADC has an output of 8 bits and an input clocking frequency of 500 kHz, it takes approximately: 8•(1/500kHz) = 8•2µs=16µs ◊ In actual practice it may take more than one clock edge per step, but this is still faster than some other methods. ADC 1.32 The ADC08 ◊ The ADC08 family is a relatively popular SAC ADC. VDD +VIN D0 to D7 -VIN Digital Output Vref/2 CS RD ClkOUT WR ClkIN INTR GNDAnalog A GNDDigital D ADC 1.33 ADC08 ◊ +VIN and –VIN : Differential analog voltage. ◊ Vref/2 : Used to change the input voltage range. Normally at 2.5V when VDD = 5V, if 1.5V is applied the input range is 3.0 Volts and the resolution is changed accordingly. ◊ ClkIN: Input clock. External clocking edges can be provided to the ADC. ◊ ClkOUT: Output Clock. This ADC has an internal clocking circuit that requires external connection to an RC. T = 1.1RC Typical values: 10kΩ & 150ρF ADC 1.34 ADC08 ◊ CS’ : Chip Select (input), tri-states the digital output for bus applications ◊ RD’: Read enable (input), enables the output from the Approximation register to the output register. ◊ WR’: Write enable (input), used to request the start of a new conversion. ◊ INTR: Interrupt, output high when the ADC is in the process of converting an input. Used to signal microprocessors or microcontrollers. Conversion time is approximately 100µs. ADC 1.35 ADC08 ◊ Questions: ◊ What is the purpose of two grounds? ◊ How would the device be configured for an input of: ◊ 0 to 5 Volts ◊ 0 to 3 Volts ◊ -2.5 to +2.5 Volts ◊ What is the purpose of the Vref/2 input? ADC 1.36 SAC ADC ◊ The SAC ADC is a fast, accurate device. ◊ It has few disadvantages over other methods. ◊ It requires a high clock frequency as each bit takes up an edge. ◊ It is not overly complex, and can be scaled more easily. ADC 1.37 Other Methods of ADC ◊ Up/Down Ramp ◊ Similar to the Ramp ADC but instead of starting the count at zero for each measurement it increments the counter up or down based on the direction of the analog input. The time it takes for conversion is variable. ◊ Voltage-Frequency ADC ◊ This device utilizes a Voltage Controlled Oscillator (VCO). The higher the input voltage the higher the output frequency of the VCO. The ADC enables the output of the VCO for a specific period of time and the output of the oscillator is connected to a counter. The result of the count is supplied as the digital value. ADC 1.38 Other Methods of ADC ◊ Sigma/Delta ◊ Creates an internal bitstream based upon the difference (Delta) between the analog input and a feedback comparator. The running total (Sigma) is reported as the digitized value. Operates at a high internal frequency. See http://www.analog.com/Analog_Root/static/techSupport/designTools/interactiveTools/sdtutorial/sdtutorial.html for more information. ADC 1.39 Errors ◊ Analog to Digital systems have several possible sources of error. ◊ The errors can be the result of: ◊ ◊ ◊ ◊ Quantization Noise Slew Under-Sampling ADC 1.40 Quantization Error ◊ Quantization errors are a normal occurrence for ADCs. The input voltage will commonly have a value that is between the LSB voltage step and must be rounded up or down. ◊ For instance, if the resolution is 20mV per bit and a value of 10 mV is applied, the ADC will interpret this as either 0v or 20 mV, depending on the ADC design. ADC 1.41 Quantization ◊ There are several additional quantization issues: ◊ If the total number of bits representing the amplitude of the signal is too small the quantization error increases. ◊ If the voltage applied to the ADC is not properly compensated then the full range of output values is not used. ADC 1.42 Quantization and Sampling ◊ Sampling-Related Quantization Errors ◊ Relatively low sampling frequencies can lead to quantization errors ◊ If the sampling frequency is slightly different from the analog signal’s frequency (or a harmonic..a factor of the frequency), then the values may not indicate all the peaks and valleys, leading to other harmonics (also see aliasing). ADC 1.43 Not quite perfect...lower sample rate Above: original signal with samples Below: imperfections in the digital output quantization ADC 1.44 Not quite perfect...higher sample rate ADC 1.45 Noise ◊ Noise is a factor in analog communications and it causes problems in ADC. ◊ The sources for noise are varied and can be somewhat complex. ◊ Sources include: ◊ External Sources ◊ Internal circuit sources ◊ Aliasing ADC 1.46 Aliasing ◊ Higher quality ADC (and DAC) will contain anti-aliasing filters to remove frequencies that are aliasing (“posing”) as signal. ◊ Aliasing occurs when additional frequencies are inadvertently produced in the AD process. ◊ For instance, if there are some frequencies present in the original signal that are higher than the Nyquist sample rate, a different lower frequency may appear on the conversion. ◊ Aliasing also occurs with adequate sampling frequencies. ADC 1.47 Aliasing due to Inadequate Sampling Rate ADC 1.48 Aliasing with an Adequate Sampling Rate ADC 1.49 Noise Sources ◊ Analog values are susceptible to noise (an advantage of digital electronics!). This noise causes problems for the AD conversion, as the noise will be included in the conversion process. ◊ There are external and internal sources of noise. ◊ External: use filters and proper techniques to minimize noise (such as decoupling, isolation, etc) ◊ Internal: switching noise occurs with AD converters. Use filters, decoupling and ground isolation. Thermal noise (aka white noise) is caused by a variety of reasons. ◊ Other solutions include processing the signal (DSP), injecting additional white noise to help average out the noise and ignoring the LSB. ADC 1.50 Filter ◊ The analog input to an ADC should contain a lowpass filter to ensure high frequencies cannot pass and create aliasing problems. ◊ Advanced filtering techniques are also employed. These include DSP (Digital Signal Processing) to mathematically analyze and adjust the digital values. ADC 1.51 Gain Error ◊ A Gain Error occurs when the ADC produces an output at a different quantization level than desired. The output is linear but the steps are either larger or smaller than they should be. The resolution is poor and there is the possibility of clipping (the binary number stops changing with a change in analog input). The voltage values will be inaccurately represented. Red: Ideal Blue: Error Green: Error Binary Code Input Volts ADC 1.52 Gain Error Typical Causes: •wrong VDD/VEE/Vreference voltage to the ADC •Improper Analog input voltage Red: Ideal Blue: Error Green: Error ADC 1.53 Offset Error ◊ An Offset Error occurs when the output has the same voltage per step but the starting voltage is different. Red: Ideal Blue: Error Green: Error Binary Code Input Volts ADC 1.54 Offset Error Typical Causes: •Improper ground reference •Improper analog voltage range Red: Ideal Blue: Error Green: Error ADC 1.55 Non-Linearity: Non-Monotonic ◊ A Monotonic Error occurs when the individual voltage steps are non-linear. Binary Code Red: Ideal Blue: Error Input Volts ADC 1.56 Non-Linearity: Non-Monotonic Typical Causes: •defective ADC •wrong outputs measured •significant noise on ac input Red: Ideal Blue: Error ADC 1.57 Slew ◊ Slew represents the maximum rate of change of a signal. Slew rate is measured in V/t. Black: ideal binary step from ADC Grey: binary step from ADC with slew ADC 1.58 Analog Sample & Hold ◊ The AD conversion process may be adversely affected when an analog signal changes voltage during conversion. ◊ Analog sample & hold circuits are able to capture the analog value and retain it, allowing the ADC to perform the conversion without input changes. Digitally controlled switch Analog In Storage Capacitor Analog to ADC ADC 1.59 Specification Sheet ◊ View the specification sheet for the ADC08 from National Instruments. ◊ Definitions: ◊ Common-Mode noise is noise that occurs on both conductors at the same time. ◊ Ratiometric means measures the ratio, or takes ratio into account when measuring. ADC 1.60 DSP ◊ Digital Signal Processors perform operations on the digitized signals including: ◊ removing interference, noise and other frequency and transmission effects ◊ encoding the values for transmission ◊ reconstruct signals by enhancing or decreasing specific frequencies ◊ DSPs are complex devices that rely on programming code (algorithms) to perform operations. ADC 1.61 ADC-DAC with DSP Filter ADC DSP DSP DAC Filter ADC 1.62 DSP ◊ Analog signals contain noise. Noise can be filtered but sometimes the filtering process can eliminate wanted frequencies. ◊ The better means of removing noise is to take an average, as illustrated below as the red line. Analog Signal with Noise ADC 1.63 END ADC1 ©Paul R. Godin prgodin°@ gmail.com ADC 1.64