Download Xilinx Template (light) rev

How Do I Plan to Power My FPGA?
Xilinx Training
Objectives
After completing this module, you will be able to:
Explain how static power is different from dynamic power
Describe the impact a smaller device geometry has on static
power consumption
Define the relationship between leakage current and junction
temperature
Describe some of the device data sheet information that pertains
to power consumption
Total Power = Static + Dynamic
Once the device has powered up, there are two main
components to power consumption
Static power
• Primarily transistor leakage current
 Source to Drain leakage IS →D source
 Gate to substrate leakage IGATE
• Some current from special circuits (DCM, etc)
Dynamic power
• Switching in the FPGA core and I/O
• Determined by CV2f
 node capacitance,
 supply voltage
 switching frequency
gate
IGATE
ISD
Buf
drain
Buf
C
The Industry Trend in Leakage Current
Ileakage (nA/um)
New Technologies  Smaller
transistor length Higher IS →D
Faster transistors (lower Vt )
Smaller Gate Oxide thickness 
Higher (IGATE)
The total leakage for all
transistors in the device
100
0
100
10
Transistor Ileakage
Trend
Low
VT
– ICCINTQ = IS →D + IGATE
Even when the device is not
doing a task it still draws some
power
– This leads to the development of
new features such as Suspend and
Hibernate mode
Smaller process geometries
lead to higher static power
1
Regular VT
0.1
220 180 150 130 90
75
Technology Node
65
Properties of Leakage Current
Leakage
Current
Junction
Temperature
(TJ °C)
Normalized
ICCINTQ Typical
25
1.00
50
1.46
85
2.50
100
3.14
ICCINTQ
100 °C
85 °C
50 °C
25 °C
-40
-20
0
20
40
60
80
100
120
140
Junction Temp
°C
 Leakage current increases dramatically with Junction
Temperature
Data Sheet Specifications
Iccintq, Iccoq, Iccauxq
– These are the bare minimum currents (quiescent) required for
your power supply to operate the device
–
–
Does not guarantee that your design is going to work, just that
this is the minimum current
– Dynamic power requirements will increase the required
current during operation
Refer to the Spartan-6 FPGA Data Sheet or the Virtex-6
FPGA Data Sheet
Data Sheet Specifications
Power-On requirements are greater than the operating
current requirements
– These are the bare minimum currents (quiescent) required for
your power supply to power up the device
–
–
–
This is used for picking out a sufficient power supply
Does not guarantee that your design is going to work, just that
the device will configure
Refer to the Spartan-6 FPGA Data Sheet or the Virtex-6
FPGA Data Sheet
Design-Dependent Power
It is up to the user to plan on how much current their system
can use
– This is dependent on the design, FPGA, and other devices used in
your system
It is also up to you to anticipate how much your worst case
power consumption might be
– Xilinx provides descriptions of the current draw your
FPGA might have at power-up, during minimal operation,
but not for worst-case conditions
• Too much is design dependent (resources used, clock
frequency, etc.)
To get the best power estimate we offer a couple of power
estimation tools
– Please refer to the Power Estimation Video for more information
Estimating Power Consumption
Power calculations can be performed at three distinct phases of
the design cycle
– Concept phase: A rough estimate of power can be calculated based on
estimates of logic capacity and activity rates
• Use the Xilinx Power Estimator spreadsheet
– Design phase: Power can be calculated more accurately based on detailed
information about how the design is implemented in the FPGA
• Use the XPower Analyzer
– System Integration phase: Power is calculated in a lab environment
• Use actual instrumentation
Accurate power calculation at an early stage in the design cycle
will result in fewer problems later
Summary
Static power is dependent on the transistor leakage current
Dynamic power is dependent on the switching of the logic in the
CLB array and IOB resources
Smaller device geometry increases the static power consumption
of all devices
– Newer devices have a higher static power consumption
An increase in junction temperature dramatically increases the
leakage current and your static power
The minimum current required to operate and configure the
FPGA is provided in your FPGAs data sheet
– But the best way to estimate your power consumption is with either the
Xilinx Power Estimator spreadsheet or the XPower Analyzer utility
Where Can I Learn More?
Xilinx online documents
– www.support.xilinx.com
• Spartan-6 FPGA Power Management User Guide, UG394
 Introduces the Suspend and Hibernate modes
 Describes the necessary voltage supplies
 Introduces the low-power (-1L) devices
 Describes the Power-On and Power-Down behavior
 Power Estimation options are discussed
Where Can I Learn More?
Xilinx Education Services courses
www.xilinx.com/training
– Designing with Spartan-6 and Virtex-6 Device Families course
• How to get the most out of both device families
• How to build the best HDL code for your FPGA design
• How to optimize your design for Spartan-6 and/or Virtex-6
• How to take advantage of the newest device features
Free Video Based Training
– How Do I Plan to Power My FPGA?
– Power Estimation
– What are the Spartan-6 Power Management Features?
– What are the Virtex-6 Power Management Features?
Trademark Information
Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on,
or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded,
displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or
otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of
privacy and publicity, and communications regulations and statutes.
Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents,
copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design.
Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no
obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the
accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.
THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH
YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE,
WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS,
IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.
IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,
INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH
YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF
FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT
THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU
WITHOUT THESE LIMITATIONS OF LIABILITY.
The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe
controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons
systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You
represent that use of the Design in such High-Risk Applications is fully at your risk.
© 2012 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All
other trademarks are the property of their respective owners.