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Figure 12.1 Circuit symbol for the comparator. If v1 > v2, then vo is high; if v1 < v2, then vo is low.
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Figure 12.2 Transfer characteristics of ideal comparators.
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Figure 12.3 Transfer characteristic of a real comparator.
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Figure 12.4 The LM111 has an open-collector output.
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Figure 12.5 The input voltage vin is compared to the reference voltage Vr.
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Figure 12.6 Noise added to the input signal can cause undesired transitions in the output signal.
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Figure 12.7 A Schmitt trigger is formed by using positive feedback with a comparator.
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Figure 12.8 Noninverting Schmitt trigger.
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Figure 12.9 Schmitt triggers that can be designed to have specified thresholds.
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Figure 12.10 Schmitt trigger designed in Example 12.1.
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Figure 12.11 Input voltage and output voltage versus time for the circuit of Figure 12.10.
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Figure 12.12 Transfer characteristic for the Schmitt trigger of Example12.1.
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Figure 12.13 Answer for Exercise12.1.
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Figure 12.14
Answer for Exercise 12.2.
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Figure 12.15 Answer for Exercise 12.3.
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Figure 12.16a Astable multivibrator.
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Figure 12.16b Astable multivibrator.
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Figure 12.17 Waveforms of Figure 12.16b with t = 0 at the start of a positive half-cycle of vo(t).
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Figure 12.18 Astable multivibrator designed in Example 12.3.
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Figure 12.19 Simulated voltages for the circuit of Figure 12.18.
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Figure 12.20 Circuit for Exercise 12.5.
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Figure 12.21 Answer for Exercise 12.5b.
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Figure 12.22 Circuit for Exercise 12.6.
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Figure 12.23 Answer for Exercise 12.6b.
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Figure 12.24 Simplified functional block diagram of 555 timer IC.
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Figure 12.25 Monostable multivibrator.
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Figure 12.26 Astable oscillator.
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Figure 12.27 Circuit for Exercises 12.7 and 12.8.
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Figure 12.28 Simple rectifier circuits such as this are not suitable for precision rectification of small-amplitude ac signals.
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Figure 12.29a Precision half-wave rectifier.
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Figure 12.29b Precision half-wave rectifier.
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Figure 12.30 Improved half-wave rectifier.
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Figure 12.31 Precision full-wave rectifier.
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Figure 12.32 See Exercise 12.10.
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Figure 12.33 Simple peak detector.
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Figure 12.34 Precision peak detector.
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Figure 12.35 Answers for Exercise 12.13.
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Figure 12.36a Sample-and-hold circuit.
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Figure 12.36b Sample-and-hold circuit.
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Figure 12.37a Precision clamp circuit.
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Figure 12.37b Precision clamp circuit.
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Figure 12.38a Answers for Exercise 12.14.
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Figure 12.38b Answers for Exercise 12.14.
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Figure 12.39 Analog-to-digital conversion.
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Figure 12.40 The DAC output is a staircase approximation to the original signal. Filtering removes the sharp corners.
(Note: In addition to smoothing, the filter delays the signal. The delay is not shown.)
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Figure 12.41 Circuit symbol for a digital-to-analog converter.
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Figure 12.42 DACs can be implemented using a weighted-resistance network.
(Note: If di = 1, the corresponding switch is to the right-hand side. For di = 0, the i th switch is to the left-hand side.)
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Figure 12.43 An R -- 2R ladder network. The resistance seen looking into each section is 2R.
Thus, the reference current splits in half at each node.
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Figure 12.44 An n-bit DAC based on the R–2R ladder network.
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Figure 12.45 A practical n-bit DAC based on BJT technology that uses emitter-coupled pairs as current switches.
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Figure 12.46a Switched-capacitance DACs.
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Figure 12.46b Switched-capacitance DACs.
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Figure 12.47 Conceptual block diagram of an analog-to-digital converter.
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Figure 12.48 A flash converter.
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Figure 12.49 Output versus input for a 3-bit ADC.
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Figure 12.50a Dual-slope ADC.
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Figure 12.50b Dual-slope ADC.
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Figure 12.51a Successive approximation ADC.
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Figure 12.51b Successive approximation ADC.
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