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Transcript
CMOS Analog Integrated Circuits
Part 1. Basic Analog Models for CMOS Technology
Emil D. Manolov
Advanced level study programme in
Electronics Design and Integration Technologies
28213-IC-1-2005-1-BE-ERASMUS-PROGUC-3 2006-2322 / 001-001 SO2
Technical University of Sofia
Faculty of Electronics
ECAD Laboratory
2008
1. Basic Analog Models for
CMOS Technology
CMOS Analog Integrated Circuits
(introductory course)
Emil D. Manolov, [email protected]
Department of Electronics, Technical University – Sofia
Integrated circuits design flow
The design of an analog integrated circuit is very complicated interactive procedure.
The first step is the initial (first-cut) design. It includes analysis, proposing of an
appropriate circuit topology and hand-calculation the values of the currents and the
sizes of the transistors by using simple expressions. This is very responsible task
because it puts the fundament of the seeking solution.
The next step is an extensive simulation of the circuit in order to optimize the
parameters. This design stage aims to take in considerations the second-order effects
and to examine the influence of the process variations on the performance. It gives
to designer precise information about the circuit operation and allows in interactive
way to achieve the final specification.
Briefly, the fist stage is devoted to design and hand-calculation and the second – to
efficiently and accurately simulation of the developed circuits.
The different goals, which are seeking at the different design stages, determine the
need from different type models of the used transistors.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
3
Hand-calculation and simulation models
In practice, there are two types of transistor models, which are used in the design
process.
The first type are the hand-calculation models allowing to predict the performance of
the circuit through simple expressions. These models present the operation of each
transistor by means of as few equations as possible. They must include only the most
fundamental parameters of the transistors.
Employing the simple hand-calculation models, the designer describes the
performance of the circuit only in an approximate way, but in the initial stage of the
design, the clear understanding of the basic relations and the tradeoffs in the circuits is
more important then the accuracy of the calculations.
The second type are the transistor models, which are used to simulate the circuits.
They are very sophisticated models, with large number of parameters included in
exclusively complex relation. These models allow effectively and accurately circuit
simulation, but are not appropriate for the first step initial hand-calculations.
In this module we will discuss the most popular hand-calculation models for MOST
and BJT.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
4
MOS transistor structure
The figure reminds the typical Nchannel and P-channel MOSFET
structures. They have four terminals:
gate - G, drain - D, source - S and body
(back gate, bulk) - B. The body B, is
biased so that negligible current flows
through it. The basic operating
principle is that a voltage is applied
between the gate and the source in
order to control the conducting channel
between the source and drain regions.
If the device is fabricated so that there is no channel in the absence of a gate-to-source bias,
this device is called normally off or enhancement mode MOST. In order to turn an
enhancement mode MOST “on”, a channel must be created by applying bias to the gate.
It is also possible to fabricate devices in which a channel exists even in the absence of any
bias on the gate. Such a device is called a normally on or depletion mode MOST. To turn a
depletion mode MOST “off,” a bias must be applied that cause the channel to disappear.
The contemporary analog integrated circuits uses as a rule enhancement mode MOST.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
5
Symbols for MOSFET
The picture shows the symbols used for n-channel and p-channel enhancement mode
MOSTs. The MOST are four-terminal devices, but in some cases, when the bulk B of nMOST is connected to the minimum power supply voltage VSS or the bulk of p-MOST –
to the maximum power supply VDD, it is possible to use the simplified symbols without
the pin B.
Important!
We must remember that the source and the drain of the integrated MOST are
interchangeable.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
6
Regions of operation
The figure presents the square root of the drain current plotted as a function of the gatesource voltage for n-MOST. The left region, below the VTN0+∆, is characterized with an
exponential-law behavior. It is called weak inversion or subthreshold region. The right
region, above the VTN0+∆, is characterized with an square-law behavior. It is called
strong inversion region.
VTN0 is known as threshold voltage of the transistor.
The quantity Δ=njT, where jT is the thermal voltage (about 25.8mV at 300K) and n is a
constant. For practical estimations the value of the is about 100mV.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
7
Threshold voltage
Figure shows the transconductance characteristics of n-MOS and p-MOS transistors. With
VTN0 and VTP0 are denoted the threshold voltages of n-MOST and p-MOST, when theirs
body B and source S are short connected. If between these two terminals some voltage is
applied, the threshold voltage change its value and is denoted as VTN (or VTP).
The values of VTN0 and VTP0 depends on the technology. The typical values for VTN0 are
between 0.3V and 0.8V and between -0.4V and -1V for VTP0. The threshold voltages
depend also on the temperature and on the transistor dimensions.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
8
Body effect
Figure shows the linearization of
transconductance characteristic of
n-MOS transistor. The threshold
voltage increases as the body
potential becomes more negative.
The phenomena is known as the
body effect.
The value of threshold voltage for
n-MOST can be hand-calculated
by using the following formula
VTN  VTN 0   n
V
SB
 2 F 
2 F

where VTN0 denotes the threshold voltage when VSB=0, n is process dependent, often
called the body effect constant, |2ϕF| is the strong inversion surface potential.
Usually n ≈0.5…0.8 V1/2 and |2ϕF|≈0.6 V.
The corresponding equation for p-MOST is similar
VTP  VTP 0   p
CMOS Analog IC
Emil D. Manolov, TU-Sofia
V
BS
 2F 
2F
Basic analog models for CMOS Technology

9
About equations for p-MOS transistors
In this module we will present and discuss the basic DC relations and formulas mainly on
the base of n-MOS transistors.
To obtain the corresponding equations for p-MOS transistors it is necessary to put
negative signs in front of all voltages in DC relations for n-MOST.
Example
From previous slide the equation for the threshold voltage of the n-MOST is
VTN  VTN 0   n
V
 2 F 
SB
2 F

To obtain the equation for p-MOST we put negative signs in front of all voltages
 VTP   VTP 0   p
After simple transformations we obtain
VTP  VTP 0   p
 V
SB
V
BS
 2 F 
 2F 
2 F
2F


which coincides with presented in previous slide formula.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
10
Weak, moderate and strong inversion
Figure depicts the log ID
against VGS characteristic,
where an another transition
region of operation called
moderate inversion appears.
This region (in red) is situated
between weak (in light brown)
and strong (in green) inversion
regions (i.e. from VTN0- up to
VTN0+∆).
The operation in strong inversion is a typical solution in the practice of contemporary
analog integrated circuits design. Therefore our introductory course will concentrate
thoroughly on the models and circuits operating in strong inversion.
Recently the weak and moderate inversion operations (i.e. subthreshold region)
become very actual when low-power circuits are desired. This is the reason to make a
short description of the basic relations in this region of operation. The detailed study
of the weak and moderate inversions is a purpose of the others advanced courses.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
11
Operation in strong inversion
The n-MOS transistor operates in strong
inversion when
VGS  VTN  
In most practical cases the typical value
of  is about 0.1V, i.e.
VGS  VTN    0.1V
The difference VGS-VTH is called the
effective gate-source voltage Veff . Finally
the n-MOST is in strong inversion when
Ve ff  VGS  VTN  0.1V
The figure shows the family of output
characteristics of the n-MOST (ID vs. VDS
for different values of VGS).
The area of characteristics is separated in two regions by curve, which fulfill the condition
VDS = VGS-VTN . The first region is on the left side and it is characterized with nearly linear
dependence between ID vs. VDS. It is called linear (ohmic or triode) region. In the another
region the current ID is practically independent on the VDS. It is called saturation (active,
pinch-off) region.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
12
DC modeling in linear region
The condition for operation in
strong inversion is
Ve ff  VGS  VTN  0.1V
The condition for operation in
linear region is
VDS  Veff  VGS  VTN
The equation for the drain current
where mn is the mobility of
electrons, Cox is the gate
capacitance per unit area, W is the
gate width and L is the effective
gate length.
The above figure presents the DC equivalent circuit of the n-MOST in linear region.
The transistor is modeled with resistance RLIN, which is practically independent of
VDS.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
13
Small signal model in linear region
The high-frequency equivalent circuit of
the MOST in linear region include a
resistor and four parasitic capacitors.
In case of low-frequency operation only
the resistor is important.
rds is the small signal drain-source resistance, which is equal to the RLIN from DC model.
Cgs and Cgd are gate-to-source and gate-to-drain capacitances.
Csb and Cdb consist of depletion capacitances of source and drain junction. Each of them
includes also the corresponding junction-to-substrate and junction-sidewall capacitance.
The respective equations are
where Cox is the gate capacitance per unit area; LD is the gate-source (or gate-drain)
overlap; Cj0 is the depletion capacitance per unit area; As (Ad) is the area of the source
(drain); VSB (VDB) is source (drain)-to-substrate voltage; F0 is the built-in voltage of
the junction.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
14
DC operation in saturation
The condition for operation in
strong inversion is
Ve ff  VGS  VTN  0.1V
The condition for operation in
saturation region is
VDS  Ve ff  VGS  VTN
The drain current in saturation is
given with equation
As it is shown on the figure, ID rises somewhat for increasing the VDS. This is the channellength modulation effect, which causes the nonzero slope in the output characteristic. To rend
an account this effect, the parameter ln is included in the above equation. It is is denoted as a
channel-length modulation parameter. ln is inverse proportional to the channel length. For
hand-calculations, usually the simplified formula, shown bellow is used. In this formula the
new parameter VE [V/mm] is a constant for a certain technology.
l
CMOS Analog IC
Emil D. Manolov, TU-Sofia
1
VEL
Basic analog models for CMOS Technology
15
DC model in saturation
The figure presents the DC equivalent
circuit of the n-MOS transistor in saturation.
This model is based on the equation for the
ID discussed in the previous slide
The equivalent circuit consists of an voltage-controlled current source IDSAT and a
resistor RDS. Their values are
In most cases, for hand-calculations, a simplified DC model of the MOS transistor is
used. This model neglects the slope in the output characteristics and contains only the
voltage-controlled current source.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
16
Small signal low-frequency model in saturation
The low-frequency
equivalent circuit of the
MOST in saturation
consists of a resistor and
two voltage-controlled
current sources.
The source gmvgs is the basic component of the model. It presents the
dependency of the output current from the input control voltage vgs.
The gm is known as transistor transconductance.
The second source models the body effect in the transistor - when the vsb is
applied between the source and the body, the output current decreases.
The gmb is called body transconductance.
The small signal source-drain resistor ro gives an account the finite output impedance
of the transistor.
In most applications the body and the source of the transistors are short connected,
which remove the second source from the equivalent circuit. The gmb is much smaller
then gm and the second source can be ignored even in the case when the source is
connected to small-signal generator.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
17
Small signal parameters - definitions
Based on the discussions in the previous slide now we will define the parameters of the
low-frequency equivalent circuit of the MOS transistor.
Using the equation for DC output current in saturation we can find the transistor
transconductance gm as
gm 
ID
W
W
2I
 m nCox
Ve ff  2m nCox
ID  D
 VGS
L
L
Ve ff
After complex transformations the body transconductance gmb is determined as
g mb 
ID
 I D  VTN
g m


 VSB  VTN  VSB 2 VSB  2j F
Usually the body transconductance gmb is about (10…30)% from the transistor
transconductance gm.
The small-signal drain-source (output) resistance of the MOS transistor is equal of
rds 
CMOS Analog IC
Emil D. Manolov, TU-Sofia
 VDS
 lI DSAT  lI D
ID
Basic analog models for CMOS Technology
18
Small-signal common gate equivalent circuit
The figure shows the smallsignal common gate equivalent
circuit for low-frequency
operation of the MOS transistor
in saturation.
The circuit is obtained from the previous general model through appropriate
transformations.
The model consists of a small-signal source-gate (input) resistor and voltage-controlled
current sources. The small-signal output (drain-gate) resistance is ignored, because of its
very high value.
The input resistance is inverse proportional of the sum of the transistor and body
transconductances. Its value is small (usually between 2k and 20k).
The output current is a product of the sum of the two transconductances and the input
small-signal source-gate voltage.
In most cases the value of the body transconductance gmb is smaller then the transistor
transconductance gm and can be ignored for hand-calculations.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
19
High-frequency equivalent circuit
The high-frequency equivalent circuit of the MOS transistor in saturation has the same
structure as the low-frequency circuit. Additionally the parasitic capacitors are included.
Cgd is a gate-drain overlap capacitor. It is caused to the unwanted diffusion under the
gate and drain regions.
Cgs includes gate-source overlap capacitor and a part of the gate-bulk capacitor.
Cdb and Csb are the capacitances of the bulk-drain and bulk-source junctions.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
20
Equations for the parasitic capacitances
2
WLC ox  WL DCox;
3
Csb  ( A s  WL )C js  PsC jsw ;
Cgs 
C js 
C j0
1  VSB / F 0
;
C jd 
Cgd  WL DCox;
Cdb  A dCid  PdC jsw ;
C j0
1  VDB / F 0
;
C jsw 
C jsw0
1  VSB / F 0
.
Above are presented the equations for computation of the parasitic capacitances,
where -Cox is the gate capacitance per unit area; - LD is the gate-source (or gatedrain) overlap; - As (Ad) is the area of the source (drain); - Ps (Pd) is the length of the
perimeter of the source (drain) junction; - Cjs (Cjd) is the depletion capacitance of the
source (drain) junction; - Cj0 is the depletion capacitance per unit area of the source
(drain); -Cj-sw is the sidewall capacitance per unit length of the drain (source);
Cj-sw0 is the sidewall capacitance per unit length at 0V bias voltage; F0 is the builtin voltage of the junction.
Very often the designers avoid to hand-calculate the above described capacitors,
relying on the result from the simulations.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
21
MOS transistor frequency response
The transition frequency fT specifies the frequency capability of the MOST. fT is
defined as frequency where the magnitude of the short-circuit, common-source current
gain falls to unity. The high-frequency behavior of the transistor is controlled by the
capacitors in the small-signal model, which cause the input gate current to increase as
frequency increases. To determine fT the above circuit is used. It is built on the base of
the previous discussed high-frequency model. From this circuit we can find
io
gm

1
i i 2fT Cgs  Cgd


fT 
gm
3 m n ( VGS  VTN )

2 Cgs  Cgd
4
L2


Hence, for high-speed circuit design minimum channel length should be used.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
22
Short-channel MOS transistor
The figure presents the output
characteristics of two n-MOST,
implemented on 0.35mm CMOS
technology. The first transistor
(dashed lines) has the minimum
allowed channel length L=0.35mm.
It is known as short-channel
transistor. The second transistor
(solid lines) has L=3mm. This is
long-channel transistor. The W/L
ratio of both transistors is 1.
The comparison of the output characteristics of the transistors gives the conclusions that the
short-channel devices have a smaller output impedance than the long-channel transistors and
that their output current is smaller than the discussed above formulas predict. To avoid the
above problems, some authors propose to modify the classical square-law equations in order
to make the characteristics more linear. This approach is more complex and it is not
appropriate for the hand-calculations. The general solution is to design deliberately the
many of the transistors in the analog circuits to have channel lengths from 5 to 20 times
larger than the minimum allowed by the technology.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
23
Temperature dependence in MOST
The transconductance characteristic
of n-MOS transistor for different
temperatures is shown on the figure.
The threshold voltage VTN and the
transconductance parameter mnCox
change with temperature.
The threshold voltage VTN has a
negative temperature coefficient
TCVTN 
1 dVTN
ppm
 3000 
VTN dT
C
The temperature coefficient of the transconductance parameter mnCox is connected
with the temperature coefficient of the mobility
1.5
T
1.5
m n (T)  m n (T0 ) 
TCmn  
T
 T0 
At low-drain currents the negative TCVTN dominates the changes in the drain current,
while at higher currents the temperature coefficient of the mobility is dominating.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
24
Noise
v i2
2 1
Kf
 4kT

f
3 gm WLC oxf
The figure shows typical
equivalent input noise voltage
spectral density for MOST in
saturation.
The dominant noise sources are
flicker and thermal noises.
The flicker noise is modeled as a
voltage source in series with the
gate. The thermal noise can be
modeled as current source
between drain and source.
To simplify analysis the voltage and current sources can be replaced by one equivalent
input noise source, which is given with the above formula. The first component presents
the thermal noise and the second – flicker noise. The thermal noise is inverse
proportional to the transconductance of the transistor and the flicker noise is the inverse
proportional to the transistor area, i.e. larger devices have less 1/f noise. The constant Kf
in the equation depends on device characteristics and can vary widely for the different
devices in the same process.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
25
Variation of the parameters
The device parameters in integrated circuits vary from run to run and from wafer to
wafer. As a result, the values of the threshold voltage VTN and the transconductance
parameter mnCox can change up to ±50% from its nominal value. Most parameters
follow a "normal" (Gaussian) distribution. It is characterized with a mean value, at
which the number of occurrences is maximum. A deviation of ±s (sigma) from this
point contains 68.3% of all measured values. If the deviation is three times larger
(±3s) - the 99.73% of all measurements are enclosed. The goal of the design is to
create a product, which can withstand a variation of each and every device parameter to
at least 3s.
So, we have to know how to check the output parameters of the designed circuit at 3s
deviation. The most reliable approach is Monte Carlo analysis, which varies the device
parameters in a random fashion, so that every combination of variations is covered.
This is also what we get in production.
There is in use what is called a "four-corner analysis". Device parameters are combined
together in four groups, representing extremes, or worst cases. This is a simple method,
which is intended to predict the fastest or slowest speed of digital ICs. Despite of this
method does not guarantee the reliable results for analog circuits, for the present time it
have a large application in practice.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
26
Subthreshold operation
The MOST operates in subthreshold
region when Veff<100mV. In this area
the accuracy of the square-law equations
is poor. The current is more accurately
modeled by an exponential relationship
so, the MOST transfer characteristics
look like to the BJT. The figure shows
the drain current against drain-source
voltage for five values of Veff. The drain
current is almost constant when VDS > (3…4)jT and the equation for ID is
 V  VTN 0 
 W
 where
I D  I D0   exp GS
njT
L


n  1
CBC
Cox
The constant ID0 depends on the technology and is around 20nA. CBC is the depletion bulkchannel capacitance. The value of n is around 1.5.
Because of the small bias currents the presented region is characterized with small value of
the transconductance and slow transistors. The matching of the transistors is difficult
because it now strongly depends on transistor threshold voltage matching.
MOST operates in subthreshold rarely, mainly in low frequency and low power
applications.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
27
Vertical bipolar transistor
Figure shows a vertical pnp bipolar transistor implemented in standard CMOS
technology. The n-well forms the base of transistor, the source (drain) diffusion – the
emitter, and collector is tied to the p-substrate.
If the substrate is n-type – the corresponding transistor is npn.
This type of transistors are particularly employed in band-gap references, and in output
stages.
The main disadvantage of this transistor is that its collector (the substrate of the IC) is
definitely connected to a power supply.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
28
Lateral bipolar transistor
Figure shows a lateral pnp BJT implemented in standard CMOS technology. The n-well
forms the base, the source (drain) diffusion – the emitter and the lateral collector. The
emitter and collector of this transistor correspond to the source and the drain of a p-MOS
transistor. To disallow its operation, the gate is connected to the highest supply voltage.
The base width corresponds to the channel length of the MOS transistor, which can be very
small. Thus, the bF and fT of the lateral transistors can be very high. The limitation of this
structure is that the vertical parasitic transistor appears. Its emitter and base are the same as
for the lateral transistor, but the collector is the substrate. This causes the appearance of the
undesired current ICV, which is comparable to the basic current ICL. To minimize the losses
different layout techniques are applied.
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
29
DC modeling of BJT
IE  IC  IB  IC
 V  V 
I C  J S A exp  BE 1  CE 
 jT  VAF 
IB 
V 
JS
A exp  BE 
bF
 jT 
bF 
aF
1  aF
VBE  jT ln
CMOS Analog IC
Emil D. Manolov, TU-Sofia
aF 
IC
JSA
bF
1  bF
In analog integrated circuits BJT operates
mostly in the forward active region. Picture
shows the DC equivalent circuit of npn
BJT. The model for pnp is similar, only the
polarities of the voltages and the directions
of the current must be inverted.
Below the picture are presented the basic
DC equations. The condition to operate in
active region is: VBE>0.5V and VCE>0.3V.
JS, bF, aF and VAF are process dependent
parameters: JS is the transport saturation
current density; bF and aF are well known
current gain coefficients; VAF is the Early
voltage.
A is the design parameter. It is equal to the
area of the emitter.
Typically in hand calculations, the emitter
and collector currents are considered to be
equal, as well as the VCE/VAF ratio usually is
neglected.
Basic analog models for CMOS Technology
30
Small-signal BJT model
The typical small-signal equivalent circuit of BJT consist of: rb - the resistance of the
semiconductor material between the base contact and the effective base region; Cbe the capacitance of the emitter junction; Ccb - the capacitance of the collector junction;
Ccs - the capacitance of the collector-substrate junction; r - the small-signal emitter
resistance; gm - the transconductance; ro - the small output resistance; Cj0 - the
depletion capacitance per unit area of the source (drain).
r 
 VBE j T b F


 IB
I B gm
ro 
Cbe C j  Cd  2A EC je0  g m  b
CMOS Analog IC
Emil D. Manolov, TU-Sofia
 IC
V
 AF
 VC E
IC
Ccs 
A TC js0

V 
 1  C S 
F s0 

12
Basic analog models for CMOS Technology
gm 
 IC
I
b
 C  F
 VBE j T g m
Ccb 
A CC jc0

V 
 1  C B 
F c0 

13
31
Instructions for self-study
The past presentation gives only a first sight on the hand-calculation models for
CMOS active devices. After reading and understanding the presented information
you have to study the material from at least one of the following textbooks:
- R. Baker, H. Li, D.Boyce. CMOS Circuit Design, Layout and Simulation, IEEE
Press, New York, 2005, ISBN 0-7803-3416-7. Chapter 5, pp.84-105.Chapter 9,
pp.165-184.
- Ph. E. Allen, D. R. Holberg. CMOS Analog Circuit Design, Oxford University
Press, Inc., 2002. ISBN 0-19-511644-5, Chapter 3, pp. 72-112, Appendix B, pp.
744-767.
- F. Maloberti. Analog design for CMOS VLSI Systems. Kluwer Academic
Publishers, 2003, eBook ISBN: 0-306-47952-4, Print ISBN: 0-7923-7550-5,
Chapter 1, pp.1-54.
The next step in the learning process is to study the examples and complete the
experiments, which are presented in Guided exercise 1
After that you can go on to the next part : CMOS Biasing Circuits
CMOS Analog IC
Emil D. Manolov, TU-Sofia
Basic analog models for CMOS Technology
32