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ICCM_HLD_092904.doc High level Design for an Implanted Central Communications module This document is a high level description of a compact wireless system for acquiring ~100 Channels of neural data. The design is prefaced by work by Wolf, Obeid, Marizio, Nicolalous and others. The design is a tiny piece of a DARPA funded project to build a brain-machine interface. 1 Revision history Date Revision By Notes 9/29/04 Initial Draft Steve Callender First draft High-level ICCM design released for review. 2 Table of Contents High level Design for an Implanted Central Communications module .............................. 1 1 Revision history .......................................................................................................... 1 2 Table of Contents ........................................................................................................ 2 3 Overview of Neural Data Acquisition System............................................................ 3 4 ICCM High level Design ............................................................................................ 4 4.1 Programmable Logic Section .............................................................................. 4 4.1.1 DHSM interface block ................................................................................ 5 4.1.2 Data Reduction block .................................................................................. 5 4.1.3 I/O Handler Block ....................................................................................... 5 4.1.4 Digital Data path Block .............................................................................. 6 4.1.5 RF transceiver Block................................................................................... 6 4.2 FPGA device selection ........................................................................................ 6 4.3 Bi-directional radio frequency digital data transceiver module .......................... 7 4.4 Power supply....................................................................................................... 8 4.5 EEPROM .......................................................................................................... 10 4.6 Reset Generator ................................................................................................. 10 4.7 Clock Source ..................................................................................................... 10 4.8 Connectors ........................................................................................................ 11 4.8.1 DHSM connector ...................................................................................... 11 4.8.2 Power Connector ....................................................................................... 11 4.8.3 Digital Data path Connector ..................................................................... 11 4.8.4 JTAG connector ........................................................................................ 12 4.9 Physical Layout ................................................................................................. 12 4.10 Packaging .......................................................................................................... 13 5 Required Materials .................................................................................................... 13 6 References ................................................................................................................. 13 7 Appendix A: Xilinx device tables ............................................................................. 14 2 3 Overview of Neural Data Acquisition System The following document provides a high level design for a component of a Brain Machine interface. The component is the Implanted Central Communications module (ICCM). Each 96-channel Brain Machine Interface (BMI) system consists of three (3) identical digitizing headstages (DHSM) one ICCM, one wearable communications unit (WCM), a Computer, and actuator. See the figure below for a high level view of the system DATA Power & CLOCK DHSM RF COIL RF COIL RF COIL RF COIL DATA RF COIL RF COIL ICCM Power & CLOCK WCM Figure 1: Neural Data Acquisition System 3 NETWORK CPU ACTUATOR 4 ICCM High level Design The ICCM controls the headstages, and collects, processes, and transmits the neural data. The ICCM is approximately the size of a package of cigarettes. The block diagram below shows the major components. D H S M DHSM INTERFACE 16 CHANNELS DATA REDUCTION 16 CHANNELS DATA REDUCTION 16 CHANNELS DATA REDUCTION - CONFIGURATION REGISTERS - DATA ARBITRATION AND MUX -SIMPLE PROTOCOL STACK - RESET BEHAVIORS 16 CHANNELS DATA REDUCTION DIGITAL DATA CONNECTOR I/O HANDLER DIGITAL DATAPATH INTERFACE D H S M 16 CHANNELS DATA REDUCTION DHSM INTERFACE D H S M DHSM INTERFACE PROGRAMMABLE LOGIC DEVICE 16 CHANNELS DATA REDUCTION EEPROM CLOCK SOURCE ANTENNA RF TRANSCEIVER INTERFACE POWER_ON RESET GENERATOR POWER RECTIFICATION & FILTERS & SUPERCAP +5, +3.3, +2.5, +1.8 REGULATORS POWER_ON_RESET POWER CONNECTOR BIDIRECTIONAL RADIO FREQUENCY DIGITAL TRANSCIEVER MODULE JTAG CONNECTOR Figure 2: ICCM Block Diagram 4.1 Programmable Logic Section The majority of the functions of the ICCM are implemented in a programmable digital logic device. 4 4.1.1 DHSM interface block A DHSM interface block controls each DHSM. The ICCM provides power and control signals to the DHSM. The DHSM provides a continuous serial data stream to the ICCM. 4.1.2 Data Reduction block Each data reduction block acquires data from a DHSM interface block, performs data reduction operations, and provides data to the I/O handler block. The data reduction process is performed in parallel by multiple instances of the data reduction logic. 4.1.2.1 Data reduction algorithms A number of data reduction algorithms are be supported. 4.1.2.1.1 Best 8/12 bits This data reduction algorithm determines the most valuable 8 of the 12 input bits. 4.1.2.1.2 Spike Detection This data reduction algorithm works on 8 bit wide data. It detects and stores spikes. The spikes are stored as 40byte (?) samples along with a timestamp. 4.1.2.1.3 Binning This algorithm counts detected spikes for each electrode and outputs a ‘bin count’ at a periodic interval (often 100ms). Each bin count indicates the number of spikes detected during the last interval. A nice thing about binned data is that the output data rate is constant. 4.1.2.1.4 Data reduction bypass It is possible to bypass the data reduction algorithms. This allows the downstream interfaces to ‘see’ the raw data. Because of the high data rate of the raw data, it is not practical to transmit more than a few channels of raw data at a time. 4.1.2.2 Interface to I/O Handler Logic Block Each data reduction block has a data interface and a configuration interface. The data interface is for processed or unprocessed neural data headed downstream for transmission. The data interface is 8 bits wide with some handshaking lines. The configuration interface allows the I/O handler block to configure each of the data reduction devices. The configuration interface is undefined. 4.1.3 I/O Handler Block The I/O Handler logic block handles both control and data paths. Streaming data is collected and passed downstream. Control information is registered, and passed upstream. 5 4.1.3.1 Configuration and Control logic The I/O handler block accepts configuration and control information from the digital data path interface, and or the RF transceiver interface. The configuration information is stored in registers, and distributed to upstream locations. 4.1.3.2 Data path logic The I/O Handler reads spike data from each of the data reduction blocks. The data reduction blocks indicate when data is available. The data format includes channel number, timestamp, and samples. The I/O handler accepts all the data from all 96 input channels. The data is sorted against an enabled channel list, and entered into an output queue. The data in the output queue is passed on to the digital data path interface, and or the RF transceiver interface 4.1.4 Digital Data path Block The digital data path block interfaces between the I/O handler block and the Digital data path connector. The data interface is parallel, and bi-directional. The digital data path is intended as an aid during development. It will be functionally replaced by the RF transceiver interface as the project develops. 4.1.5 RF transceiver Block The RF transceiver block interfaces between the I/O handler block and the RF Transceiver module. The RF side of this interface is bi-directional Half-duplex serial, and likely involves some line encoding and decoding. The I/O handler side of this interface is parallel and has an interface similar to the Digital Data path block. 4.2 FPGA device selection Dr. Obeid’s 16-channel implementation of a Spike-detection algorithm was implemented in a Spartan II Xilinx device. The table below makes a rough estimate at the programmable logic requirements of a 96channel system. See Appendix A for details. For approximation purposes, memory and gates are assumed to scale linearly with the number of channels in the system. The data reduction algorithm is assumed to be about the same size as the I/O handler block. 6 Design DEVICE Obeid Design Spartan II XC2S100 (TQFP144 22x22mm) Spartan II XC2S200 (PQ208 30x30mm) (FT256 17x17mm) VIRTEX II XC2V1000 32 channel Reduction device 96 channel single integrated device # channels 16 Clock rate 12mhz Block ram Gates 10BLOCKS/ 40k 100,000 32 12 (20/80k) 56K (200,000) 200,000 96 12/(24?) (120/500k) 720K (800,000) 1M (FG456 23X23mm) Table 1: FPGA logic and memory comparison 4.3 Bi-directional radio frequency digital data transceiver module The Bi-directional radio frequency transceiver module is mounted on the ICCM board. The radio module telemeters data to and from the ICCM. Digitized neural data from the ICCM makes up the bulk of the transfers. Configuration data is transferred to the ICCM only during setup. How can the user force the ICCM to turn the bus around for configuration? How can the user signal a change in single channel number? The transceiver is based on the RFM TR1100. The TR1100 is a 916.50MHz Hybrid module capable of transferring 100Mbits/second. 7 Below are some of the design requirements for the transceiver Physical Size Module is 7mm X 10mm excluding external components and antenna. Data Rate RAW data rate is 1MegaBit per second Actual throughput is less due to line coding. Power Consumption Power efficient: 0.1 to 0.3W Voltage Operates from 3.3V Range Desired range is ~10mm down to 2mm Communications Digital bi-directional communication is required. Protocol Half Duplex communication is supported by module No High-level communication s protocol is used. Low Level line encoding (4b/5b) is implemented to preserve 1’s density. Immunity to RF The transceiver module must work in close proximity to the RF from Transcutaneous power coils. power Table 2: Transceiver design requirements The Table below shows the required RF Telemetry links for three features. Full rate Data samples per second kilobits per channels second per per system system bits per sample 31,250 16 12 10 8 100 bits per second per channel 50000 37500 31250 25000 kilobits per second per channel 500000 375000 312500 250000 500 375 312.5 250 Spike Data only samples per Spike spikes per bits per second per second per channels bits per second channel channel per system per system Bits per sample 50 8 90 36000 100 kilobits per second per system 3600000 3600 Binned spike counts only bits per second per channel Binning period bits per (seconds) bin 0.1 8 80 channels bits per second per system per system 100 kilobits per second per system 8000 Table 3: Required Telemetry data rates 4.4 Power supply The power supply section of the ICCM works with a single voltage input. The input voltage comes from a transcutaneous power coil, or from a wired connection. 8 8 The table below summarizes the power requirements for the electronics in a system consisting of one ICCM and three headstages. Power Current Current at Current at Current at per Devices Power per at 5 volts 3.3Volts 2.5 volts 1.5 volts device per system Device (mA) (mA) (mA) (mA) (mW) system (mW) Notes DHSM 45.5 38.9 0.021 0 355.9 3 1067.8 Measured value XCV21000 27 250 464.1 2 928.2 2x quiescent max TR1100 12 39.6 1 39.6 XMIT mode 2036 mW Table 4: ICCM & 3 DHSM voltages and currents All voltages leaving the power supply section are clean, quiet, and well regulated DC. The designers’ preference is to use low-noise low-dropout linear regulators. A preferred device family is: Linear Technology: LT1962EMS8 300mA output current 270mV dropout 20uVRMS noise (10Hz to 100Khz) Fixed and adjustable output voltages available in 3mm X 5mm MSOP8 package Table 5: Recommended Linear Regulator The Table below shows the VI power losses associated with using parallel linear regulators on the ICCM. Parallel linear regulators Input Voltage Regulated Voltages Regulated currents (mA) REGULATED POWER (mW) Wasted power (mW) REQUIRED Power (mW) 6.5 5 135 675 202.5 877.5 3.3 182.7 602.91 584.64 1187.55 2.5 0.063 0.1575 0.252 0.4095 1.5 Total mW 500 2028.1 750 3287.4 2500 5315.5 3250 Table 6: power costs for parallel linear regulators Power sequencing issues will be studied and addressed in the detailed design. The power supply has a built in ‘super-cap’ to allow for variation in the input voltage that may occur during alignment of the transcutaneous power coils. 9 4.5 EEPROM The EEPROM stores the program for the programmable logic device in non volatile memory. When the ICCM comes out of reset, then FPGA programs itself from the EEPROM. The EEPROM is programmed in system via the JTAG connection. Should the EEPROM be sized to accommodate TWO versions of the FPGA code? One for fallback & one to support RF link programming? 4.6 Reset Generator All digital devices are held in reset until the reset generator releases the reset line. The reset generator monitors the voltage levels & de-asserts reset only after all monitored voltages are deemed to be in an acceptable range. A provision for a soft reset is included in the FPGA design. It is possible for a reset command to be sent over the radio link. This reset signal is received by the FPGA and is then driven by the FPGA to reset all the DHSM modules, and the radio link. A population option exists for a magnetic reed switch to be used to assert reset to the ICCM. Due to the magnetic fields produced by the transcutaneous power coils, the magnetic switch placement may be distant from the ICCM. 4.7 Clock Source The clock source is undecided. There are three options: a clock derived from a recovered the transcutaneous power clock frequency a crystal oscillator on the ICCM mainboard a clock derived from the RF link circuitry. The following clock frequencies are involved in the ICCM design. RF CLK (900+MHZ) carrier frequency for RF telemetry link FASTCLK oscillator frequency required for digital Phase Lock loop. (Any derived or recovered clock will require a high speed clock.) 12MHZ Oscillator frequency for OBEID 16 channel data reduction algorithm, and 32 channel DHSM. 500KHZ sample rate for 32channel Headstage running two (2) 16chanel paths. (Loopclk Freq) 250 KHz transcutaneous power base frequency . (4Watts to 50 Ohm load 8/30/04) 64.5 KHz Filter Clock used by PA16MUX 31.25 KHz Per channel sample rate Table 7: ICCM clock frequencies 10 4.8 Connectors 4.8.1 DHSM connector There are three DHSM connectors. Each connector connects the ICCM to a 32channel digitizing headstage (DHSM). The DHSM signals are a combination of medium-speed digital, and power lines. The DHSM connectors on the ICCM have not been specified. The DHSM_01 design uses a flat flex cable with 14 pins on 1mm spacing (REFXX) The DHSM_01 mates with the following flex connector: Hirose FH10A series SMT ZIF type Flexible PCB connectors (REF #XX) Part Number: FH10A-14S-1SH: 14pin connector without Boss Table 8: DHSM flat flex connector 4.8.2 Power Connector The power connector has three population options: 1) Two large plated holes for wire connection to the transcutaneous power secondary coil 2) Two large plated holes for a coaxial power jack 3) Three plated pads, two for power in, and one for ‘ACGND’ connection. 4.8.3 Digital Data path Connector The digital data path connector is a bi-directional port for both acquired data and configuration data. The I/O handler block masters the data on this port. The Digital Data path connector can be mated to a digital data interface like, a Digital Data Acquisition card, or a logic analyzer. 11 Signals on the digital data path connector include the following: Signal Bits Direction relative to Notes ICCM Bi-directional data 8 Bi-directional WRITE 1 Out READ 1 Out Ready_to_write 1 Out Ready_to_read 1 In Reset_Digital_port 1 Out Pulled inactive (Reset remote device) Reset host 1 In Pulled inactive (External reset to CM) Synch clock 1 Unknown Clock line to synch ICCM to external device +5 volts 2 Out Clean Power +3.3 Volts 2 Out Clean Power Digital Ground 16 Bi-directional How many pins really needed? 8-16? Table 9: signals on digital data path connector 4.8.4 JTAG connector The JTAG connector will be used extensively during prototype development. In the ‘final’ version of the implant design, the JTAG port will be used once to program the FPGA, EEPROM, and CPLD devices. The JTAG connections are made through the same physical connector as the digital data path connections. The JTAG chain will be configured to allow for automatic bypass of un-connected headstages. At the cost of added components and complexity, it may be possible to re-program the FPGA over the radio link. This requires a bunch of hooks, including a partitioned xilinx EEPROM with a failsafe boot kernel. At the cost of added wires and design complexity, it may be possible to re-program the CPLD’s on each of the DHSM modules from the FPGA program. 4.9 Physical Layout The ICCM is a single circuit board. The board has a number of connectors and is encapsulated in a biocompatible medium when used as an implant. Below is a scale drawing of the ICCM. 12 70.00 D H S M POWER COIL D H S M PWR D H S M 50.00 XILINX 17X17mm ANTENNA RFC 60mm spiral Figure 3: Scale drawing of ICCM 4.10 Packaging The ICCM Board and the RF module are encapsulated in a biocompatible medium. The Secondary coil will likely be encapsulated separately. 5 Required Materials Known good RF Transceiver Working DHSM modules Flip Chip Machine for assembling uBGA Packages onto circuit Board System for simulating neural Signals Known good spike detection algorithm Biocompatible packaging expertise 6 References 1) Detailed Design Document for Brain Machine Interface (BMI) 32 channel Digitizing Headstage Module (DHSM). By Steve Callender: Duke University BME Dept., Revision #5: 4/01/04. 2) DATASHEET: Xilinx Virtex-II Platform FPGAs: Complete Data Sheet DS031 (v3.3) June 24, 2004. 3) DATASHEET: Hirose FH10A series SMT ZIF type Flexible PCB connectors. 1.0mm contact pitch. Recommended thickness of flexible circuit board 0.25 to 0.35mm 4) DATASHEET: Linear Technology: LT1521/LT1521-3 LT1521-3.3/LT1521-5: 300mA Low Dropout Regulators with Micropower Quiescent Current and Shutdown. Doc # 1521335fb c1995. 13 5) DATASHEET: RFM 916.50 MHz Hybrid Transceiver: filename: tr1100za.vp, 2003.08.19 7 Appendix A: Xilinx device tables This section contains tables that may be useful for choosing the appropriate programmable device. 14 --- END OF DOCUMENT --- 15