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Design and Implementation of VLSI Systems (EN1600) Lecture 15: Interconnects Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson] S. Reda EN160 SP’08 Transistors + Wires = Circuits • Wires (interconnects) are as important as transistors – Speed – Power – Noise • Alternating layers run orthogonally S. Reda EN160 SP’08 How interconnects contribute to delay and power? • Interconnects have resistance, capacitance (and inductance) • Interconnects increase circuit delay: – The wire capacitance adds loading to each gate – Long wires have significant resistance that further contribute to the delay • Interconnects increase dynamic power: – Because of the wire capacitance S. Reda EN160 SP’08 Wire geometry • Pitch = w + s • Aspect ratio: AR = t/w – Old processes had AR << 1 – Modern processes have AR 2 • Pack in many skinny wires S. Reda EN160 SP’08 1. Wire Resistance • ρ = resistivity (W*m) • R = sheet resistance (Ω/) – is a dimensionless unit(!) S. Reda EN160 SP’08 How does the kind of metal impact resistivity? • Until 180 nm generation, most wires were aluminum • Modern processes often use copper – Cu atoms diffuse into silicon and damage FETs – Must be surrounded by a diffusion barrier S. Reda EN160 SP’08 Contact and via resistance • Contacts and vias also have 2-20 Ω • Use many contacts for lower R – Many small contacts for current crowding around periphery S. Reda EN160 SP’08 2. Wire capacitance • Wire has capacitance per unit length – To neighbors – To layers above and below • Ctotal = Ctop + Cbot + 2Cadj s w layer n+1 h2 Ctop t h1 layer n Cbot Cadj layer n-1 S. Reda EN160 SP’08 Factors impacting the capacitance • Parallel plate equation: C = eA/d – Wires are not parallel plates, but obey trends – Increasing area (W, t) increases capacitance – Increasing distance (s, h) decreases capacitance • Dielectric constant – e = ke0 • e0 = 8.85 x 10-14 F/cm • k = 3.9 for SiO2 • Processes are starting to use low-k dielectrics – k 3 (or less) as dielectrics use air pockets S. Reda EN160 SP’08 M2 capacitance data (180nm) 400 350 300 M1, M3 planes s = 320 s = 480 s = 640 s= 200 8 Ctotal (aF/m) 250 Isolated s = 320 150 s = 480 s= 50 0 0 500 1000 1500 2000 w (nm) • Typical wires have ~ 0.2 fF/mm – Compare to 2 fF/mm for gate capacitance) • Polysilicon has lower C but high R – Use sparingly for very short wires between gates S. Reda EN160 SP’08 8 s = 640 100 Given R and C, how to calculate interconnect delay? • Wires are a distributed system – Approximate with lumped element models N segments R R/N C R/N C/N C/N R R C L-model C/2 R/N R/N C/N C/N R/2 R/2 C/2 p-model C T-model • 3-segment p-model is accurate to 3% in simulation • L-model needs 100 segments for same accuracy! S. Reda EN160 SP’08 Interconnect delay: the lumped case Vm 0V S. Reda EN160 SP’08 Vout Interconnect delay: ideal analysis Ideally, modeling using diffusion equation; tpd~0.38RC S. Reda EN160 SP’08 Interconnect delay: distributed Elmore delay R1 R2 R3 C1 C2 S. Reda EN160 SP’08 RN C3 r = resistance per unit length CN c = capacitance per unit length Delay calculations Assuming ideal wires: Realistic wire modeling: S. Reda EN160 SP’08 Layer stack • AMI 0.6 m process has 3 metal layers • Modern processes use 6-10+ metal layers Intel 180nm process • Example: Intel 180 nm process • M1: thin, narrow (< 3l) – High density cells • M2-M4: thicker – For longer wires • M5-M6: thickest – For VDD, GND, clk 2000 1800 1600 1400 1200 t(nm) 1000 w (nm) 800 600 400 200 0 6 5 4 3 2 m etal layer Why do you think different metal layers have different widths/thickness? S. Reda EN160 SP’08 1