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Design and Implementation of VLSI Systems (EN1600) lecture09 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson] S. Reda VLSI Design Summary of transistor operation NMOS transistor S. Reda VLSI Design PMOS transistor DC transfer characteristics S. Reda VLSI Design PMOS on (linear), NMOS off • Vin = 0 Vin0 Idsn, |Idsp| Vin0 Vout S. Reda VLSI Design VDD PMOS on (linear), NMOS on (saturation) • Vin = 0.2VDD Idsn, |Idsp| Vin1 Vin1 Vout S. Reda VLSI Design VDD PMOS on (linear ~ sat) and NMOS (sat) • Vin = 0.4VDD Idsn, |Idsp| Vin2 Vin2 Vout S. Reda VLSI Design VDD PMOS on (sat) NMOS on (linear) • Vin = 0.6VDD Idsn, |Idsp| Vin3 Vin3 Vout S. Reda VLSI Design VDD PMOS on (off ~ linear) and NMOS on (linear) • Vin = 0.8VDD Vin4 Idsn, |Idsp| Vin4 Vout S. Reda VLSI Design VDD NMOS on (linear) and PMOS cut off • Vin = VDD Vin0 Idsn, |Idsp| Vin5 Vin1 Vin2 Vin3 Vin4 Vout S. Reda VLSI Design VDD Summary of voltage transfer function A B C S. Reda VLSI Design D E Noise margins S. Reda VLSI Design CMOS inverter noise margins desired regions of operation S. Reda VLSI Design What is the impact of altering the PMOS width in comparison to the NMOS width on the DC char? polysilicon gate Idsn, |Idsp| W tox Vin3 n+ Vin3 Vin3 L n+ SiO2 gate oxide (good insulator, ox = 3.9) p-type body Vin3 Vout VDD If we increase (decrease) the width of PMOS compared to NMOS for the same input voltage, a higher (lower) output voltage is obtained V out S. Reda VLSI Design V in Impact of skewing transistor sizes on inverter noise margins Increasing (decreasing) PMOS width to NMOS width increases (decreases) the low noise margin and decreases S. Reda VLSI Designthe high noise margin (increases) Pass transistor DC characteristics As the source can rise to within a threshold voltage of the gate, the output of several transistors in series is no more degraded than that of a single transistor S. Reda VLSI Design Summary Ideal transistor characteristics Non-ideal transistor characteristics Inverter DC transfer characteristics Simulation with SPICE and integration with L-Edit S. Reda VLSI Design