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Lecture 4
MARIE:
An Introduction to a Simple Computer
Lecture Duration: 2 Hours
Lecture Overview
 Introduction
•
•
•
•
•
•




CPU Basics and Organization
The Bus
Clocks
The Input/Output Subsystem
Memory Organization and Addressing
Interrupts
Instruction processing
A simple program
A discussion on assemblers
Extending our ISA
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2
Introduction
Outcomes (1/1)
 From Chapter 1, 2 and 3 we learned about:
• Computer systems and components
• How data is stored and manipulated inside
different computer systems.
• The fundamental components of digital circuits.
 From now on, we will be interested in:
• How computer components work?
• and how they fit together to create useful
computer systems?
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Introduction
CPU Basics and Organization (1/5)
 Recall the “Von
Neumann model”:
• A Memory stores
both data and
program instructions
(both binary!)
• The CPU fetches,
decodes, and
executes program
instructions
sequentially
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Introduction
CPU Basics and Organization (2/5)
 The CPU components can be divided into two
main parts:
• The datapath: It groups the arithmetic-logic unit
(arithmetic and logical operations), registers
(storage units) and data buses (moving data from
place to place).
• The control unit: It is responsible for sequencing
operations and making sure the correct data is
where it needs to be at the correct time.
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Introduction
CPU Basics and Organization (3/5)
 Registers
• Registers are places to store a wide variety of data
- Numerical data, Addresses, Control information, …
• “General Purpose registers” are the registers
available to the programmer.
• “Special Purpose” registers are those that always
stores the same type of data
- Examples: Index registers, status registers, etc.
• Recall that registers can be implemented using D
Flip-flops!
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Introduction
CPU Basics and Organization (4/5)
 Registers
• Registers are located on the processor so
information can be accessed very quickly
• The control unit directly accesses data inside the
registers
• Most computers have registers of a certain size
(16, 32 or 64 bits)
- The size of registers fixes the “word size”
- Data processing on a computer is usually done on
these “words” (fixed size data) stocked inside the CPU
registers
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Introduction
CPU Basics and Organization (5/5)
 The arithmetic Logic Unit – ALU
• The ALU carries out logical and arithmetic
operations as directed by the control unit.
 The Control Unit
• The control unit is the “policeman” or “traffic
manager” of the CPU.
• It fetches and decodes sequentially the
instructions stocked in the main memory.
• It also monitors the execution of these
instructions and the transfer of all information.
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Lecture Overview
 Introduction
•
•
•
•
•
•




CPU Basics and Organization
The Bus
Clocks
The Input/Output Subsystem
Memory Organization and Addressing
Interrupts
Instruction processing
A simple program
A discussion on assemblers
Extending our ISA
AOU – Fall 2012
9
Introduction
The Bus (1/5)
 The CPU communicates with the other
components via a Bus.
 A Bus is a set of wires that simultaneously
convey a single bit along each line (parallel
movement).
 A Bus connects multiple subsystems within the
system
 A Bus can be “Point-to-Point” or “Common
Pathway” (also referred to as “multipoint bus”)
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Introduction
The Bus (2/5)
 A point-to-point bus
connects two specific
components
 A multipoint bus is shared by several devices
•
Bus protocols are used to manage the bus access by
these devices
Multipoint Bus
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Introduction
The Bus (3/5)
 A typical bus consists of three main components
• Data lines: are dedicated to moving data (the actual
information that must be moved).
• Control lines: indicate which device has permission to
use the bus and for what purpose (reading or writing
from memory or from an I/O device, …)
• Address lines: indicate the location (in memory, for
example) that the data should be either read from or
written to.
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Introduction
The Bus (4/5)
 Power lines are also required to provide the
electrical power necessary
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Introduction
The Bus (5/5)
 Buses have also been divided into different
types
• Examples:
- Processor-memory buses are short, high-speed buses
that are closely matched to the memory system on the
machine to maximize the bandwidth (data transfer).
- I/O buses are typically longer than processor-memory
buses and allow for many types of devices with varying
bandwidths
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Lecture Overview
 Introduction
•
•
•
•
•
•




CPU Basics and Organization
The Bus
Clocks
The Input/Output Subsystem
Memory Organization and Addressing
Interrupts
Instruction processing
A simple program
A discussion on assemblers
Extending our ISA
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Introduction
Clocks (1/5)
 Every computer contains at least one clock
that synchronizes the activities of its
components.
 The CPU requires a fixed number of clock ticks
to execute each instruction
• Instruction performance is often measured in
clock cycles instead of seconds
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Introduction
Clocks (2/5)
 The clock frequency, measured in megahertz
or gigahertz, determines the speed with
which all operations are carried out.
 Clock cycle time is the reciprocal of clock
frequency: T= 1/F
• Example: An 800 MHz clock has a cycle time of
1/(800x 106) seconds = 1.25 ns.
• Example 2: If a machine has a 2ns cycle time,
then it is a 500MHz machine.
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Introduction
Clocks (3/5)
 It seems reasonable to assume that if we
speed up the clock, the machine will run
faster?
• Well yes, BUT:
- Suppose we want to transfer data from a register
(output) to another (input)
- The data is transferred electrically inside the bus
- If the clock cycle is less than the “propagation delay”
between the registers we can end up with some values
not reaching the destination register (before the next
clock tick)!
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Introduction
Clocks (4/5)
 What if we “shorten” the distance between
registers to shorten the propagation delay?
• We could do this by adding registers between the
output registers and the corresponding input
registers.
 But recall that registers cannot change values
until the clock ticks, so we have, in effect,
increased the number of clock cycles!!
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Introduction
Clocks (5/5)
 So, the time to execute an instruction
depends on both “The clock cycle time” and
“the number of clock cycles per instruction”
 The time needed to execute a whole program
is given by:
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Lecture Overview
 Introduction
•
•
•
•
•
•




CPU Basics and Organization
The Bus
Clocks
The Input/Output Subsystem
Memory Organization and Addressing
Interrupts
Instruction processing
A simple program
A discussion on assemblers
Extending our ISA
AOU – Fall 2012
21
Introduction
The Input/Output Subsystem (1/1)
 A computer communicates with the outside
world through its input/output (I/O) subsystem.
 I/O devices connect to the CPU through various
interfaces.
 I/O can be memory-mapped, where the I/O
device behaves like main memory from the CPU’s
point of view.
 Or I/O can be instruction-based, where the CPU
has a specialized I/O instruction set.
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Introduction
Memory Organization and Addressing (1/9)
 A Computer memory is be seen as a matrix of
bits: a linear array of addressable storage cells
that are similar to registers.
 Each row has a length typically equivalent to
the word size of the machine.
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Introduction
Memory Organization and Addressing (2/9)
 Two types of memories are available:
• Byte addressable: Each byte has its own address
(each memory row contains 8 bits only)
• Word addressable: Each word has a unique
address (each memory row contains one word
that can be lager than 8 bits).
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Introduction
Memory Organization and Addressing (3/9)
 What if the word size is larger than a single
byte but the system still employ a byteaddressable architecture?
• Byte addressable: Still each byte has its own
address!
• When accessing a word (that uses multiple bytes),
the byte with the lowest address determines the
address of the entire word.
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Introduction
Memory Organization and Addressing (4/9)
 Now how many addresses do we have in a given
memory? And how many address bits?
 To answer this question we should be aware of:
• The type of addressing?
- word addressable or byte addressable
• The word size?
- Examples: 8, 16, 32, 64 bits?
• The storage capacity of the memory?
- Memory is often referred to using the notation L x W
(length x Width)
- Example: 4M x 16 means the memory is 4M long (number
of words) and it is 16 bits wide (word size)
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Introduction
Memory Organization and Addressing (5/9)
 Example 1: How a 4M x 16 word addressable
memory is organized?
• 16 bits is the word size.
• 4M means that we have 4 x 220 = 22 x 220 = 222
different words.
• These 222 words are numbered from 0 to 222 -1,
each number represents the address of only one
word.
• So each address is represented with at least 22
bits
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Introduction
Memory Organization and Addressing (6/9)
Example 1 (Cont.):
Moves on
address bus
Physical memory
Addresses in decimal
Addresses in binary
(22 bits)
Memory words (16
bits of DATA)
0
00000…0000000000
1001111100101011
1
00000…0000000001
1111111101111111
2
00000…0000000010
XXXXXXXXXXXXXXX
3
00000…0000000011
11011010110110011
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
222 – 2 = 4194302
11111…1111111110
XXXXXXXXXXXXXXXX
222 – 1 = 4194303
11111…1111111111
00000001000100111
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Introduction
Memory Organization and Addressing (7/9)
 Example 2: How many bits would you need to
address a 2M × 32 memory if:
a) The memory is byte-addressable?
b) The memory is word-addressable?
 Solution:
a) There are 2M × 4 bytes which equals 2 * 220* 22
bytes = 223 bytes, so 23 bits are needed for an
address
b) There are 2M words which equals 2 × 220 words =
221 words, so 21 bits are required for an address
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Introduction
Memory Organization and Addressing (8/9)
 Usually, computers’ physical Memory (RAM) is
not made from a single high capacity chip, but
a group of lower capacities chips.
 Access is more efficient when memory is
organized into banks of chips with the
addresses interleaved across the chips
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Introduction
Memory Organization and Addressing (9/9)
Example: How to build a 32Kx16 word addressable
RAM memory with only 2Kx8 RAM chips?
Solution:
To create the 32K words, we
need 16x2K words.
A 32Kx16 word addressable
RAM memory can be created
with 32 different 2Kx8 RAM
chips: We could connect 16
rows and 2 columns of chips
together
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Introduction
Interrupts (1/1)
 The normal execution of a program is altered when
an event of higher-priority occurs. The CPU is alerted
to such an event through an interrupt.
 Interrupts can be triggered by I/O requests,
arithmetic errors (such as division by zero), or when
an invalid instruction is encountered.
 Each interrupt is associated with a procedure that
directs the actions of the CPU when an interrupt
occurs.
• Non-maskable interrupts are high-priority interrupts that
cannot be ignored.
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Lecture Overview
 Introduction
 MARIE
•
•
•
•
•




Introduction
The Architecture
Registers and Buses
The Instruction Set Architecture
Register Transfer Notation
Instruction processing
A simple program
A discussion on assemblers
Extending our ISA
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MARIE
MARIE – Introduction (1/1)
 We are now familiar with computer components
but how these are connected together? How
these work together?
 Leonardo Da Vinci once said:
“When you wish to produce a result by means of an
instrument, do not allow yourself to complicate it”
 In this part we will use a MARIE, A Machine
Architecture that is Really Intuitive and Easy.
 MARIE will help us to understand how computer
functions (even the more complex computers)
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MARIE
The Architecture (1/1)
 The MARIE architecture has the following
characteristics:
• Binary, two's complement data representation.
• Stored program, fixed word length data and
instructions.
• 4K x 16 word-addressable main memory.
• 16-bit instructions: 4 bits for the opcode, 12 bits for
the address.
• A 16-bit arithmetic logic unit (ALU).
• Seven registers for control and data movement.
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MARIE
Registers and Buses (1/5)
 MARIE’s seven registers are:
• AC: Accumulator, a 16-bit register that holds a
conditional operator (e.g., "less than") or one
operand of a two-operand instruction.
• MAR: Memory address register, a 12-bit register that
holds the memory address of an instruction or an
operand of an instruction.
• MBR: Memory buffer register, a 16-bit register that
holds the data after its retrieval from, or before its
placement in memory.
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MARIE
Registers and Buses (2/5)
 MARIE’s seven registers are:
• PC: Program counter, a 12-bit register that holds the
address of the next program instruction to be
executed.
• IR: Instruction register, a 16-bit register that holds an
instruction immediately preceding its execution.
• InREG: Input register, an 8-bit register that holds data
read from an input device.
• OutREG: Output register, an 8-bit register that holds
data that is ready for the output device.
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MARIE
Registers and Buses (3/5)
 The MARIE architecture is shown in the figure
below:
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MARIE
Registers and Buses (4/5)
 MARIE cannot transfer data or instructions into
or out of registers without a bus.
 In MARIE, we assume a common bus scheme
• Each device on the bus is identified by a unique
number.
• If the device is required to use the common bus, Its
number is set on the control lines.
 Some direct pathways (without using the
common bus) are also available to speed up
execution
• MAR – Memory ; AC – ALU ; AC – MBR ; MBR – ALU.
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MARIE
Registers and Buses (5/5)
 The Data path in MARIE
is shown in this figure
• Note that a data word
(that is an instruction) in
the main memory travels
a relatively long path
before achieving the IR!
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Lecture Overview
 Introduction
 MARIE
•
•
•
•
•




Introduction
The Architecture
Registers and Buses
The Instruction Set Architecture
Register Transfer Notation
Instruction processing
A simple program
A discussion on assemblers
Extending our ISA
AOU – Fall 2012
41
MARIE
The Instruction Set Architecture (1/7)
 MARIE has a very simple, yet powerful,
instruction set.
 The Instruction Set Architecture (ISA) specifies
the format of its instructions and the primitive
operations that the machine can perform.
 The ISA is an interface between a computer’s
hardware and its software.
 Some ISAs include hundreds of different
instructions for processing data and controlling
program execution.
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MARIE
The Instruction Set Architecture (2/7)
 For MARIE, each instruction consists of 16 bits
 These bits are organized as follows:
• Opcode: 4 bits (bits 12 to 15), specifies the
instruction to be executed (which allows for a
total of 24=16 instructions, but only 13 are used)
• Address: 12-bits (bits 0 to 11), forms an address.
An instruction word
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MARIE
The Instruction Set Architecture (3/7)
 The fundamental MARIE instructions are:
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MARIE
The Instruction Set Architecture (4/7)
 Example: Consider the following binary instruction:
0001000000000011. What is the job of this
instruction?
 Solution:
• The first four MSB forms the opcode “0001”. It
corresponds to a LOAD instruction.
• The remaining 12 bits indicate the address of the value we
are loading, which is address 3 in main memory.
• This instruction causes the data value found in main
memory, address 3, to be copied into the AC
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MARIE
The Instruction Set Architecture (5/7)
 One important instruction is “SKIPCOND”
• When the Skipcond instruction is executed, the value
stored in the AC must be inspected.
• The next instruction is skipped (resp. not skipped), if
the condition tested is True (resp. False).
• Bits 11 and 10 (say b11b10) in the AC specify the
condition to be tested, if:
- b11b10 = 00: The CPU tests if AC < 0
- b11b10 = 01: The CPU tests if AC = 0
- b11b10 = 10: The CPU tests if AC > 0
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MARIE
The Instruction Set Architecture (6/7)
 Example: Consider the following binary
instruction: 1000100000000000. What is the
job of this instruction?
 Solution:
• The opcode “1000” corresponds to a “skipcond”
• b11b10 = 10, so the instructions’ job is to skip the
next instruction if AC > 0.
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MARIE
The Instruction Set Architecture (7/7)
 In general we use:
• SKIPCOND 000 which means skip the next
instruction if the AC <0.
• SKIPCOND 400 which means skip the next
instruction if the AC =0.
• SKIPCOND 800 which means skip the next
instruction if the AC >0.
 Note that 000, 400 and 800 are in base 16,
They are equivalent to 12bits (Address part)!
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Lecture Overview
 Introduction
 MARIE
•
•
•
•
•




Introduction
The Architecture
Registers and Buses
The Instruction Set Architecture
Register Transfer Notation
Instruction processing
A simple program
A discussion on assemblers
Extending our ISA
AOU – Fall 2012
49
MARIE
Register Transfer Notation (1/7)
 MARIE instruction appears to be very
simplistic
 Actually, at the component level, each
instruction involves multiple operations called
“microoperations”
 Register Transfer Language (RTL), or Register
Transfer Notation (RTN) specifies the exact
sequence of microoperations that are carried
out by an instruction.
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MARIE
Register Transfer Notation (2/7)
 In the MARIE RTL we will use the following :
• M[X]: to indicate the actual data value stored in
memory location X
• ←: to indicate the transfer of bytes to a register
or memory location
 In the following few slides we will present the
RTL for each of the instructions in the ISA for
MARIE
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MARIE
Register Transfer Notation (3/7)
 Load X
(loads the contents of memory location X into the AC)
MAR← X
Place the address X in MAR;
MBR← M[MAR]
The data M[MAR] at location address MAR
is moved into the MBR;
AC← MBR
The content of MBR is placed in the AC.
 Store X (stores the contents of AC into the memory location X)
MAR← X
MBR← AC
M[MAR]← MBR
Place the address X in MAR;
Place the content of AC in MBR
Place the content of MBR in the memory
location MAR (M[MAR] is replaced by MBR)
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MARIE
Register Transfer Notation (4/7)
 Add X
(The data value stored at address X is added to the AC).
MAR← X
MBR← M[MAR]
Place the address X in MAR;
AC← AC + MBR
Place the sum AC + MBR in AC
 Subt X
Place the data M[MAR] at location address
MAR in MBR;
(The data value stored at address X is subtracted from AC).
MAR← X
MBR← M[MAR]
Place the address X in MAR;
AC← AC - MBR
Place AC - MBR in AC
Place the data M[MAR] at location address
MAR in MBR;
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MARIE
Register Transfer Notation (5/7)
 Input
(Inputs a value from the keyboard into AC)
AC← InREG
 Output
(Output the value in AC to the display)
OutREG← AC
 Halt
Place the content of InREG (contains the input) in the
AC.
Place the content of AC (contains the output) in the
OutREG (to sent data to the display)
(Terminate the program)
no need for any RTL!
 Jump X
PC← X
(unconditional branch to the given address, X)
Load X into the PC
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MARIE
Register Transfer Notation (6/7)
 Skipcond
if IR[11–10] = 00 then
{if bits 10 and 11 in the IR are both 0}
if AC < 0 then PC ← PC+1
else if IR[11–10] = 01 then
{if bit 11 = 0 and bit 10 = 1}
if AC = 0 then PC ← PC + 1
else if IR[11–10] = 10 then
{if bit 11 = 1 and bit 10 = 0}
if AC > 0 then PC ← PC + 1
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MARIE
Register Transfer Notation (7/7)
 Important Notes
• Any instruction is firstly placed into the
instruction register IR where:
- IR[15-12] contains the opcode
- IR[11-0] contains the operand (address)
• In all the previous RTL, X can be replaced by
IR[11-0]!
• Example:
- The RTL for Jump X can be written as follows:
PC← IR[11-0]
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Lecture Overview
 Introduction
 MARIE
 Instruction processing
• The Fetch-Decode-Execute cycle
• Interrupts
 A simple program
 A discussion on assemblers
 Extending our ISA
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Instruction processing
The Fetch-Decode-Execute cycle (1/1)
 MARIE, like any
other computer
architecture, follow
the basic machine
cycle:
• the fetch, decode,
and execute cycle
Fetch
Decode
Execute
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Instruction processing
Interrupts (1/3)
 An important issue (that is not covered here for
MARIE) is interrupt handling
 Most computers provide a way of interrupting a
running program
 Examples of interrupts:
• A user break is issued (e.g., Ctrl+C)
• I/O is requested by the user or a program
• A critical error occurs
 Practically, when an interrupt occurs a special bit
in the “status register” or “flag register” of the
CPU is set.
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Instruction processing
Interrupts (2/3)
 The CPU checks this bit at the beginning of every
machine cycle
• If the bit is set, the CPU processes an interrupt as
follows:
1. Pause the execution of the current program
2. Run the interrupt’s appropriate routine
3. Continue the execution of the previously paused program
(after finishing the interrupt’s routine)
•
If the bit is not set, the CPU
performs a normal new
fetch, decode, execute cycle
of the program currently
being executed.
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Instruction processing
Interrupts (3/3)
 When the CPU finishes the interrupt’s
routine, it must return to the exact point at
which it was running in the original program.
 Before the CPU switches to the interrupt
service routine, it must save:
• The contents of the PC
• The contents of all other registers in the CPU
• Any status conditions that exist for the original
program.
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Lecture Overview






Introduction
MARIE
Instruction processing
A simple program
A discussion on assemblers
Extending our ISA
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A Simple program
A simple program (1/2)
 The figure below shows a program written in
assembly language for MARIE
 What does this program do?
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A Simple program
A simple program (2/2)
 This program simply adds to numbers and stores
the result in the main memory.
• It loads the value stored at the location address 10416
into AC (the value is 002316 = 3510)
• It adds this value to the value stored at the location
address 10516 (the value is FFE916 = (-23)10)
• Stores the sum into the location address 10616.
- So what will be stored in the location address 10616?
 Now let us discover what happens during each
“Fetch, decode, execute” cycle.
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Lecture Overview






Introduction
MARIE
Instruction processing
A simple program
A discussion on assemblers
Extending our ISA
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A discussion on Assemblers
What do Assemblers do (1/4)
 Assembly language can be understood by the programmer
but not the computer!
 Assembly language must be converted into Machine Codes
(binary codes) before being executed or even stored in the
main memory.
 An Assembler is used to translate assembly language into
machine code
• It reads a source file (assembly program) and convert it to an
object file (Machine code)
 Assembler VS Compiler
• An assembler translates each mnemonic instruction (written in
assembly) to exactly one machine code.
• With compilers, this is not usually the case
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A discussion on Assemblers
What do Assemblers do (2/4)
 Going back to our simple program, what
really happens inside the CPU during each
fetch, decode, execute cycle?
• Load 104:
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A discussion on Assemblers
What do Assemblers do (3/4)
• Add 105:
• Store 106:
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A discussion on Assemblers
What do Assemblers do (4/4)
 An assembler directive is an instruction that
is not supposed to be translated into machine
code
• Example: base 16 is the
default base when writing
assembly program for MARIE,
to specify the used base we
can use “constant directives”
such as DEC (decimal) or HEX
(Hexadecimal)
 In assembly language we can also use labels
in order to clarify the program
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Lecture Overview
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Introduction
MARIE
Instruction processing
A simple program
A discussion on assemblers
Extending our ISA
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Extending our instruction set
Extending our instruction set (1/5)
 For MARIE, we have seen only 9 instructions
while we have 4 bits, so we can have 16
different instructions.
 We will now extend our ISA by adding 4 new
instructions: JnS, Clear, AddI and JumpI
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Extending our instruction set
Extending our instruction set (2/5)
 JnS: Jump-and-Store instruction
• Allows us to store a pointer and then proceeds to set
the PC to a different instruction
• This enables us to call procedures and other
subroutines, and then return to the calling point in
our code once the subroutine has finished.
 Clear:
• This instruction moves all zeros into the accumulator.
• This saves the machine cycles that would otherwise
be expended in loading a 0 operand from memory.
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Extending our instruction set
Extending our instruction set (3/5)
 The RTL for JnS and Clear are shown in the
table below
JnS RTL
Clear RTL
MBR ← PC
MAR ← X
M[MAR] ← MBR
MBR ← X
AC ← 1
AC ← AC + MBR
PC ← AC
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AC ← 0
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Extending our instruction set
Extending our instruction set (4/5)
 So far, all of the MARIE instructions that we have
discussed use a direct addressing mode.
• This means that the address (not the value!) of the
operand is explicitly stated in the instruction.
 It is often useful to employ a indirect addressing
• The address of the address of the operand is given in
the instruction.
• This means that the content of the given address is
the address of the needed value.
• If you have ever used pointers in a program, you are
already familiar with indirect addressing.
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Extending our instruction set
Extending our instruction set (5/5)
 JumpI and AddI use indirect addressing
 Their RTL are shown in the table below
 What are the differences between JumpI X
and Jump X? AddI X and add X?
JumpI RTL
AddI RTL
MAR ← X
MBR ← M[MAR]
PC ← MBR
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MAR ← X
MBR ← M[MAR]
MAR ← MBR
MBR ← M[MAR]
AC ← AC + MBR
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An Exercise
FOR NEXT LECTURE (1/1)
 Exercise:
1. Write a program that calculates 2X + Y - Z where
X, Y, Z are three different numbers in three
different memory locations. Store the result in
the main memory and display it.
2. Implement your code in MARIE simulator.
3. Check if you have errors.
4. Correct your errors and run your program.
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End of lecture 4
Try to solve all exercises related to lecture 4
Download MARIE Simulator
Use the simulator to write and run your own
assembly programs!