Download Wafer-Level Packaging and Wafer-Scale Assembly

Wafer-Level Packaging
and Wafer-Scale Assembly
Technologies
May 17, 2010
CS MANTECH Workshop 6
Portland OR
Patty Chang-Chien
Northrop Grumman Aerospace Systems
Acknowledgement
• Multi-center effort at NGAS: Microelectronics, RF Product Center,
Manufacturing, Product Engineering, Materials, Antenna Product
• Kelly Hennig, Xiang Zeng, David Eaves, Phil Hon, Peter Chou, Gerry Mei,
Roger Tsai, David Farkas, John Chen, Keang Kho, Mike Battung, Yun
Chung, Pei-Lan Hsu, Jeff Yang, Wendy Lee, Matt Nishimoto, Tony Long,
Greg Rowan, Sean Shih, Dah-Weih Duan, Jose Padilla, Pin-Pin Huang,
Minhdao Truong, Richard To, K.K. Loi, Hui Ma, Jeremy Ou-Yang, Craig
Geiger, Gershon Akerling, Chi Cheung, Sujane Wang, Jane Lee, Danny
Li, Peter Nam, Peter Ngo, Martin IIyama, Ging Wang, Tom Chung, Gary
Gurling, Randy Duprey, Cesar Romo, Ben Heying, Randy Sandhu, Ben
Poust, Matt Parlee, Denise Leung, David Eng, Eric Kaneshiro, Rich Kono,
Jansen Uyeda, Mike Barsky, Jennifer Gan, Ke Luo, Fred Dai, Edna
Yamada, Mike Wojtowicz, Rich Lai, Augusto Gutierrez, Aaron Oki and
many more!
2
Agenda
• Overview
– Technology description
– Benefits
• 2-Layer WLP/WSA
– Process description
– Examples
• Interconnects & Transitions
• Package Performance
• Multi-Layer WLP/WSA
– Process description
– Examples
• Higher Order Integration
3
What is Wafer-Level-Packaging?
Wafer-Level Packaging (WLP)
AKA: Micro Packaging
AKA: Wafer-Scale Assemlby
(WSA)
State-of-the-art
MMIC Wafer
3-D Wafer Scale
Assembled IC
•
•
Add inter-cavity interconnects and cavity ring
Stack and bond multiple wafers, then dice
•
•
Forms a hermetically packaged 3-D integrated circuit
Enables integration of different MMIC technologies
WLP provides low cost, high volume, hermetic packaging
4
Advanced Capabilities for Next-Generation Systems
• Next-generation system needs performance superiority & affordability
• WLP
performance superiority
– Advanced integration
• best semiconductor technology for the function
– Ultra-compact, light weight packaging
• size & weight savings
– High functional density & low loss interconnects
• Superior circuit performance
– Hermetic MMIC packaging
• Enhanced circuit reliability
• WLP
Military Systems
Affordability
– Batch fabrication processes
• Low cost, high volume
– Fully compatible with NGAS MMIC production processes
• Existing & proven MMIC technologies
• Next-generation MMIC technologies
– Reduce higher order assembly cost, relax module
assembly requirement
5
Large Aperture
Phased Arrays
Satellite Comm.
Restricted
WLP Benefits
•
Heterogeneous
Integration using WLP
Superiority
– Hermetic compact MMIC packaging
– Performance enabler
• High functional density
• Superior circuit performance
• Affordability
Combine multiple MMIC wafers
by wafer bonding technology
– Batch fabrication processes, low cost, high volume
– Reduce higher order assembly cost, relax module assembly requirement
Integrated
Microwave
Assembly (IMA)
Wafer-LevelPackage (WLP)
Size reduction
1
1,000X
Weight reduction
1
1,000X
Cost reduction
1
10-100X
Tri-layer WLP TR Module
X-band operation
Mass: <15mg
Size: 2.5mm x 2mm x 0.46mm
WLP content: 3 bit PS, LNA, PA
WLP offers superiority in performance and affordability in cost
6
Integrated Microwave Assembly Packaging
GaAs
InP
IMA
7
GaN
CMOS
Wafer-Level Integration Benefits
•
Hermetic
•
Ultra-light weight, ultra-compact
•
Low cost, high volume
•
Performance enhancement
IMAs
Weight: g to >1000g
Size: cm x cm x cm
Assembly: serial, manual
Package near
a thumb tack
Wafer-Level Integrated Package
Weight: < 50 mg
Size: mm x mm x mm
Assembly: mass parallel, wafer scale
8
Integration Using Wafer-Level Packaging
• WLP is assembled using a low temperature wafer bonding process
• WLP technology is fully compatible with NGAS MMIC production
processes
a. Diagram and photograph of WLP LNA
Bonding
Ring
(wafer 1)
Through
Via
Low-Noise
Circuit with
Wafer Bonding Ring
Amplifier
Wafer
Bonding
Circuit
(low-noise amplifier)
Bonding
Ring
(wafer 2)
Bonding
Ring
Low
temperature wafer bonding process is
20
key to MMIC compatible, robust WLP
b. Measured data from WLP LNA circuits
10
)
9
2-LAYER WLP
10
2-Layer WLP
• Wafers are individually processed prior to bonding
– No changes to standard MMIC processes
• ICIC = Intra-Cavity InterConnections
2-layer Bonding Process Flow
ICIC
• BICIC = Backside ICIC
Wafer 2
Wafer 1
2-layer Bonding Process Flow
BICIC
Flip & align
ICIC (Front side)
BICIC (backside)
Bonding Layer
Wafer Bonding
2-Layer WLP is constructed by
bonding 2 individually processed wafers
11
Bonded pair
WLP Demonstrations
• WLP is fully compatible with NGAS’s MMIC production processes
Frequency bands w/
• X-band
• Ku-band
• V-band
Different circuit types
• LNAs
• Oscillators
• Shift registers
WLP
Ka-band
Q-band
W-band
w/ WLP
PAs
Phase shifters
Switches
Substrate combinations w/ WLP
• GaAs + GaAs
• InP + GaAs
• InP + InP
• Quartz + Quartz
• Si + InP
• Glass + Glass
• GaAs + Duroid
• GaAs + InP + GaAs
• GaAs + InP + InP
• SiC + SiC
• Multiple GaAs integrations
• Multiple InP integrations
Different compound-semiconductor technologies w/ WLP
InP HEMTs
InP HBTs
ABCS HEMT
GaAs HEMTs
MEMS switches
GaAs HBTs
Passives
GaAs Schottky diodes
GaN HEMTs
InP diodes
NGAS has extensive experience in heterogeneous integration using WLP
12
Examples of Packaged MMICs
Ku Band LNA, WLP GaAs HEMT circuit
Ku Band PA, WLP GaAs HEMT circuit
25
30
20
25
S21 (dB)
S21 (dB)
20
15
10
15
10
5
5
0
0
0
5
10
15
20
15
20
25
W-Band PA, WLP GaAs HEMT circuit
WLP
Q-Band
(IRFFE)
Q-Band
LNA,
WLPLNA
GaAs
HEMT Circuit
16
20
14
10
12
S21 (dB)
S21 (dB)
10
Frequency (GHz)
Frequency (GHz)
0
LNA
-10
-20
10
8
6
4
Bonding Ring
-30
2
0
-40
0
10
20
30
Frequency (GHz)
13
5
25
40
50
80
85
90
95
100
Frequency (GHz)
105
110
Wafer Level Packaging (WLP) MMICs Proven across the bands
4-bit PHSH
-Chip size: x=3.3mm, y=2.7mm
-TTL compatible
-avg RMS Amp Error=1.08dB
-avg RMS Phase Error=16.5º
2-Stage, self-biased LNA
-Chip size: x=3.3mm, y=2.7mm
-bias: 4V, 26 mA
-Gain > 26.5 dB at 16 GHz
2-Stage PA
-Chip size: x=3.3mm, y=2.7mm
-bias: 4V, 120 mA
-Gain > 19 dB at 16 GHz
KU
3-Stage, self-biased LNA
-Chip size: x=4.2mm, y=4.2mm
-bias: 4V, 45 mA
-Gain > 24 dB at 35 GHz
3-Stage, self-biased LNA
-Chip size: x=4.2mm, y=4.2mm
-bias: 4V, 60 mA
-Gain > 11.8 dB from 30-50 GHz
KA
Miniaturized WLP T/R modules for large arrays
14
Q
GaN WLP Technology
• Developed world’s first GaN wafer level package process for record
power density
• Demonstrated >99% GaN WLP interconnect yield
Passive
Cover Wafer
Active GaN
Wafer
Photo of GaN WLP MMIC
GaN WLP chip
GaN WLP TEG chip
15
W-Band WSA Oscillator
• W-Band oscillator with built-in on chip
resonant cavity
• 2-layer active MMIC integration:
– InP HEMT + GaAs HBT
Measured spectrum of Oscillator
1st and 2nd Half of
Resonant Cavity
Coupling Through Wafer
Slot
RF Transition
Active Device
Through Wafer RF Transition
(Backside Probe Location)
Photo of the integrated oscillator chip
Demonstrated 2-Layer WSA Oscillator
16
Comparison of WLP and non-WLP circuits
ALH 140
ALH140 vs. ALH140V3
1.4mm
ALH140_1
ALH140_2
ALH140_3
ALH140_4
ALH140_5
ALH140_6
ALH140_7
ALH140_8
ALH140_9
ALH140_10
ALH140_11
ALH140_12
ALH140_V3_1
ALH140_V3_2
ALH140_V3_3
ALH140_V3_4
ALH140_V3_5
ALH140_V3_6
ALH140_V3_7
ALH140_V3_8
ALH140_V3_9
ALH140_V3_10
ALH140_V3_11
ALH140_V3_12
18
16
14
12
ALH 140V3 (WLP)
S21 (dB)
2.5mm
10
1.9mm
8
: Conventional ALH140
(FIDR1/A-J103 1146A-031)
6
: ALH140V3 with WLP cover
(WLP5/1/P200-001)
4
2
0
30
31
32
33
34
35
36
37
38
39
Frequency (GHz)
3.2mm
RF performance similar for WLP and non-WLP circuits
17
40
2-LAYER INTEGRATED
WLP/WSA EXAMPLES
18
Heterogeneous Integration Example
• Integrated RF front end module with antenna
–
–
–
–
Amplifier (GaAs HEMT)
3 bit phase shifter (GaAs HEMT)
Interconnections (ICICs)
Antenna
WLP bottom side
WLP top side
(antenna)
Integrated RF Front-End Module
Sealing Ring
(Wafer 2)
Wafer 1
antenna
Wafer 2
Wafer
Bonding
Phase
shifter
19
ICIC
Sealing Ring
(Wafer 1)
Amplifier
Wafer 1
Ground Fence
Through wafer via
On-Wafer Measured Data
•WLP technology
- Wafer1=passive, 4-mil GaAs
- Wafer2=0.1um, 4-mil GaAs
•2-stage balanced Amplifier
•3-bit reflective phase shifter
Phase Shifter Phase States
20
400
S21
0
Phase (deg)
Magnitude (dB)
Amplifier S-Parameter
S11
-20
S22
-40
200
100
0
10
20
300
20
30
40
Frequency (GHz)
50
1
2
3 4 5 6
Phase States
7
8
WLP Linear Array Demonstration
Measured Beam Pattern
• Demonstrated fully functional front-end
modules with a linear 4-element array
-5
=0
-10
E-Field Magnitude (dB)
– GaAs HEMT + passive
– Amplifier + 3bit PS + antenna in an
integrated Q-Band WLP package
– Successful integration to BFN board
– Demonstrated electronic beam steering
0
-15
-20
-25
-30
=15
-35
Integrated RF front-end modules w/ antenna
-40
-60
-40
-20
0
(deg)
WLP bottom side
Beam Forming Network (board)
21
20
40
WLP top side
(antenna)
60
INTERCONNECTS &
TRANSITIONS
22
RF ICICs
•
RF ICIC 50 Ohm Coaxial Transition
•
Designed to provide minimal mismatch between 50 Ohm microstrip line (wafer
1) and 50 Ohm CPW line (wafer 2)
Measured Data from RF ICIC Structure
(2 RF ICIC transition + thru line)
0
-0.1
-0.2
S21 (dB)
-0.3
Wafer 2 – ICIC Coaxial transition to
CPW transmission line
-0.4
-0.5
(a)
-0.6
Wafer 1 – Microtransmission line to
ICIC Coaxial transition
-0.7
-0.8
(b)
-0.9
-1
0
5
10
Frequency (GHz)
15
Demonstrated Low Loss, RF ICICs
23
20
Low Loss RF Vias
• RF via transitions
RF Via Test Structure
– Low loss up to 50GHz
– <0.1dB insertion loss up to 30GHz
• DC interconnects
– > 99% yield
• Calibration structures
– To ensure accurate measurement
RF calibration and Test Structures
Measured Data
Simulation
Demonstrated Low Loss RF Vias for WLP devices
24
High Frequency RF Interconnects
Electro-Magnetic Simulation of Transition
• First-of-a-kind W-band WLP RF interconnect
— Insertion Loss < 0.2 dB
— Return Loss > 20 dB
— 20 dB isolation
Input
~0.2
mm
Output
Top Wafer
Measured Transition-Line-Transition Response
Bottom Wafer
Ground Vias
connecting top
and bottom
ground planes
Bottom Wafer
Back-to-Back Interconnect Cross Section
Demonstrated Low Loss, High Isolation
W-Band WLP Interconnects
25
Isolation Using Ground Fence
Isolation Fence
• Isolation fence can be built using 3D
interconnects within WSA
ICIC
• Demonstrated 30dB isolation improvement
in W-band using ground fence
• 3D WSA offers design flexibility and
performance improvement
Thru-Wafer Via
RF Transition Line
Simulated Isolation Fence Response
0
Isolation (dB)
Loss (dB)
Isolation
0
Isolation Loss (dB)
-10
Isolation (dB)
0
Measured Isolation Fence Response
0
-20
Blue: no via fence
Red: with via fence
-30
-40
No via fence
-10
-20
-20
DB(|S(2,1)|)
DF_MS22_ISO_0_1a
-30
Single via fence
DB(|S(2,1)|)
DF_MS22_ISO_1_1a
-40
-40
-50
-60
-60
-50
-70
-60
-60
91 91
92
93
94
95
Frequency
(GHz)
Frequency (GHz)
96
97
97
-80
-80
91
91
92
94
95
Frequency
(GHz)
Frequency (GHz)
93
RF Isolation Design For WSA MMIC
26
96
97
97
PACKAGE PERFORMANCE
27
Package Mechanical and Thermal Integrity
•
WLP chips Passed the many military standard tests:
– Vibration-Sine
• MIL-STD 883F, Method 2007.3, condition B
– Mechanical Shock (Pyroshock)
Mechanical Robustness
• MIL-STD 883F, Method 2002.4, condition B
– Die Shear
• MIL-STD 883F, method 2019.7
– Temperature Cycling
• MIL-STD 883F, Method 1010.8, condition B
• -55ºC to 125ºC, 50 cycles, MEMS
Thermal Robustness
• -55ºC to 85ºC, 300+ cycles, W-Band GaAs circuits
• -55ºC to 125ºC, 500 cycles, GaAs PA
– Hermeticity
• MIL-STD 883F, Method 1014.11
Seal Robustness
• He fine leak, condition A2, flexible
• Radioisotope fine leak, condition B
• Penetrate dye gross leak, condition D
•
Environmental test: 85C 85% humidity 7 days Ku band GaAs MMICs
WLP packages are hermetic, thermally and mechanically robust
28
Thermal Robustness
• 24 to 40 GHz GaAs HEMT LNA
• Thermal cycling, -55 C to 125 C
• 500+ cycles
Measured s21 response as function of thermal cycles
Photo of WLP GaAs LNA
20
15
10
9-R6C6M0
5
0
0
-5 1
-10
-15
-20
-25
11
-10
S11 (dB)
S21 (dB)
-5 1
11
21
31
21
29
31
41
Post_500 Cycles
-15
Post_300 Cycles
-20
Post_100 Cycles
-25
Post_10 Cycles
-30
Pre_Cycle
-35
-30
41
-40
Frequency (GHz)
Frequency
(GHz)
MULTI-LAYER WLP/WSA
30
Advanced Integration: Multiple Layer WLP
4-layer Bonding Process Flow
• Example: 4-layer construction
Bonded Pair 1
– Use bonded pair as starting units
Multiple Layer WSA Flow
Bonded Pair 1
Bonded Pair 2
or single wafer
Process Bonding
layer if necessary
(backside)
ICIC (Front side)
BICIC (backside)
Bonding Layer
Wafer Bonding
4-Layer Construction is Achieved By
Bonding 2 bonded WLP pairs
31
Bonded Pair 2
X-Band Tri-Layer Tx/Rx Modules
WLP Tx/Rx Module
Average mass: 12.9mg
Size: 2.5mm x 2mm x 0.46mm
ABCS HEMT LNA
Low Noise
Amplifier
ABCS HEMT
32
InP HBT PA & digital control
Power Amplifier
Shift Register
GaAs HEMT
h
Phase
Shifter
Sw
itc
h
InP HBT
Sw
itc
•Next-Generation Large Aperture
Array T/R Module
–Ultra light weight (<15 mg)
–Extremely compact (<5 mm2 )
•Transceiver Module Performance
–FOM > 10,000
–Reliability: MTTF >106 Hours
GaAs HEMT PS & Switches
Demonstrated X-Band Integrated T/R Module
Tri-Layer T/R Demo
• Tri-layer T/R module demonstration
– GaAs HEMT + InP HBT + InP HEMT
– Demonstrated excellent yield and T/R circuit performance
Measured NF (Rx) of the tri-layer WLP T/R module
33
CMOS + III-V Integration Demo
WLP 8-bit VAP
5-mil solder ball
8-bit shift register
8-bit CMOS
Shift Register
WLP 8-bit VAP
Measured Phase
ShifterMeasured
Data
Ideal
Input Digital CTRL Waveform
CLK
ENB
Data
Measured Angle (Deg)
225
180
135
Measured Angle (Deg)
225
Ideal
Measured
180
135
90
45
0
90
0
45
90
135
180
Set Angle (Deg)
45
Demonstrated heterogeneously integrated CMOS flip-chip to WLP MMICs
34
0
HIGHER ORDER ASSEMBLY
35
WLP Higher Order Integration Demonstrations
Fixture
Alumina
Organic Board
Assembly
•
Technologies integrated
Benefit
•
CMOS to III/V Integration
 SWaP reduction
•
Direct WLP to Board Attach
 SWaP, cost reduction
•
16-element Ku-band Rx Array
 Near term insertion
Techniques demonstrated •
8-element Ku-band Rx SubArray
 Design to
manufacturing
•
4-element Q-band Tx Array
 mmW array
implementation
–
–
–
–
•
Demonstrations
–
–
GaAs-GaAs
GaAs-InP
InP-InP
ABCS-InP-GaAs
Epoxy to Fixture/Board
Bump to Board
• Manual
• Auto assembly
Demonstrated WLP-to-Board Integration
36
Microbump: Chip-Board Integration
• Developed microbump technologies for WLP–
to-board attachment and integration
Cu stud microbump
Microbumps on backside of the package
Sn/Pb microbump array
Microbumps enable direct WLP-to-Board Integration
37
Direct Board Attach Using Microbumps
chip
board
Cu studs
X-ray result showing good board to chip interface
Excellent Chip-to-Board Microbump Interface
38
Example of Epoxy Attach and Ribbon Bonds
Implementation
Ku Band subarray board with WLP chips
Integrated Subarray
Antenna Board
5 WLP MMIC fixture
for environmental
testing
Normalized Amplitude
Measured Far Field Pattern
-45.0
-25.0
0.0
25.0
Azimuth ( )
WLPs are compatible with epoxy attachment
39
45.0
WLP on Interposer Boards on PWB
Front Side: WLP on Interposer
Back Side (Solder Ball)
WLP on Interposer
WLP Interposer board
attachment to PWB
40
Higher Order Integration Using WLP/WSA
• Demonstrated thermal cycling
robustness of WLP-board
assembly with underfill
• Successfully demonstrated dual
side WLP chip-to-board
attachment
• >200 cycles
• from -40C to 100C
• Pass without failure
WLP chips
Dual-Sided
Assembly
5mil Solder Balls
Dual sided board
WLP chips
2-layer
WLP chip
WLP cavity
5mil solder
balls
underfill
PWB
Chips on the front side of PWB after
backside assembly
41
Chips on the backside of PWB
Summary
• WLP technology offers performance superiority and affordability for
next-generation systems
• WLP offers significant size, weight and cost savings for future
systems
• Demonstrated multiple advanced technology integration with WLP
• Verified robustness of WLP packaging by MIL-STD tests
• Demonstrated WLP integrated MMICs & modules across the bands
• NGAS is committed to mature and improve wafer-scale integration
technology for system insertion
42
43