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CREST R&D GRANT APPLICATION FORM REV3.0
Reference No:
CREST RESEARCH APPLICATION FORM
One (1) hardcopy and softcopy (email : [email protected]) of this form must be submitted to the
Collaborative Research in Engineering, Science & Technology (CREST) Center, Research & Development
Division, Block C, Ground Floor, SAINS@USM, No. 10 Persiaran Bukit Jambul, 11900 Bayan Lepas, Penang,
Malaysia. (http://www.mycrest.com.my)
[Incomplete Applications will not be reviewed]
DETAILS OF RESEARCHER
Name of Project Leader:
Dr. Fakhrul Zaman Rokhani
Position:
Senior Lecturer
Office Telephone No:
+603-8946-6434 / +6019-775-7007
E-mail Address:
[email protected]
NAME OF ORGANISATION
Universiti Putra Malaysia
LOCATION OF RESEARCH :
Faculty of Engineering,
University Putra Malaysia,
43400 UPM Serdang
Selangor, Malaysia
CREST R&D GRANT APPLICATION FORM REV3.0
COMPANY INFORMATION
Company Name:
Silterra Malaysia Sdn. Bhd.
Address:
Lot 8, Phase II
Kulim Hi-Tech Park
09000 Kulim
Kedah Darul Aman,
Malaysia
Company No:
368948-D
Brief description of Company:
Silterra is a project of strategic national interest to promote front-end semiconductor manufacturing and a
catalyst for high technology investments in Malaysia. It was founded in November 1995 as Wafer Technology
Malaysia Sdn Bhd and was renamed as Silterra Malaysia Sdn Bhd in December 1999. Since its inception,
Silterra has served many top-tier global fabless design and product companies covering the consumer
electronics, communications & computing, and mobile device market segments.
Silterra provides complete design solutions for customers to create leading-edge products, optimized for its highyielding manufacturing processes, through strategic partnerships with industry-leading Intellectual Property (IP)
design library providers, Design Services and Electronic Design Automation (EDA) suppliers. Silterra also offers
comprehensive in-house Failure Analysis (FA) services to high-tech companies and universities, performing
detailed construction and failure analysis of nano-scale structures.
Silterra offers CMOS design and a broad range of fabrication processes for Integrated Chips (IC) in Advanced
Logic, Mixed Signal & Radio Frequency and High Voltage applications.
Company’s role in the project:
1. To provide technical support in terms of the design of standard cells including layout design, impact of
variation investigation, circuit simulation, characterization and testchip design.
2. To provide manufacturing support in terms of Multi Project Wafer (MPW).
Note:
(1) If more than one company is involved, please provide information about the primary company and include
information on the other companies in attachments.
(2) Please attach a support letter signed by Company’s top management.
CREST R&D GRANT APPLICATION FORM REV3.0
ACADEMIA INFORMATION
University Name:
Universiti Putra Malaysia
Address:
Faculty of Engineering,
University Putra Malaysia,
43400 UPM Serdang
Selangor, Malaysia
Brief description of University:
UPM, a leading research university in Malaysia is located in Serdang, next to Malaysia’s administrative capital
city; Putrajaya. As a world renowned centre of learning and research, UPM has attracted students and staff from
all around the world making it a well-respected global entity. UPM is recognised by the independent government
assessments as one of Malaysia's leading research Universities. Founded in 1931 as the School of Agriculture,
the University today combines impressive modern facilities and a dynamic approach to teaching and research
with its proud heritage of quality services and achievements.
VISION: To become a university of international repute.
MISSION: To make meaningful contributions towards wealth creation, nation building and universal human
advancement through the exploration and dissemination of knowledge.
Historically, UPM and Silterra has been working closely in the design of standard cell library on Silterra 130nm
process where UPM focus was on validating various design metrics of the standard cell library.
University’s role in the project:
1. To architect the standard cell library with energy-efficient optimization, to design circuits and layout of the
cells, to compile the standard cells into library, to design test chips and conduct investigation on the impact
of process variation to the standard cell library performance.
2. To ensure the project runs per schedule and each milestone is delivered.
Note:
(1) If more than one university is involved, please provide information about the primary university and include
information on the other universities in attachments.
(2) Please attach a support letter signed by University’s head of department / dean.
CREST R&D GRANT APPLICATION FORM REV3.0
PROPOSED RESEARCH TEAM MEMBERS:
Name
Organisation
Position
Highest
Academic
Qualification/
Designation
Email
1
Dr. Roslina
Mohd Sidek
Universiti Putra
Malaysia
Associate
Professor
PhD
roslina@e
ng.upm.ed
u.my
2
Dr. Shaiful
Jahari Hashim
Universiti Putra
Malaysia
Senior Lecturer
PhD
shaiful@e
ng.upm.ed
u.my
3
Dr. Noor Ain
Kamsani
Universiti Putra
Malaysia
Senior Lecturer
PhD
nkamsani
@eng.up
m.edu.my
4
Mr. Park Sang
Hyun
Silterra
Member of
Technical Staff
Degree
sanghyun
_park@silt
erra.com
5
Mr. Chan Chee
Kean
Silterra
Senior
Engineer 2
Master
cheekean
_chan@sil
terra.com
7
Mrs. Nur
Liyana Binti
Jasni
Silterra
Engineer
Degree
nur_liyana
1@silterra
.com
4
Dr. Subhash
Rustagi
Silterra
Deputy
Director
PhD
subhash_r
ustagi@sil
terra.com
Signature
CREST R&D GRANT APPLICATION FORM REV3.0
A
A(i)
RESEARCH INFORMATION
TITLE OF PROPOSED RESEARCH :
Standard Cell Library Design and Validation Under Variability Influence for Energy Efficient System-onChip Application
A(ii)
Research Area (Please tick ( √ ):
Industrial Cluster
√ Semiconductor
Solar
Optoelectronics
Industrial Electronics
Others
A(iii)
Duration of this research (Maximum 36 months):
Duration: ___36 months________
CREST R&D GRANT APPLICATION FORM REV3.0
B
Executive Summary of Research Proposal (maximum 300 words)
(Please include the background of research, literature reviews, objectives, research methodology and
expected outcomes from the research project)
The major challenge in designing next-generation System-on-Chip (SoC) has been shifted from absolute timing
to meeting timing without blowing out the power budget. Energy-efficiency has become the key differentiator in
many products especially in mobile devices. Efforts in designing energy-efficient SoC for green computing have
spurred at various design level to ensure the final chip is not a “dark silicon” design.
The fundamental element of the SoC’s digital block is the standard cells, generally occupying a large segment of
any SoC designs. Standard cell-based or Application Specific IC (ASIC) design are widely adopted in designing
multi-million transistors chip due to the fast turn-around time and highly scalable with design complexity.
Worldwide market for ASIC design was reported around US$37B in 2010 and projected for a 12% annual growth
up to 2016.
To date, no comprehensive optimization effort on such standard cell design for energy-efficient application is
reported. In this project, energy efficient CMOS standard cell library based on Silterra 90nm process will be
designed. Cross-layer optimization at the architecture, circuit, layout and process level is proposed to mitigate
both dynamic and static power. Special cells to support low power methodologies will be designed, circuits and
layout will be fine-tuned on the new Silterra 90nm low power process. Multiple test-chips will be designed making
use of the developed standard cell to validate the pre-silicon characterized data and the developed library is
industry-usage ready. To address test-chip resource issue in validating pre-silicon characterized data, novel
circuit architectures will be designed. The impact of sub-100nm process variation on the standard cell library will
be investigated at the simulation and process level and new variation model will be developed.
It is expected that a silicon validated, energy-efficient standard cell library compatible with commercial tool will be
developed and the impact of process variation on standard cells performance are comprehend. The developed
library is expected to boost the competency of local design houses and put Malaysia in the global SoC market
map.
CREST R&D GRANT APPLICATION FORM REV3.0
C
DETAILED PROPOSAL OF RESEARCH PROJECT:
(a) Research background including Problem statement and research methodology.
Energy-efficiency metric has become the key differentiator in many System-on-Chip (SoC) products especially in
mobile computing devices and servers. With the green computing and integration of more chips, the chip design
paradigm has shifted from absolute timing optimization to meeting timing without blowing out the power budget.
This new design optimization is utmost important to ensure that the chip can run at the targeted operating
frequency with acceptable power density. High chip’s power density leads to frequent battery charging for mobile
devices and cooling and reliability issues for all types of devices. Recently, there has been an alarming report on
“dark silicon” phenomena in which the percentage of a chip that can be actively powered on within a chip's power
budget is dropping exponentially [1]. This reality will force designers to ensure that, at any point in time, large
fractions of their chips are effectively dark or dim – either idle or significantly underclocked which does not
embrace the best out of Moore’s law scaling.
SoC is the core of most embedded computing and electronic equipment, eg: smartphone, tablet, media players,
computer, aerospace, medical electronics and etc. Current global SoC market value is at USD85.9B and is
expected to grow to USD212 bilion in 2016, commanding more than 85% control of global IC market [2]. The
fundamental element of the SoC’s digital block is the standard cells, generally occupying a large segment (in the
order of 70-80%) of any SoC designs. Thus, optimizing the standard cell libraries to achieve very low power
libraries will give significant impact to the final energy efficiency of any SoC design.
The standard cells are typically provided in the form of a library having many choices for cell types, cell sizes,
delays, power and drive-strengths. The library is formatted to be compatible with available Electronic Design
Automation (EDA) tools from well established EDA vendors such as Mentor Graphics, Synopsys and Cadence
among others. Worldwide market for standard cell-based design or Application Specific IC (ASIC) design was
reported around US$37B in 2010 and projected for a 12% annual growth up to 2016. From the business
perspective, high growth of ASIC market is largely contributed by the well structured standard cell library
networks initiative - Open Innovation Platform pioneered by TSMC [3]. Through this open platform, over more
than 40 standard cell suppliers based on TSMC Process Design Kit (PDK) provide the opportunity for TSMC’s
customers to choose the best cost-effective design solution for their product.
From the technical standpoint, standard cell-based design are widely adopted in designing multi-million
transistors SoC due to the fast turn-around time, highly scalable with increase design complexity and usually
guaranteed first time successful silicon implementation. With advanced technologies, the process characteristics
become more remarkably complex and process variations comes into play, thus to ensure manufacturability,
designers are restricted with large number of design rules [4]. This indicate increasing challenges in the layout
design employing the non-standard cell based design flow (i.e. analog design flow) for designing large blocks.
This can be seen as there is a clear trend of implementing analog blocks based on digital standard-cells, like the
all-digital phase locked loop (ADPLL) and all-digital analog-to-digital converter (ADC) [5], [6].
Energy-efficient standard cell library is a library of cells that consumes less energy and power compared to the
cells in the general standard cell library. Previous works in energy efficient standard cell library can be
categorized into 2 groups which are dynamic power and leakage power optimization. Under the dynamic power
optimization, approaches include track size optimization [7], cell drive strength optimization [8-10], transistor beta
ratio sizing [11, 12], selection of cells to be included in the library [10, 13], low-power library flip-flop registers [10,
14], low operating voltage standard cell design at sub-threshold voltage [15] and novel logic circuits [16]. Hybrid
techniques to mitigate dynamic power in standard cell include the optimization of cell drive strength and
transistor sizing [8-9], optimization at the circuit level, macro-block and layout level [14] and optimization of cell
drive strength, transistor sizing and low-power flip-flop [10]. Techniques in mitigating leakage power include
novel circuit structure [17] and multi-threshold voltage transistors application [18]. To the best of our knowledge,
there is no work on exploring cross-layer optimization between library architecture, circuit and layout optimization
for a particular low power process to achieve energy-efficient standard cell library, which is the focus of this
project.
Today's sophisticated standard cell libraries require simulation models that match the actual silicon performance
to avoid exposing ASIC customers to costly design iterations. For any library based approach, the complete
electrical characterization model of logic gates is required before applying them in the IC design flow. Such
characterization model shall be accurately performing under different design parameters, i.e. signal input slopes,
CREST R&D GRANT APPLICATION FORM REV3.0
output capacitive loads and design corners (temperature, power supply and process parameters variation). In
most cases, post-silicon library validation will be conducted on the standard cell library to assess the correlation
between the timing, power consumption and noise characterization model with the data from silicon and to check
the quality of the library working with EDA tool.
Two approaches have been proposed in the literature to conduct the library qualification. To assess the quality of
the standard cell library working with EDA tool, test chip comprised of medium size to large digital blocks
exercising as much library cells are designed using commercial synthesis and place-and-route tools. Quality of
results (QOR) of the designs is analyzed to understand the performance of the library at work with the
commercial tool. Second approach is to design the Test Element Group (TEG) chip, which is a special purpose
fabricated chip used to assess the correlation between library models and the silicon data in terms of the cell
function, timing, power and noise characterization. These works can be categorized into two groups, one
focusing on combinational logics [18-23] while the other focused on sequential cells including latch and flip-flop
[24-27]. Issues in designing the TEG chip includes the constraint resources in terms of input and output pins,
single point as opposed of library cell tables validation, pins validation for multi-input cells, parametric variations
and the presence of soft defect [28]. In this project, both approaches to assess the the correlation between
timing and power consumption of characterized model with the silicon data and the quality of the library working
with EDA tool will be conducted. In particular, new circuit structures for TEG circuits will be designed to address
design issues of resource constraints and validation pins for multi-input cells.
Process variability also has become increasingly problematic in device scaling. It causes circuit layout or
electrical parameters to vary from the designed values, and hence can lead to catastrophic or parametric yield
losses. The device process variability can be categorised into global and local variations. In global variation, the
physical parameter variations induced by manufacturing processes (i.e. inaccuracy of process parameters and
non-uniformity of the fabrication equipment) such as the oxide layer thickness, gate length and doping
concentration change gradually across the chip/wafer. Local variation, which is associated with the fluctuations
of physical or electrical parameters of transistors within a die, arises due to the physics of manufacturing
process. It can further be divided into systematic and random variations. Systematic variation is the component
of the physically varying parameters that follow a well understood behaviour and can be predicted or modelled
up-front. Examples of systematic variations are the optical proximity effect [29], layout mediated strain [30] and
the well proximity effect [31]. Random variations or also known as the intrinsic parameter fluctuations (IPF),
arises from the discreteness of charge and the granularity of matter. IPF can be further categorized into random
discrete dopant (RDD), line edge roughness (LER) and oxide thickness variation (OTV) [32-34]. They have
become prominent in extremely scaled devices as the physical device dimensions approach the atomic scale
affecting design, yield and pose difficulties in circuit simulation and verification for future technology nodes.
Variability in standard cells comes from the process and operating condition variations. Standard cell libraries for
integrated circuits are specified to meet operating standards across a range of defined variations [35]. Related
study on standard cell library variability include defining metrics for comparing variability among standard cells
[36], characterization methodology including statistical techniques and new circuits design to quantify variability
in combinational and sequential cells [35, 37-39] and design technique to increase the cell’s tolerant to variability
[40]. In this research, we will investigate the impact of process variation on the performance of the standard cell
library through both simulation and process-level approach and new variation model for standard cell
performance on Silterra 90nm low power process will be developed.
The aim of this research is to develop silicon validated, energy-efficient standard cell library which is highly
compatible with commercial synthesis, place and route tool. In particular, new cross-layer optimization from the
architecture, circuit, layout and process level will be explored to mitigate both dynamic and static power. Special
cells to support low power methodologies will be designed, circuits and layout will be fine-tuned on the new
Silterra 90nm low power process. In order to assess the correlation between pre-silicon characterized data with
the silicon data, TEG circuits based test-chips will be designed. Specifically, new circuit architectures for TEG
circuits will be designed to address design issues of resource constraints and pins validation for multi-input cells.
Medium to large size digital blocks will be designed using commercial synthesis and place and route tool to
qualify that the developed standard cell library is industry-usage ready. Investigation on the impact of Silterra
90nm process variation to the standard cell library will be conducted at the simulation level and process-level. At
process-level, variation will be deliberately introduce during fabrication and it is expected new variation model
illustrating the impact to standard cell performance will be developed.
It is expected that the developed standard cell library can boost up the competency of local design houses
through the offering of high-quality library at high-end process and put Malaysia in the global SoC market map.
CREST R&D GRANT APPLICATION FORM REV3.0
References
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12. Fisher, C., Blankenship, R., Jensen, J., Rossman, T., Svilich, K., “Optimization of standard cell libraries for
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Conference, 1996, pp.493-496, 1996.
13. Minh Duc, N. Sakurai, T., “Compact yet high-performance (CyHP) library for short time-to-market with new
technologies,”. Proceedings of the Asia and South Pacific Design Automation Conference, 2000 (ASP-DAC
2000), pp. 475-480, 2000.
14. Dragone, N., Guardiani, C., Zafalon, R., Meier, P., “An Innovative Methodology for the Design Automation of
Low Power Libraries,” Proc. Int. Workshop Power and Timing Models, Optimization and Simulation
(PATMOS), 1998.
15. Amarchinta, S., Kanitkar, H., Kudithipudi, D., “Robust and high performance subthreshold standard cell
design,” 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009 (MWSCAS '09),
pp.1183-1186, 2009.
16. Lotze, N., Manoli, Y., “A 62 mV 0.13um CMOS Standard-Cell-Based Design Technique Using SchmittTrigger Logic,” IEEE Journal of Solid-State Circuits, Vol. 47 , Issue. 1, pp.47-60, 2012.
17. Lakshmikanthan, P., Sahni, K., Nuñez, A., “Design of Ultra-Low Power Combinational Standard Library Cells
Using A Novel Leakage Reduction Methodology,” 2006 IEEE International SOC Conference, pp.93-94, 2006.
18. Lu, L.-Y., Chen, K.-Y, Wu, T.-Y, “High Performance and Low Leakage Design Using Cell Replacement and
Hybrid Vt Standard Cell Libraries,” Proceedings of the International Multiconference of Engineers and
Computer Scientists 2008, Vol. 1, 2008.
19. Agatstein, W., McFaul, K., Themins, P., “Validating an ASIC standard cell library,” Proceedings., Third
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20. Badam, U., “Development of a 5V digital cell library for use with the Peregrine semiconductor silicon-onsapphire (SOS) process,” MSc. Thesis, Oklahoma State University, 2007.
21. Jain, V., “Design of 5V digital standard cells and I/O libraries for military standard temperatures,” MSc.
Thesis, Oklahoma State University, 2008.
22. Lin, R.-B., Chou, I. S.-H., Tsai, C.-M., “Benchmark circuits improve the quality of a standard cell library,”
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23. Singh, A., Panwar, N., “On Silicon Timing Validation of Digital Logic Gates,” 25th International Conference
on Microelectronics, pp.424-427, 2006.
24. Nedovic, N., Walker, W. W., Oklobdzija, V. G., “A Test Circuit for Measurement of Clocked Storage Element
Characteristics,” IEEE Journal of Solid-State Circuits, Vol. 39, Issue 8, pp. 1294-1304, 2004.
CREST R&D GRANT APPLICATION FORM REV3.0
25. Ribas, R. P., Reis, A. I., Ivanov, A., “Performance and functional test of flip-flops using ring oscillator
structure,” 2011 IEEE 6th International Design and Test Workshop (IDT), pp. 42-47, 2011.
26. Ribas, R. P., Reis, A. I., Ivanov, A., “Ring oscillators for functional and delay test of latches and flip-flops,”
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, pp. 67-72, 2011.
27. Ribas, R. P., Sun, Y., Reis, A. I., Ivanov, A., “Self-checking test circuits for latches and flip-flops,” 2011 IEEE
17th International On-Line Testing Symposium (IOLTS), pp.210-213, 2011.
28. Aitken, R. C., “The challenges of correlating silicon and models in high variability CMOS processes,”
Proceedings of the 2009 International Symposium on Physical Design (ISPD’09), pp. 181-182, 2009.
29. J. N. Randall and A. Tritchkov, “Optically induced mask critical dimension error magnification in 248 nm
lithography,” Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, Vol.
16, No. 6, pp. 3606–3611, Nov 1998.
30. E. Morifuji, H. Aikawa, H. Yoshimura, A. Sakata, M. Ohta, M. Iwai, and F. Matsuoka, “Layout dependence
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31. T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto,
“Impact of well edge proximity effect on timing,” 37th European Solid State Device Research Conference,
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32. K. J. Kuhn, “Reducing variation in advanced logic technologies: Approaches to process and design for
manufacturability of nanoscale CMOS,” IEDM Tech. Dig. Papers, 2007, pp. 471–474, 2007.
33. C.-C. Liu, P. F. Nealey, Y.-H. Ting, and A. E. Wendt, “Pattern transfer using poly(styrene-block-methyl
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N. J. Rohrer, “High-performance cmos variability in the 65-nm regime and beyond,” IBM Journal of Research
and Development, Vol. 50, No. 4.5, pp. 433–449, July 2006.
35. Aitken, R. C., “Defect or Variation? Characterizing Standard Cell Behavior at 90nm and below,” 8th
International Symposium on Quality Electronic Design, 2007 (ISQED '07), pp.693-698, 2007.
36. Aitken, R. C., “DFM metrics for standard cells,” 7th International Symposium on Quality Electronic Design,
2006 (ISQED '06), pp. 496, 2006.
37. Neuberger, G., Kastensmidt, F. L., Reis, R. A., Wirth, G. I., Brederlow, R., Pacha, C., “Statistical analysis of
systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies,” IFIP
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38. Das, B. P., Amrutur, B. S., Jamadagni, H. S., Arvind, N. V., Visvanathan, Vish, “Within-Die Gate Delay
Variability Measurement Using Reconfigurable Ring Oscillator,” IEEE Transactions on Semiconductor
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(b) Objective (s) of the Research
This study embarks on the following objectives:
1) To design energy efficient CMOS standard cell library through cross-layer optimization between
library architecture, circuit and layout and process.
2) To perform library qualfication through silicon validating the designed standard cell library for
functionality, timing and power consumption and design compliance with the commercial EDA
tool.
3) To investigate and assess the impact of nanometer process variations to the standard cell library
performance.
(c) Please state research methodology
CREST R&D GRANT APPLICATION FORM REV3.0
The research project is divided into 4 main tasks:
Task 1: Energy Efficient Standard Cell Library Design
The aim of this task is to design energy efficient CMOS standard cell library through cross-layer optimization
between library architecture, circuit and layout and process. Special cells to support low power
methodologies will be designed, circuits and layout will be fine-tuned on the new Silterra 90nm low power
(LP) process.
No
1
2
3
4
5
6
7
Sub-Tasks
Design Planning: The architecture of the library including special cells to
support low power methodology and library parameters (cell height, cell
drive strength, transistor sizing, routing tracks, operating frequency,
maximum loading and others) will be defined tailoring to the Silterra 90nm
LP process and energy-efficient system requirement.
Circuit Synthesis: The best circuit topology option for low power will be
identified. Various power optimization techniques such as circuit reordering,
transistor-stacking and hybrid of these techniques will be explored through
schematic design to achieve lowest power consumption for every cell.
Layout Creation: Cell layouts are to be drawn based on the library
parameters defined earlier in the design planning phase. Layout optimization
and compaction will be applied to further reduce the power consumption.
Verification: Cells will be verified to ensure meeting the designers and
foundry specification - design rule check (DRC), layout-versus-schematic
(LVS) and electrical-rule check (ERC).
Characterization: Cells will be characterized under defined temperature,
operating voltage and process variation.
Abstraction Export: Cell’s information will be compiled into multiple files
namely the technology library (.lib), library exchange format (.lef), frame view
(.fram), layout database file (.gdsII), hardware description language (.verilog)
and milkyway library format (.mw) which will provide different level of
abstractions to the cell-based EDA design tools.
Steps 2- 6 will be repeated for N number of cells in the library.
Tool(s)
N/A
Mentor Graphics DAIC
Mentor Graphics DAIC, NANGATE layout
optimizer
Mentor
Graphics
Calibre
Cadence Encounter
Library Characterizer
Mentor Graphics DAIC,
Synopsys
Milkyway
Environment
N/A
Task 2: Circuits and Blocks Design for Standard Cell Library Validation
The aim of this task is to qualify the designed library through silicon validating the designed standard cell
library for functionality, timing and power consumption and design compliance with the commercial EDA tool.
No
1
2
Sub-Tasks
Three (3) digital blocks of different sizes and functions will be
synthesized, place and routed to exercise all designed cells in the
library and ensure that the library is at the industry-usage ready
quality. Designs will be designed and signed-off with the commercial
tools. New test-bed platform will be designed to test this digital
blocks.
Six (6) chips containing special test structures will be designed
making use of the designed cells to validate the library
characterized value. New circuit structures will be designed to
address resource issues in test-chip design.
Tool(s)
Synopsys Design Compiler
and Synopsys IC Compiler,
Synopsys PrimeTime, Mentor
Graphics
Caliber,
FPGA
platform
Mentor
Caliber
Graphics
DA-IC,
Task 3: Investigation on the Impact of nanometer process variation to standard cell library
performance
The aim of this investigation is to comprehend the impact of nanometer process variation to standard cell
library robustness and performance. The investigation will be done at the simulation-level and at the
CREST R&D GRANT APPLICATION FORM REV3.0
process-level. In the process-level investigation, process variations are deliberately introduced during
fabrications. Results from simulation-level and process-level will be correlated.
No
1
2
Sub-Tasks
Simulation-level investigation:
i.
Standard cell circuits will be investigated using SPICE (or equivalent)
circuit simulation and a Monte Carlo technique – a series of circuit
simulations will be carried out by varying certain parameters which are
related to the investigated variation sources in the devices.
ii.
This set of simulations will give the detailed distributions of any circuit
parameters of interest, with the accuracy of the distributions dependent
on the number of repeat simulations of a given nominal circuit, and the
size of the device ensemble.
iii.
The results will then be correlated with the data from process level
investigation.
Process-level investigation:
i.
The critical dimensions of specific layers such as polysilicon will be varied
by introducing variations at the lithography level.
ii.
The transistor performance will be further varied by tweaking the process
steps such as thresold implants using controlled variations.
iii.
The standard cells and the test circuits implemented using these cells will
be characterized after fabrication to evaluate the effect on the standard
cells designed and correlate the data with the simulation-level
investigation.
Tool(s)
Mentor
Graphics Spice
Simulator
Fabrication
facilities
Task 4: Test-Chip Fabrication, Testing and Measurement
The aim of this task is to fabricate the test chips with and without deliberate parameter variation. Upon
receiving the test-chips, the chips will be tested and measurement on the wafer-level and package-level will
be conducted.
No
1
2
Sub-Tasks
Test-chips will be sent for fabrication at Silterra Kulim Hi-Tech Park.
Upon receiving the test-chips, special test structure chips will be
measured at the wafer-level targeted using Silterra testing facility.
3
Digital block chips will be packaged and tested at UPM Serdang.
Equipment(s)
Silterra fabrication facility
Oscilloscope,
signal
generator, probe station,
parametric analyzer, LCR
meter
Signal
generator,
Logic
analyzer, FPGA platform
(d) Research Project Plan (Please refer CREST R&D Grant Guideline on Developing Project Plan)
1. Research project scope
This project is a joint effort between Universiti Putra Malaysia and Silterra Sdn. Bhd. to develop standard cell
library for the newly developed low-power process of 90nm deep-submicron Silterra CMOS technology.
The scope of the research covers the investigation of design and validation techniques for energy-efficient
standard cells and the assessment of the impact of nanometer process variations to the standard cell library.
It includes iterative processes of design, verification, fabrication, measurement, characterization of energyefficient standard cells, and followed by library compilation and designing test-chips for the validation of the
standard cells for SoC/ASIC applications that demand energy-efficient solutions.
The project involves three full-time graduate researchers who will be assisted by three Silterra engineers
(equivalent to one full time engineer) and co-supervised by UPM and Silterra personnels. In addition to the
existing facilities available in Silterra and UPM such as the IC design tools, measurement and fabrication
CREST R&D GRANT APPLICATION FORM REV3.0
facilities will be utilized and additional necessary tools/equipments need to be purchased to ensure the
completion of this project. The progress of the project will be monitored according to the project plan through
meetings and reports.
The results of the research will include low-power combinational and sequential logic circuits, low-power IPs,
physical designs and quantifying the effect of nanometer process variation on the standard cell performance.
The final deliverable of this project is an energy-efficient standard cell library that can readily be used by
customers. In addition, research outputs will be published in journals.
2. Flow Chart of Research Activities (Please enclose in the Appendix as appropriate)
Please find in the Appendix A.
3. Gantt Chart of Research Activities including Milestones and Dates (Please enclose in the Appendix
as appropriate)
Please find in the Appendix B.
4. Human Resources Plan (Team composition, roles and responsibilities, hiring, etc.)
Name
Dr. Fakhrul Zaman Rokhani
Roles
Project Leader, Principal
Investigator
Dr. Roslina Mohd. Sidek
Principal Investigator
Dr. Shaiful Jahari Hashim
Principal Investigator
Dr. Noor Ain Kamsani
Principal Investigator
Park Sang-Hyun
Principal Investigator
Dr. Subhash
Chan Chee-Kean, Nur Liyana
Jasni
3 MSc. Students
Advisor from industry
Researcher
Hiring Plan:
Training Plan:
Researcher
Responsibilities
Library design and library
validation using digital block
approach
Circuit and Layout optimization,
library validation using TEG
circuits approach
Design environment and design
automation
Process Variation Investigation
(simulation-level)
Process Variation Investigation
(process-level)
Fabrication side
Cell characterization, layout
optimization
Standard cell library
development, standard cell library
validation and process variation
investigation
Students will be hired as researcher in the month of May-June as this period coincides
with the semester ends
New hire research students need to undergo basic training on design environment,
design tool, Unix and scripting. In addition, research students will be exposed to
advanced VLSI and mixed signal design through courses offered at UPM.
Note: Silterra proposes to put equivalent of one full-time engineer by deploying 3-4 engineers partially on this
project for contributing towards the designs of the cells along with UPM. In addition, Silterra will also
contribute resources towards fabrication of the cells through standard Multi Project Wafer (MPW) fabrication.
5. Risk Plan
Factors that may cause risk to the project, their impact and the proposed actions against them are
summarized as the following:
CREST R&D GRANT APPLICATION FORM REV3.0
Risk
Rank
1
2
Risk Statement
Unavailability or insufficiency of
design tools
Changes in device models due to
modification in fabrication process will
delay or prolong the standard cell
development process
Risk
Impact
High
Medium
3
Unavailability for measurement
facilities
Medium
4
Incompatibility of design tools
Medium
5
Inability to hire graduate researchers
Low
6
The distance between Silterra and
UPM may cause communication and
logistic problem
Low
Risk Response
Justify the need for additional fund from
Silterra or UPM
Continuous changes in fabrication
process should be avoided and finalized
device model should be made available
prior to standard cell design activity
Prepare the test-chip design to suit other
measurement
facilities
elsewhere.
External facility will incur cost.
Test for tool compatibility at early project
stage and prepare for tool interface
development if necessary
Hire students or interns currently in
faculty. The availability of engineers for
this project minimizes the risk in human
resource.
Prepare video conferencing facility
(e) Expected output:
1. Number of Malaysian post graduate students to be produced (Please specify Master or / and
PhD)
Masters (MSc) students: 3
2. Number of potential intellectual property (patent / open source) to be filed
Product 1: Silicon Validated Energy Efficient Standard Cell Library on Silterra 90nm LP process
3. Number of expected publications (refereed conference, journal)
Conference 1 and Journal 1: On the cross-layer optimization of the library architecture, circuit, layout and
process approach for energy-efficient standard cell library
Conference 2 and Journal 2: On the new circuit architecture addressing resource constraints and pins for
multi-input cells for test-chip design in validating pre-silicon characterized standard cell library data
Conference 3 and Journal 3: On the impact of process variation to the standard cell library performance and
new developed model.
(f) Expected benefits:
1. How does this research benefits participating companies?
This project explores the possibility of local development of standard cell libraries. Once the development is
demonstrated successfully through design and implementation of standard cells and their use in ASICs
(small size with a limited purpose of demonstration), it will bring in huge benefits in terms of serving these
very essential requirements at lower cost and faster turn-around time. This further opens up possibility of
bringing in new design service companies. For any typical high-end process option at Silterra, it can
CREST R&D GRANT APPLICATION FORM REV3.0
contribute upwards of US$50m towards its annual revenue. Another major benefit is expected in terms of
faster redress of customer queries related to these libraries and opens up door for creating libraries for
specific application segments such as low power or high performance as needed by the customers.
2. How does this research benefits other companies within the industry?
Other than Silterra which is a silicon foundry, the ASIC design houses will also benefit, particularly the local
ones as this project has potential for reducing the cost of entering the ASIC Design market at reduced cost.
3. How does this research increase competency of participating universities?
The research increases the university competency in the following areas:
1. Academic Competency
This project provides a platform for university lecturers and graduate researchers to engage in IC design for
mass production which demands consideration beyond the classroom requirements such as to address
process variation and robustness. It enhances the quality of teaching and supervision as well as the skill of
postgraduates in solving real problems.
2. Research Competency
The project will improve the competency in developing standard cell library that meets the
industrial/commercial standard. The research outputs will be validated from simulation, to silicon
implementation and up to packaging which will enhance the research output for quality publication and
adding commercial value to the research product.
3. Part of Semiconductor Eco-System
Becoming as part of the semiconductor eco-system, the university has the opportunity for future
collaboration, consultancy and business development.
4. What are the shared benefits of this research to the participating companies and universities?
Typically the Standard Cell library vendors market their designs to the companies that show a good potential
for generation of large revenues through their big volume products. Through this collaboration, energyefficient 90nm standard cell library is generated for Silterra to market it to their potential customers and
strengthen UPM capability to stand up as a fabless design house. These locally owned libraries can benefit
ASIC research in academia by providing useful resources to innovate new products or applications in
advancing humanity towards a sustainable future.
D
ACCESS TO EQUIPMENT AND MATERIAL
(ACCESSIBILITY TO THE UNIVERSITY AND INDUSTRY)
Equipment
Location
CREST R&D GRANT APPLICATION FORM REV3.0
E
1. Probe-station
Silterra, Kulim High Tech Park
2. Semiconductor Parametric Analyzer
Silterra, Kulim High Tech Park
3. High Precision LCR (inductance, Capacitance and
Resistance) meters
Silterra, Kulim High Tech Park
4. Pulse/Signal Generators
Silterra, Kulim High Tech Park
5. Oscilloscope
Silterra, Kulim High Tech Park
6. Cadence Encounter Library Characterizer
Silterra, Kulim High Tech Park
7. Pattern Generator
Universiti Putra Malaysia, Serdang
8. Computer Servers
Universiti Putra Malaysia, Serdang
9. Mentor Graphics Analog Design Tool
Universiti Putra Malaysia, Serdang
10. Milkyway library Converter
Universiti Putra Malaysia, Serdang
11. FPGA platform
Universiti Putra Malaysia, Serdang
BUDGET
R&D Application
Template CREST RD Project Application Form Edited Rev. 3.0.xlsx
Note:
THE INDUSTRY IS ENCOURAGED TO CONTRIBUTE FOR THE RESEARCH. CONTRIBUTIONS IN THE FORM OF
FINANCIAL FUNDS, EXPERTISE, EQUIPMENT, SERVICES ETC. NEED TO BE TRANSLATED IN VALUE OF
FINANCIAL CONTRIBUTION
Notes for H (iv) Procurement of equipment, research material, etc.:
1. Quotation for equipment and software shall be provided.
CREST R&D GRANT APPLICATION FORM REV3.0
2. Equipment and software descriptions and the potential users shall be provided.
3. Please specify if the equipment is dedicated to a specific industry.
F
Declaration by applicant / Akuan Pemohon
(Please tick ( √ )): / (Sila tanda ( √ )):
I hereby declare that:
√
1. All information stated here are accurate, CREST has right to reject or to cancel the offer without
prior notice if there is any inaccurate information given.
2. Application of this CREST R&D grant is also presented for the other reasearch grant/s (grant’s
name and total amount)
Date :
08/03/2013
Applicant’s Signature :
Note: APPLICATIONS SUBMITTED WILL BE TREATED IN FULL CONFIDENCE. THE AWARD DECISION IS FINAL.
CHECKLIST FOR CREST RESEARCH APPLICATION FORM
1)
One (1) set of hardcopy CREST Research Application Form
√
2)
One (1) set of softcopy CREST Research Application Form
√
3)
Letter of Support signed by Company’s top management
√
4)
Letter of Support signed by University’s head of department / dean
√
√
CREST R&D GRANT APPLICATION FORM REV3.0
5)
Company’s Profile
6)
University’s Profile
√
7)
Minimum two (2) quotations for procurement of equipment.
√
8)
Minimum two (2) quotations for procurement of software.
√
9)
Minimum two (2) quotations for procurement of research materials.
10)
Minimum one (1) quotations for rental of equipment.
11)
Minimum one (1) quotations for rental of software.
12)
Minimum three (3) quotations for professional services.
√
13)
Curriculum Vitae for every researchers.
√
14)
Research project plan
√
15)
Salary/fee rate declaration (as used in industrial contribution)
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