Download Design of Ultra Low Power Tri-CAM with45nm

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 12 (2016) pp 7603-7608
© Research India Publications. http://www.ripublication.com
Design of Ultra Low Power Tri-CAM with45nm
Dr. Sreenivasa Rao Ijjada1 and Raviteja Patnala2
1,2
Department of ECE, GITAM University, Visakhapatnam, AP, India.
Abstract
Technology advancement leads to the fast growth rate in the
emerging fields of communication, space and information
technologies. The SOCs used in these fields are mostly battery
operated portable devices. Improving battery life,
performance and the density of the chip become the major
challenges for the VLSI design engineers. Major portion of
the SOC is occupied by the semiconductor memories. The
design of low voltage operated bit cell architectures may
improve the battery life of the devices. In this paper, ultra
low voltage concept based new 10T SRAM cell with body
biasing technique is proposed to design a new content
addressable memory (CAM) bit cell architecture for the high
speed searching applications. To enhance the speed further,
tri-CAM cell is preferred than bi-CAM cell and owing to the
new structure with the 24-transistor tag cell for
accommodating the one-step hit/miss, a small hit access time.
To achieve low power and good expansion capability without
sacrificing speeds, 45nm CMOS technology used in this
design. Cadence Virtuoso® tools are used for simulations.
Figure 1: content-addressable memory with w words
Match-lines are fed to an encoder, generates a binary match
location corresponding to the match-line is the match state.
An encoder is used to expect only a single match. In addition,
there is often a hit signal that flags the case in which there is
no matching [4]. A search operation begins with loading the
search-data word into the search-data register followed by
pre-charging. The search-line drivers broadcast the search
word onto the differential search-lines, and each CAM cell
compares its stored bit against the bit on its corresponding
search-lines [5]. Match-lines with all bits matches remain in
the high state. Match-lines that have at least one bit that
misses discharged to ground. Bit cell serves two functions, bit
storage and bit comparison. The speed of cell comes at the
cost of increased area and power, two design parameters that
designers strive to reduce. As its applications grow,
demanding larger CAM sizes, the power problem is further
exacerbated. Reducing power, without sacrificing speed, is the
main thread of recent research in large-capacity CAMs.
In order to achieve powerful data searching, comparison
circuit architecture is implemented in parallel. All valid data
stored in the CAM compared with the input data
simultaneously and the address from those matches of
comparison is the output. It requires greater amount of the
power and much hardware [6-7]. To reduce the search current
NAND-type match-line circuit proposed rather than the NORtype [8]. Selective pre-charge technique was proposed to
reduce the power in the large memories with the cost of delay
[9]. Noise margin, charge sharing and other problems in the
dynamic CMOS circuit design in the achievement of low
power CAM cell architectures were explained [10].
To convince OC-48 ATM requirements, proposed a new
design with a search access time of 26n sec, cycle time of 32n
sec and dissipates an average power of 5.2W when
performing the search operations at 25 MHz. At 65 nm
technology, it consumes 4.021 mW power compared to the
traditional CAM consumes-12.538 mW at 800 MHz [11]. To
limit the voltage swing of match lines thereby reduce the
Keywords: Ultra low voltage, SRAM,CAM, Tri-CAM
INTRODUCTION
CAM is a special type of memory used in very high speed
searching applications. It is fully associative memory with a
search time of only one clock cycle unlike the traditional
SRAMs requires two or more clock cycles for a search
operation and allows access of data instead of physical
address as in the case of SRAM and DRAM. CAM consumes
less energy for a search compared to RAM. The primary
commercial application of CAM is the forward Internet
protocol (IP) packets in network routers [1]. The two types
CAMs are Bi- CAM and Tri-CAM. In networks like Internet,
a message(e-mail or Web page) is transferred by first breaking
up the message into small data packets of a few hundred
bytes, and then, sending each data packet individually through
the network. It is a good choice for implementing lookup table
operation due to its fast search capabilities [2]. The CAM with
w words is shown in the Figure1. Here the input is the search
word and is broadcast onto the search-lines to the table of
stored data.
The number of bits in a CAM word is usually ranging from 36
to 144 bits. A typical CAM employs a table size ranging
between a few hundred entries to 32K entries, corresponding
to an address space ranging from 7 bits to 15 bits[3]. Each
stored word has a match-line that indicates whether the search
word and stored word are identical (the match case) or are
different (a mismatch case, or miss).
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International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 12 (2016) pp 7603-7608
© Research India Publications. http://www.ripublication.com
power in match lines proposed a new technique [12]. Here, a
PMOS match line driver used to enable the match line
discharge level and sustain at the deeply back gate biased
transistor’s threshold voltage above the ground level. The
voltage swing of match line reduced further by reducing precharged level with deeply back gate biased NMOS isolation.
A pre-computation based CAM is proposed to eliminate most
of the comparison operations to reduce majority parts of the
power in the parallel comparison process and achieves low
power, low cost, and low voltage features [13]. It results that
the data searching speed of the chip achieves 100 MHz with
power consumption less than 33 mW at 3.3V. Moreover, the
experimental results indicate that the minimum operating
voltage of the chip is 1.5V. A low-power self-disable sensing
technique for CAM has been proposed in the papers [14]-[16].
These methods reduce the unnecessary dc currents. Moreover,
the comparison process has been accelerated by a positive
loop to reduce the unwanted power dissipation. The word
match line structure of low power Bi-CAM employs static
pseudo CMOS logic. HSPICE simulations for 32x32 and
128x32 CAM were performed under 180 nm technologies for
different cell structures results the power dissipation of 3.94
mW with the delay of 2.02n sec @ 1.8 V [18]. A 1V 128KB
4-way set-associative CMOS cache memory with word lineoriented tag-compare structure in a 180 nm CMOS technology
for low supply voltage and low power VLSI applications
implemented [17]. It results an access time of 3.5n sec, and
power of 4.1 mW at 50 MHz.
Demand of ultra-low-power circuits for the WSNs forces the
importance of circuit designs in the sub-threshold regime [19].
In sub-threshold, the current density is very low and the ratio
of the trans-conductance to bias current is maximum.
Exponential relation between drain current and gate voltage
makes it more suitable for wide range of applications.
Conventional CMOS circuits utilize sub-threshold operation
with a very low power, which is mainly due to the dynamic
power and is quadratically dependent to the supply voltage
[20]. Reduced supply voltage will result in reduction of power
and output logic swing but increases the delay in each gate.
6TSRAM cell. The CAM cell uses SRAM cell to store the
data and for comparison purpose, three more transistors (TN1,
TN2 and TN3) are employed. The comparison circuitry varies
depending on the design and the implementation. The sense
amplifiers and latches provide an interface to give the result of
the search. A CAM cell has four different states of operation
[21].
i) Standby: where the circuit is inactive
ii) Reading: when the data has been requested
iii) Writing: when revising the contents
iv) Comparing: comparing the data that is stored.
The standby, reading and writing operations of CAM is
similar to SRAM. Bit comparison logic is an equivalent to
XOR of stored and search bits. The comparison mode begins
with pre-charging the ML to ‘VDD’, then the complementary
search data is loaded into the bit lines and this is compared
with the storage cell contents.
Figure 3: Conventional Bi-CAM cell
The cell compares its stored bit with the bit on its
corresponding search line. If it mismatches, the word match
line will be pulled down only when bit match, otherwise state
will be kept as pre-charged.
Analysis: When Vin = 0, transistor TP2 is ‘ON’ and is in the
saturation then the voltage at the source node of TP2 is 1.8V,
since, VDD=1.8V and out = ‘VDD’. Since the transistor TN7
source terminal is grounded i.e., Vg = 0, its drain to source
voltage
CAM DESIGN METHODOLOGY
The two basic forms of CAMs are binary and ternary. BiCAM stores and searches binary bits, zero or one (0,1), while
Tri-CAM supports additionally don't care bit (0,1,X) also as
shown in the fig 2. Tri-CAMs presently the dominants since
longest-prefix routing are the Internet standard.
VDS > VGS − VTH 7
VD − VS > VG − VS − VTH 7
VD = Vout > 0 − VTH 7
∴Vout = 1.3V (becauseVTH 7 = 0.3V )
As BLbar is high and VS = Vin = 0 , the transistor TN3 is in
cutoff and is ‘OFF’ since the gate voltage of the transistor
TN1 is the drain voltage of the transistor TN3, the output for
matchline (ML) = 0. Therefore, it is observed that when the
stored bit is logic‘0’ and is compared with the March line
driver (MDL) =1, it satisfies the mismatch condition.
Figure 2: Bi-CAM and Tri-CAM search tables
Basic CAM cell architecture is shown in the fig 3. Its structure
(TP1, TN6-TP2, TN7-TN4, and TN5) is similar to the
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International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 12 (2016) pp 7603-7608
© Research India Publications. http://www.ripublication.com
Hence the power consumption is less. DTMOS cell offers
more supply voltage scaling to decrease the power in ultra low
power applications. In addition, it improves the SNM in
hold/read compared to 6T-SRAM cell. This circuit enables the
SRAM to work properly with a supply voltage below 135mV
for wireless applications. A new 10T SRAM cell has been
proposed as shown in Figure 5 to improve the SNM in
hold/read modes compared to other SRAM cells.
TRI-CAM DESIGN METHODOLOGY
The binary CAM cells stores either logic “0” or logic “1”, in
addition to that ternary cells stores an “X” (don’t c are)
value[22]. A ternary symbol can be encoded into two bits,
ternary storage requires only three states, the state where
BL1c and BL2c are both zeros case is not allowed. To store a
ternary value in a cell, second SRAM cell added as shown in
Figure 4. An “X” can be store by setting both BL1c and BL2c
equal to logic “1”, which disables both pull-down paths and
forces the cell to match regardless in the inputs. Logic “1”
ഥ =0 and store a logic
can be stored by setting BL1c =1 and ‫ܦ‬
“0” by setting D=0 and BL2c=1. In addition to storing an “X”,
the cell allows searching for an “X” by setting both SL and to
logic “0”. This is an external don’t care that forces a match of
a bit regardless of the stored bit. Although storing an “X” is
possible only in ternary CAMs, an external “X” symbol
possible in both binary and ternary CAMs. The conventional
Tri-CAM structure has an advantage that it has less number of
transistors (means less area) compared to proposed structures.
It can operate upto 0.25 v supply voltage. The Conventional
Tri-CAM has less stability as it is very affected by the process
variations. The threshold voltage has its highest importance in
the subthreshold operation.
Figure 5: Proposed body biased SRAM for Tri CAM design
The proposed design takes more area compared to 6T-SRAM
cell but its operation down to supply voltages of 250mV.
Hence it decreases the dynamic power more and facilitates
more supply voltage scaling for ultra low power needs. For all
designs, upsizing is used to work in sub-Vth region, properly.
Anyway, upsizing method in sub-Vth has not significant
effect on static noise margin (SNM) improvement as much as
super-threshold design.
Figure 4: Conventional Tri-CAM cell
Due to lower frequency rate, the supply voltage may be
reduced below the threshold voltage. This operation is
referred as sub-threshold design that uses the sub-threshold
current as drive current to evaluate the inputs. Lowering the
supply voltage reduces the subthreshold current,
exponentially. Due to the effect of Vth variation on subthreshold current, working in this region causes more
sensitivity to process variations. The effect of process
variation is more important in circuits such as memories, that
causing data loss on storage nodes in memories. Due to
minimum size transistors in SRAM memories, the sensitivity
to inter-die as well as intra-die process variations is
significant. Failure in SRAM such as Read and Write are
caused by process variations in ultra low supply voltage
applications.
Figure 6: Proposed Tri- CAM cell
The new Tri-CAM cell can be formed by the combination of
two proposed SRAM cells, search transistors and match line
transistor. The proposed Tri-CAM cell is shown in the fig 6.
The proposed Tri-CAM cell has an advantage of that it has
read margin compared to conventional Tri-CAMs. The area of
the cell is increased due to the extra transistors are used to
body bias the structure. So overall power consumption and
delay also increased with respect to conventional one, but not
to a significant value. It can operate up to 0.22 v. The
Proposed TCAM
The 5T, 8T, and 10T SRAM cells employs single ended
reading, 6T and 7T SRAM cells utilizes differential read
operation. 8T and 10T SRAM cells uses separate read line to
read data, so these designs improve Read SNM compared to
6T-SRAM cell. This design uses more area but works at lower
supply voltages.
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International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 12 (2016) pp 7603-7608
© Research India Publications. http://www.ripublication.com
following table gives the information about power, delay and
SNM of the conventional TRICAM cell. The Write SNM of
the Tri-CAM is degraded when compared to the Conventional
one but the Read SNM is improved up to 17% – 20%
RESULTS
The conventional Tri-CAM structure has an advantage that it
has less number of transistors (16)compared to the Proposed
Tri CAM Transistor count 24. But the Conventional Tri-CAM
can be efficently works upto 0.25 v supply. The following
table-1 gives the information about power, delay and SNM of
the conventional Tri-CAM cell. The Conventional Tri-CAM
has less stability as it is very affected by the process
variations. The threshold voltage has its highest importance in
the subthreshold operation. The values of Read and Write
SNM reflects the stability of a cell. The hold SNM of a cell
does not vary with the process, voltage or temperature
variations. Therefore the hold margin does not have particular
importance.
0.8
0.6
0.5
0.3
0.29
0.28
0.27
0.26
Power
(nW)
25.66
15.01
4.275
1.533
1.470
1.394
1.289
1.216
Delay
(ps)
4.10
11.3
32.7
64.5
80.3
108.2
117.6
127.3
Write
SNM
(mV)
272.8
198.35
181.75
170.45
140.26
121.42
115.73
109.39
1.227
192.6
154.27
73.276
0.23
1.121
206.1
147.15
68.045
0.22
0.972
223.4
139.41
62.176
Figure 7: Power comparisons of both tri-CAMs
Table. 1: Conventional Tri-CAM performance parameters
Vdd
(V)
0.24
From the Figure7, it is obseved that the power of newcell had
been increased by 3-5% with respect to conventional for the
operating voltage more than 0.26V. But at voltages lower than
0.26 its power is drastically decrease.
From the Figure8, it is clear that the delay of the proposed cell
slightly increased due to the extra circuitry that causes extra
parasitic capacitances.
Read SNM
(mV)
130.67
121.21
102.730
86.731
72.934
67.876
63.921
61.281
Where as the proposed Tri-CAM cell with the new SRAM
cell Architecture designed is shown in the Figure5. This new
Tri-CAM effectively designed for ultra low votage operation
i.e upto 0.22V which is fao below the threshold voltage of
transistor at 45nm. The following table 2 shows the
power,delay, read and write static noise margines.The
convenional Tri-CAM works with less power when compared
to new structure,but its operation seases below0.26V.
Table. 2: Proposed Tri-CAM performance parameters
Vdd
(V)
0.8
Power
(nW)
27.92
Delay
(ps)
4.32
Write SNM
(mV)
282.69
Read SNM
(mV)
167.588
0.6
18.37
12.13
260.76
140.642
0.5
6.92
34.5
242.53
134.977
0.3
3.02
69.7
231.34
121.617
0.29
2.16
81.76
224.47
114.268
0.28
1.95
116.2
219.63
102.930
0.27
1.76
121.3
203.46
97.526
0.26
1.529
132.5
189.66
89.833
0.25
1.316
138.7
167.59
79.937
Figure 8: Delay comparisons of both tri-CAMs
The delay of the proposed circuit has been increased upto 7%
with respect to conventional one hence the speed is little bit
reduces. In the whole cell design the important parameter is
SNM in both read and write modes. From the fig 9 & 10, it is
clear that the write and read SNMs are more even at 0.22V
also.
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Figure 9: Write SNM comparisons of both tri-CAMs
27% of Write SNM and 18% of read SNMs are improved
when compared to conventional Tri-CAM for the Ultra low
voltage range.
Figure 10: Read SNM comparisons of both tri-CAMs
CONCLUSIONS
From the results, it is observed that both Bi-CAM and TriCAM cells can operate ultra low voltage 260mV. Tri-CAM
cells offers very low power and they are high speed compared
to Bi-CAM cells but the stability of Bi-CAM is high compare
to Tri-CAM cells. New TRICAM topologies based on body
biasing technique are proposed. SNM in read/write/hold have
been improved compared to other conventional TRICAM
cells. Using body-biasing technique in TRICAM cells
increases the area but improves the effect of upsizing on SNM
and improves the SNM in read/hold/write modes. The
proposed circuit occupies larger areas due to using separate NWell but they are only choice for ultra low voltage operated
wireless applications. All the simulations are done using
CADENCE software in 45nm technology. Cadence
Virtuoso® is trademark tool.
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International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 12 (2016) pp 7603-7608
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