Download RF MEMS Charge Pump

Data Sheet
TT6820QFN / TTP681A20
RF MEMS
Charge Pump
FEATURES
DESCRIPTION
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The TT6820QFN / TTP681A20 Charge Pump is
designed to supply the 68V control signals
required by TeraVicta MEMS switches.
The charge pump can drive multiple TeraVicta
MEMS switches from a 3.0V control line. The
charge pump has six edge-sensitive inputs
which drive six independent output lines.
When combined with multiple miniaturized
TeraVicta
switches,
the
TT6820QFN
/
TT681A20 provides a small footprint 3V switch
solution.
Low power consumption: 3 mW at VDD=3V
Six independent switch driver channels
Edge Sensitive, Latched CMOS logic-level inputs
Unused inputs disabled via active pull down device
Low current sleep mode
Power-On Reset
RoHS Compliant
PIN DESCRIPTIONS
One charge pump can control up to three
independently operating banks of multiple
SPDT switches (for example, each TT71268CSP SPDT requires two control lines).
Alternatively, if two SPDTs are operated in
tandem as a DPDT, then each pair of SPDTs
operating in this fashion requires only two
lines.
As a result, one charge pump can
control six SPDTs operating as three DPDTs.
FUNCTIONAL BLOCK DIAGRAM
Pin
Label
QFN Pin
Number
TSSOP Pin
Number
GND
1
20
VDD
2
1
NC
3
19
Sleep
4
2
Description
Ground
Logic Supply Voltage
No Connect
Sleep Mode Enable
(Active HIGH)
NC
5
18
Out1
6
3
No Connect
Driver 1 Output
Out2
7
4
Driver 2 Output
Out3
8
5
Driver 3 Output
Out4
9
6
Driver 4 Output
Out5
10
7
Driver 5 Output
Out6
11
8
Driver 6 Output
VCP
12
10
NC
13
9
Charge Pump Output
No Connect
IN6
14
12
Driver 6 Enable
NC
15
11
No Connect
IN5
16
13
Driver 5 Enable
IN4
17
14
Driver 4 Enable
IN3
18
15
Driver 3 Enable
IN2
19
16
Driver 2 Enable
IN1
20
17
Driver 1 Enable
Figure 1. Functional Block Diagram
Ordering Guide
Part
Operating
Other
Package
Control Voltage
TT6820QFN
QFN-20
2.7V – 5.5V
-40°C to +85°
RoHS Compliant
TTP681A20TC
TSSOP-20
2.7V – 5.5V
-40°C to +85°
RoHS Compliant
Number
Copyright © 2007 TeraVicta Technologies, Inc.
Temperature Range
June 2007 v2.7
Data Sheet
TT6820QFN / TTP681A20
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD)
Input Voltage (IN1-6, Sleep)
Operating Junction Temperature
Storage Temperature Range
-0.3V to 6.5V
-0.3V to VDD+0.3V
-40°C to +85°C
-40°C to +150°C
SPECIFICATIONS (TA=25oC unless otherwise noted)
Typical values are representative of laboratory measurements. TT6820QFN and TTP681A20 specifications are
identical unless otherwise noted.
Parameter
ESD Voltage
Operating Conditions (VDD=3V)
Logic Supply Voltage
Logic Supply Current
Sleep Mode Current (See Note 1)
High Side Supply Voltage
Driver Output Voltage HIGH
Driver Output Voltage LOW
Power Dissipation (68V)
Static Electrical Characteristics
Resistive Load
LOGIC SECTION
Logic “1” input voltage VDD=2.7
Logic “1” input voltage VDD=3.4
Logic “0” input voltage VDD=2.7
Logic “0” input voltage VDD=3.4
Logic “1” input current (INx<=5V)
Symbol
VESD
Min
Typical
Max
2.0
Unit
kV
VDD
IDD
IDDsip
Vcp
VoutH
VoutL
PD
2.7
3
950
5.5
8
66
VCP-.2
V
µA
µA
V
V
V
mW
RL
200
VinH
VinH
VinL
VinL
IinH
1.9
2.2
GND
GND
67.5
15
69
GND+.2
3
MΩ
1.6
2.0
1.2
1.5
0.7
VDD
VDD
1.2
1.7
2
V
V
V
V
µA
Typical
Max
Unit
Notes:
1) Sleep mode current when VDD=2.7V (MIN) and VDD=5.5V (MAX)
DYNAMIC ELECTRICAL CHARACTERISTICS
Typical values are representative of laboratory measurements.
Parameter
Oscillator Frequency (see Note 1)
Symbol
Min
fs
2
MHz
trOUT
2.6
µS
tfOUT
500
nS
tpdOUT
1.5
µS
tpdVCP
7.5
mS
tEN
3.0
mS
Delay Sleep Pin HIGH to VCP LOW
(Ccp = 40pF)
tSLP
7.5
mS
Delay Sleep Pin LOW to VCP HIGH
(Ccp = 40pF, Out1 High)
tpdSLP
3.3
mS
Output Driver rise time 5 to 95%
(Cload=10pF, VCP=68V)
Output Driver fall time 5 to 95%
(Cload=10pF, VCP=68V)
Output Driver Prop Delay (Cload=10pF,
VCP=68V)
Delay VDD HIGH to VCP HIGH
(Ccp=40pF, Out1 High)
Delay VCP HIGH to Input Latch Enable
(see Note 2)
TeraVicta Technologies, Inc.
Austin, Texas U.S.A.
Page 2 of 8
www.TeraVicta.com
June 2007 v2.7
Data Sheet
TT6820QFN / TTP681A20
TIMING DIAGRAMS
VDD
tpdVCP
VCP
tEN
IN0
OUT0
IN1
tpdOUT
tpdOUT
OUT1
trOUT
tfOUT
Figure 2. Startup Timing and Output Delay Timing
SLEEP
tSLP
VCP
tpdSLP
Figure 3. Sleep Mode Timing
Notes:
1) The inputs, IN1-IN6 are edge sensitive. As shown in Figure 2, an edge received on IN0 before time
tEN (after the VCP propagation delay, time tpdVCP) will not propagate to the output Out0.
2) Typically the level seen on the RF lines of a closed switch (for example, TT712-68CSP) driven by a
charge pump is <-135 dBm @ 2MHz oscillator frequency.
TeraVicta Technologies, Inc.
Austin, Texas U.S.A.
Page 3 of 8
www.TeraVicta.com
June 2007 v2.7
Data Sheet
TT6820QFN / TTP681A20
APPLICATION CIRCUIT
Figure 4. TT712-68CSP-EB Circuit Diagram
TeraVicta Technologies, Inc.
Austin, Texas U.S.A.
Page 4 of 8
www.TeraVicta.com
June 2007 v2.7
Data Sheet
TT6820QFN / TTP681A20
OPERATING INFORMATION AND PRECAUTIONS:
1.
Power Up Sequence: VDD must be applied to the charge pump device before a voltage is applied
to the control lines IN1-6. Driving the inputs high before VDD has been applied will cause the input
structure ESD protection diodes to function improperly and will damage the device.
2.
Startup Sequence and Latching Inputs: For noise immunity, inputs IN1-6 are edge-sensitive.
This means that if the charge pump is powered up with any of the inputs high, the outputs will not
be high. To make the output go high requires bringing the corresponding input low and then high
again (creating an edge) after the VCP propagation delay (tpdVCP) and after input latch enable delay
(tEN).
3.
VDD: Internal structures at this pin are designed to operate at logic supply voltages less than or
equal to 5.5 Volts. The absolute maximum voltage rating at this pin is 6.5V - input voltages
exceeding this maximum will damage the IC. If VDD supply voltage is known to exceed 6.5V, a 5V
zener diode must be connected between VDD and GND to limit the voltage at this pin. A 0.1µF
decoupling capacitor is required at this pin.
4.
IN1-6, Sleep: To ensure proper operation, it is necessary that input voltages are kept between VDD
and GND.
5.
Test and measurement of VCP voltage: Most voltage measurement devices draw more current
from the VCP output pin than the typical MEMS relay load (i.e. a probe or DMM with 1MΩ input
impedance will draw 68µA at 68V, 10MΩ will draw 6.8µA...etc.). These devices will load the VCP pin
and affect the accuracy of voltage readings. Once VCP functionality has been confirmed, it is
strongly recommended that these measurement devices be removed prior to operation of the IC;
especially if SLEEP mode is to be utilized.
6.
Although low-current active pulldown devices are provided on the following pins (IN1-6, Sleep), it is
recommended that unused pins be grounded, especially if the IC is to be operated in a noisy
environment.
7.
The charge pump output, VCP, requires an external capacitor, Ccp (>= 40pF, >70V breakdown).
Increasing Ccp from 100pF may improve the immunity of the VCP rail from transient current spikes
and other events that may temporarily disrupt the 68V output. However, larger Ccp capacitors will
increase the VCP power up time.
8.
The charge pump is a high impedance device which is sensitive to leakage paths between leads that
can be caused by flux residue. For this reason, the solder mask should be open only where solder
will actually be applied when mounting the TT6820QFN. It is essential that no conductive flux residue
be left on the PCB after assembly. It is strongly recommended that assembly be done with noclean flux and that the PCB NOT be cleaned after assembly. The TTP681A20TC should be used if noclean flux is NOT used for PCB assembly.
9.
The TT6820QFN / TTP681A20 can drive multiple TeraVicta MEMS switches due to the high impedance
of the gate on the switch, however depending on the total capacitance of the lines driven by the
charge pump the switching time may increase. PCBs and PCB layouts will have varying amounts of
capacitance for a number of switches. The total capacitance on all driver outputs from the charge
pump should be kept below 40pF.
TeraVicta Technologies, Inc.
Austin, Texas U.S.A.
Page 5 of 8
www.TeraVicta.com
June 2007 v2.7
Data Sheet
TT6820QFN / TTP681A20
CASE OUTLINE: TT6820QFN
NOTES:
D
1. DIMENSIONS AND TOLERANCING
CONFORM TO ASME Y14.5-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS,
Ø IS IN DEGREES
4
E
INDEX AREA
(D/2 X E/2)
3. N IS THE NUMBER OF TERMINALS
4. THE TERMINAL #1 IDENTIFIER AND
TERMINAL NUMBERING CONVENTION
CONFORM TO JEDEC PUBLICATION 95
SPP-002. THE TERMINAL #1 IDENTIFIER
IS LOCATED IN THE ZONE INDICATED.
THE TERMINAL #1 IDENTIFIER MAY BE
EITHER A MOLD OR MARKED FEATURE.
TOP VIEW
5. DIMENSION b APPLIES TO METALLIZED
TERMINAL AND IS MEASURED BETWEEN
0.15mm AND 0.30mm FROM THE TERMINAL
TIP.
4X Ø°
A3
6. ND AND NE REFER TO THE NUMBER
OF TERMINALS ON EACH D AND E SIDE
A
SIDE VIEW
7. THIS PACKAGE IS COMPLIANT TO JEDEC
MO-220 VHHC-2
D2
MILLIMETERS
DIM
E2
1
4
INDEX AREA
(D/2 X E/2)
L
20
b
e
6
A
A3
b
D
D2
E
E2
e
L
Ø°
N
NE
ND
MIN
NOM
MAX
0.80
0.25
3.50
3.50
0.35
0°
0.90
0.20 REF
0.30
5.00
3.65
5.00
3.65
0.65
0.40
1.00
0.35
3.80
3.80
0.45
14°
20
5
5
BOTTOM VIEW
TeraVicta Technologies, Inc.
Austin, Texas U.S.A.
Page 6 of 8
www.TeraVicta.com
June 2007 v2.7
Data Sheet
TT6820QFN / TTP681A20
CASE OUTLINE: TTP681A20TC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE
ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE −W−.
TeraVicta Technologies, Inc.
Austin, Texas U.S.A.
Page 7 of 8
MILLIMETERS
INCHES
DIM
MIN
MAX
MIN
MAX
A
6.40
6.60
0.252
0.260
B
4.30
4.50
0.169
0.177
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
C
G
H
1.20
0.65 BSC
0.27
0.37
0.047
0.026 BSC
0.011
0.015
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
M
6.40 BSC
0°
8°
0.252 BSC
0°
8°
www.TeraVicta.com
June 2007 v2.7
Data Sheet
TT6820QFN / TTP681A20
REVISION HISTORY
Rev.
Date
Revision 2.7
6/15/07
Revision 2.6
4/16/07
Revision 2.5
11/20/06
Revision 2.4
07/12/2006
Revision 2.3
04/01/2006
Description
• Added information for TSSOP package – TTP681A20TC
• Reformatted document.
• Removed duplicate reference to Power Dissipation in Absolute Maximum Ratings.
• Reduced the level of accuracy for Typical values of “Static Electrical
Characteristics.”
• Added timing diagrams.
• Replaced VSS with GND and VCC with VDD.
• Added “edge-sensitive” to description of input pins IN1-6.
• Added Operating Information 1 about driving the control inputs before VDD has
been applied to the device.
• Added Operating Information 8 about assembly.
• Moved Operating Information 9 from the Description text on page 1.
• Replace package drawing with more complete drawing.
• Added “, however depending on the total capacitance of the lines driven by the
charge pump the switching time may increase.” on the 1st column, page one (per
testing).
• Added Revision Page.
• Added existing Version to Doc Control System.
Information in this document is provided solely to enable system implementers to use TeraVicta products. Product characteristics and specifications mentioned
in this document are subject to change without prior notification. TeraVicta Technologies assumes no obligation regarding future manufacture unless otherwise
agreed to in writing. TeraVicta Technologies does not warrant this product for use in any application, and assumes no responsibility for damage resulting from
the use of this product; or for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of TeraVicta Technologies.
TeraVicta Technologies, Inc.
Austin, Texas U.S.A.
Page 8 of 8
www.TeraVicta.com
June 2007 v2.7