Download 88AP510 Hardware Specifications

88AP510
High-Performance SoC with
Integrated CPU, 2D/3D Graphics
Processor, and High-Definition
Video Decoder
Hardware Specifications
Doc. No. MV-S105141-U0, Rev. F
July 13, 2011, Preliminary
Marvell. Moving Forward Faster
Document Classification: Proprietary Information
88AP510
Hardware Specifications
Document Conventions
Note: Provides related information or information of special importance.
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Doc. No. MV-S105141-U0 Rev. F
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Copyright © 2011 Marvell
Document Classification: Proprietary Information
July 13, 2011, Preliminary
Revision History
Revision History
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Rev. F
July 13, 2011
Revised Draft
1. Added the following note to M_DQS[3:0]/M_DQSn[3:0] in Table 5, DDR SDRAM Interface Pin Assignments, on
page 30:
NOTE: A 1 Kilohm pull-down resistor must be connected to DQS. A 1 Kilohm pull-up resistor must be connected to
DQSn. The resistor must be a least 500 mils from the 88AP510. For more information, see the 88AP510 Design
Guide.
2. Added the following note to M_AVDD in Table 28, Power Supply Pin Assignments, on page 53:
NOTE: If unused, connect to GND.
3. Removed M_AVDD from Table 37, I/O, Analog, and Core Voltages, on page 73, Table 41, Absolute Maximum Ratings,
on page 82, and Table 42, Recommended Operating Conditions, on page 85.
4. Revised Table 45, I/O Interfaces Power Dissipation, on page 89 to only support DDR3 SDRAM at 500 MHz.
5. Change Table 66, SDRAM DDR3 1.5V Interface AC Timing Table, on page 119 to 500 MHz support.
6. In Section 9.6.10, Serial Peripheral Interface (SPI) AC Timing, on page 129:
• Added Note 4 to Table 73, SPI (Master Mode) AC Timing Table, on page 129.
• Combined four figures into one in Table 37, SPI (Master Mode) AC Timing Diagram, on page 130.
Rev. E
February 17, 2011
Revised Release
1. Added detail about SPI support for timing mode CPOL=CPHA=0 in the SPI Controller features.
2. Added support for DDC2 monitor interface for Extended Display Identification Data (EDID) in the TWSI Controller
features.
3. Corrected the name of the VGA_AVSS pin to VGA_VSS in Table 28, Power Supply Pin Assignments, on page 53, and
throughout the specification.
4. In Table 31, Unused Interface Strapping, on page 59:
• Included PEX<n>_ISET as one of the PCIe signals that can be left unconnected.
• Deleted a portion of the VGA port description. It is not required to tie VGA_EXT_CLK to ground.
5. Added Table 36, Supported Clock Combinations, on page 70.
6. In the attached reset strapping Excel file in Section 7.5, Pins Sample Configuration, on page 76, the following changes
were made:
• Revised CPU clock frequency options.
• The following extended boot options are now reserved: 0x8, 0xC, 0x10, 0x14, 0x18, 0x1C.
7. Added 0x7 as the 88AP510-A1 setting in Table 40, IDCODE Register Map, on page 81.
8. In Table 42, Recommended Operating Conditions, on page 85:
• Added 400/500 MHz and 1 GHz values for VDD_CPU.
• Added 1 GHz value for VDD_CORE.
9. Revised the values in Table 43, CPU Subsystem Power Dissipation, on page 88 and Table 44, SoC Core Power
Dissipation, on page 89.
10. Revised the output low/high level test conditions to 8/-8 mA in Table 48, General 3.3V Interface (CMOS) DC Electrical
Specifications, on page 96 Table 49, General 2.5V Interface (CMOS) DC Electrical Specifications, on page 97, and
Table 50, General 1.8V Interface (CMOS) DC Electrical Specifications, on page 98.
11. Changed the tIS value from tRP-18 ns to tRP-22 ns in Table 62, NAND Flash AC Timing Table, on page 112.
12. Added “Return loss includes contributions from on-chip circuitry, chip packaging, and any off-chip components related
to the driver/receiver” to Note 1 in Table 87, PCI Express Interface Driver and Receiver Characteristics, on page 149.
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
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Hardware Specifications
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Rev. D
June 23, 2010
Revised Release
1. Changed the following pins throughout the document:
• The RSVD_VDD_CPU pins are now named RSVD_VDD_CORE[1:0].
• VGA_CLK and VGA_E are now LCD_EXT_REF_CLK[0] and LCD_EXT_REF_CLK[1], respectively (see Table 10,
LCD Serial Peripheral Interface Pin Assignments, on page 36).
NOTE: If a single external reference clock is used, Marvell® recommends to use LCD_EXT_REF_CLK[1].
• VGA_RGB_AVSS, VGA_DAC_AVSS, and VSSM pins are now named VGA_AVSS.
2. Added DDR2/3 connection information for the M_CAL pin in Table 5, DDR SDRAM Interface Pin Assignments, on
page 30. For DDR2, connect to VSS through a 300 ohm (1%) resistor. For DDR3, connect to VSS through a 240 ohm
(1%) resistor.
3. In Table 31, Unused Interface Strapping, on page 59:
• Revised the strapping guidelines for the Audio 0, 1, and SSP units. If these interfaces are unused, it is only required to
connect VDDO_AUD to 3.3V.
• Added strapping information for VDDO_SDIO1. If this interface is unused, connect to 3.3V.
• Added strapping information for the VGA_EXT_CLK. It must be connected to ground.
4. Added LCD controller clock information to Table 35, 88AP510 Clocks, on page 69.
5. Revised Figure 6, Power Up Sequence, on page 73 to show that the CPU can be powered up at any time before the
VDD_CORE.
6.
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In Section 7.5, Pins Sample Configuration, on page 76, the attached reset strapping file:
Added Boot from NAND Flash mode extended option in SAR0[30] in the “Core and IO Reset Strapping” worksheet.
Added extended boot options for SAR[30]=0x1 in the “Boot Mode Options” worksheet.
Added CPU PLL Frequency (MHz) data in the “Clock Frequencies” worksheet.
7. Revised Table 40, IDCODE Register Map, on page 81.
8. Revised the note associated with VDDO_VGA in Table 42, Recommended Operating Conditions, on page 85.
NOTE: Apply typical 3.3V for VGA digital signals and the LCD external reference clock.
9. Added Table 57, NAND Flash 3.3V DC Electrical Specification, on page 104 and Table 58, NAND Flash 1.8V DC
Electrical Specification, on page 104.
10. Added the LCD External Clock value to Table 59, Reference Clock and Reset AC Timing Specifications, on page 105.
11. Added Figure 20, NAND Flash Output AC Timing Diagram, on page 113.
12. Added the following note after Table 79, LCD AC Timing Table, on page 139:
NOTE: The LCD_CLK output can be shifted by 90/180/270 degrees with clock invert mode and/or the FTDLL.
13. Revised Figure 51, VGA Hsync/Vsync Test Circuit, on page 142 as follows:
• Pullup resistor was removed.
• Pulldown resistor value was updated to 2.2 kilohm.
14. Changed units from ns to tCK for frame signal parameters in Table 81, SSP Clock Master Frame Master AC Timing
Table, on page 143.
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July 13, 2011, Preliminary
Revision History
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Rev. C
February 5, 2010
Revised Release
NOTE: The changes in this Hardware Specification revision apply to device revision X0.
1. In Table 26, Miscellaneous Pin Assignments, on page 51:
• Changed the MRn signal pin type to CMOS.
• Added resistor details for RTC_XIN and RTC_XIN
2. Added 1.8V power option for VDDO_SDIO0/1 in Table 28, Power Supply Pin Assignments, on page 53 and Table 42,
Recommended Operating Conditions, on page 85.
3. Revised the strapping description for the RTC interface in Table 31, Unused Interface Strapping, on page 59. The RTC
must be connected to external 32.768 KHz crystal to ensure proper operation.
4. Added the following MPP options to the list in Section 5.1, MPP[71:0] Multiplexing Options, on page 61 with the
following changes.
MPP PinSetting
Option
MPP[8]0x1
WD_RST_OUT (output)
MPP[9]0x5
PEX1_CLKREQn (input)
MPP[10]0x5 SSP_SCLK (in/out)
MPP[11]0x5 PEX0_CLKREQn (input)
5. Made several changes to the attached Reset Strapping Excel file in Section 7.5, Pins Sample Configuration,
on page 76. For details, see the revision history in the Excel file.
6. Added X0 stepping version number information to Table 40, IDCODE Register Map, on page 81.
7. Added 1.8V option for VDDO_SDIO0/1 in Table 42, Recommended Operating Conditions, on page 85 and Table 50,
General 1.8V Interface (CMOS) DC Electrical Specifications, on page 98.
8. Updated the PVDD_CPU Power values in Table 43, CPU Subsystem Power Dissipation, on page 88.
9. Updated the PVDD_CPU Power values and added 3D graphic application measurements to Table 44, SoC Core Power
Dissipation, on page 89.
10. In Table 45, I/O Interfaces Power Dissipation, on page 89:
• Revised the PCI Express and USB interfaces values.
• Added new RGMII power dissipation values for 2.5V and 3.3V.
11. Updated the Idle mode CPU power value in Table 46, SoC Power Dissipation for Low Power Modes, on page 93.
12. In Table 47, Maximum Current Consumption, on page 94:
• Updated the CPU and SoC core maximum current consumption values.
• Added new RGMII 3.3V and SDRAM DDR3 (533 MHz) values.
13. Added support for RGMII 1000 Mbps in Section 9.5.1, General 3.3V (CMOS) DC Electrical Specifications, on page 96
and Section 9.5.2, General 2.5V (CMOS) DC Electrical Specifications, on page 97.
14. In Table 59, Reference Clock and Reset AC Timing Specifications, on page 105:
• Added information for the LCD output clock at 2.5/3.3V output frequencies.
• Added the following notes:
The load is CL = 15 pF.
Slew rate is defined from 20% to 80% of the reference clock signal.
15. Updated all skew values and tIS/tIH values in Table 62, NAND Flash AC Timing Table, on page 112.
16. Changed Table 73, SPI (Master Mode) AC Timing Table, on page 129 to the correct SCLK rising and falling edge
measurements.
17. Revised Table 79, LCD AC Timing Table, on page 139.
• Changed tOIV value from max 2.5 to +/- 1.25.
• General comment: All values were measured from vddio/2 to vddio/2, unless otherwise specified.
18. Updated Figure 50, LCD Transmit AC Timing Diagram, on page 140.
Copyright © 2011 Marvell
July 13, 2011, Preliminary
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88AP510
Hardware Specifications
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Changed numerous values to a function of tCK in:
Table 81, SSP Clock Master Frame Master AC Timing Table, on page 143
Table 82, SSP Clock Master Frame Slave AC Timing Table, on page 144
Table 83, SSP Clock Slave Frame Master AC Timing Table, on page 144
Table 84, SSP Slave Frame Slave AC Timing Table, on page 145
20. Added the following note to all of the tables in Section 9.7.3, SATA Interface Electrical Characteristics, on page 151:
NOTE: The value is informative only, and it can be achieved by using a proper board layout. Refer to the hardware
design guidelines for more information.
Rev. B
November 9, 2009
Revised Release
1. Changed product number to 88AP510.
2. Added write leveling support for DDR3 to the DDR Controller features list on page 10.
3. Changed CPU to L2 clock ratios to 1:N under the L2 Cache features on page 10.
4. Updated the SDIO features in the Secure Digital Input/Output (SDIO) Card Controller list on page 13.
5. In Table 5, DDR SDRAM Interface Pin Assignments, on page 30
• Added a note to the M_RESETn pin that a pull-up is required for DDR3.
• Added to the M_CKE[1:0] description that the pins must be pulled down through a 10 kΩ to 100 kΩ resistor to support
Standby mode.
6. In Table 10, LCD Serial Peripheral Interface Pin Assignments, on page 36
• Added pull-up and pull-down information for SPI_2_MOSI and SPI_2_SCK in.
• Updated the table with new power rail and MPP information.
7. Revised Table 25, Power Management Unit Interface, on page 50 by adding the PMU_ prefix, updating MPP power rail
information, and descriptions.
8. Added in the VDD_CORE description in Table 28, Power Supply Pin Assignments, on page 53 that it also applies to
the VMeta™ and GPU.
9. Added Table 2.4, Pin State During Reset, on page 58.
10. Added Figure 6.2, Clock Topology, on page 71.
11. Revised Section 7.1.1, Power Up Sequence Requirements, on page 72 and Section 7.1.2, Resume Power Up
Sequence from Standby Mode, on page 74. This includes information about which power supplies must be powered
down when the SoC core voltage is powered down, and which PHY AVDD voltages can be powered up while the core
voltages are powered down. There is also a new version of Figure 6, Power Up Sequence, on page 73.
12. Added EEMBC 1.1 Benchmark Suite and Mplayer (Full HD) 1G power values to Table 43, CPU Subsystem Power
Dissipation, on page 88.
13. Changed the PCI Express power dissipation values in Table 45, I/O Interfaces Power Dissipation, on page 89.
14. Made the following changes in Table 46, SoC Power Dissipation for Low Power Modes, on page 93:
• The Deep Idle mode DDR I/O power is 0 mW.
• The Hibernate mode PMU power is 2.5 µW.
15. In Table 47, Maximum Current Consumption, on page 94
• Revised the CPU, RGMII, and PCI Express values
• Changed the DDR2 SDRAM interface to 1000 mA max, and added DDR3 SDRAM interface consumption values.
16. Added Camera interface duty cycle and slew rate parameters to Table 59, Reference Clock and Reset AC Timing
Specifications, on page 105.
17. Added Figure 10, I2SMCLK/CAM_PIXMCLK/SYSCLK_OUT Reference Clock Test Circuit, on page 107 and Figure 11,
I2SMCLK/CAM_PIXMCLK/SYSCLK_OUT AC Timing Diagram, on page 107.
18. Added Table 9.6.2.2, RGMII Test Circuit, on page 108.
19. Revised Table 73, SPI (Master Mode) AC Timing Table, on page 129.
20. Added the following note to the tables in Section 9.6.17, Synchronous Serial Port (SSP) Interface AC Timing,
on page 143:
NOTE: Defined from 10% to 90% of the signal.
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21. Added the parameter dTRrefclk in Table 85, PCI Express Interface Differential Reference Clock Characteristics, on
page 147.
22. Added 1 GHz part ordering number to Table 94, 88AP510 Part Order Options, on page 161.
Rev. A
July 12, 2009
Initial Release
Copyright © 2011 Marvell
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88AP510
Hardware Specifications
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88AP510
High-Performance SoC with Integrated CPU, 2D/3D
Graphics Processor, and High-Definition Video Decoder
Hardware Specifications
PRODUCT OVERVIEW
The Marvell® 88AP510 is a high performance, highly integrated, low-power SoC with a high-end ARM-compliant
processor, graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of
peripherals.
88AP510 Block Diagram
VGA
16/32-bit
DDR2/3
SheevaTM
CPU
ARMv6/v7
32-KB L1
I-Cache
FPU
V3.0
32-KB L1
D-Cache
WMMX
2
Display
Controller
SPI + PWM
RTC
512 KB L2 Cache
Camera
BootROM
TWSI
8/16-bit
NAND Flash
GPU
2D/3D Graphics
2 Ports
SPI
VMeta™
HD Video Decoder
H264, VC-1,
MPEG2
Audio
AC ‘97/I2S
Audio
I2S / S/PDIF
2 Ports
4 Ports
SPDIF
SDIO
SSP
3 Ports
I2S
Cryptographic
Engine and
Security
Accelerator
AES, DES, 3DES,
SHA-1, MD5
GbE MAC
(RGMII)
Two XOR/DMA
Engines and PDMA
USB 2.0 HS
2 ports
PCIe x1
2 Ports
TWSI
UART
Power Management Unit
SATA 2.0
GPIO
Copyright © 2011 Marvell
July 13, 2011, Preliminary
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88AP510
Hardware Specifications
FEATURES
• High performance dual issue ARMv6/v7 compliant
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CPU
Integrated Floating Point Unit (FPU)
512 KB of L2 Cache
Tightly coupled 32-bit DDR controller: DDR2,
DDR3
Advanced Power Management
Integrated 2D/3D Graphics Processing Unit (GPU),
with up to 10 MTriangle/Sec
Integrated Hi-definition Multi-format Video Decode
Unit
VGA-out port
Two audio controllers
Two PCI Express (PCIe) 1.1 x1 ports, with
integrated PHY
Two USB 2.0 ports with integrated PHYs
Single Gigabit Ethernet MAC controller
Single SATA 2.0 port with integrated SATA II PHY
Cryptographic engine
Two XOR/DMA engines
Three SPI controllers
8-bit or 16-bit NAND Flash controller
Two Secure Digital (SD)/SDIO controllers
Camera interface (2 MPixel)
Four UART ports
Four TWSI ports
72 Multi-Purpose Pins (MPP)
Interrupt controller
Timers
Integrated Real Time Clock (RTC)
JTAG port
Synchronous Serial Port (SSP) suitable for GPS
support
Sheeva™ CPU
• Superscalar, dual issue CPU
• ARMv6/v7 architecture
• Single precision and double precision FPU
Version 3 support
• WMMX2 Multimedia Coprocessor
• 32-bit and 16-bit RISC architecture
• 16-bit Thumb instruction set for code density
• Supports DSP instructions to boost performance
for signal processing applications
• Includes MMU to support virtual memory features
• 32-KB L1 I-Cache and 32-KB L1 D-Cache
• Physical tagged L1 Cache
• Variable pipeline stages—seven to ten stages
• Out-of-order execution for increased performance
• In-order retire via a Re-ordering Buffer (ROB)
• Branch Prediction
• JTAG/ARM-compatible ICE
• Little, Big and Mixed Endian memory formats
• Dynamic clock gating to save power when not
actively used
• Performance monitor counters
„
L2 Cache
• 512 KB of L2 Cache
• Physical mapping mode
• Write-Back and Write-Through schemes
• 8-way set associativity
• 1:N CPU to L2 clock ratios
• Sub-blocking prefetch support
• Clean and clean-invalidate range operation
• Pseudo-random replacement
• ECC error protection
• Instruction and Data way lockdown mechanism
• Power Saving modes
• Performance monitor counters
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DDR Controller
• DDR2 support up to DDR 800 (400 MHz clock rate)
• DDR3 support up to DDR 1066 (533 MHz clock
rate)
• 1.5V or 1.8V I/O supply for DDR2
• 1.5V or 1.35V I/O support for DDR3
• Write leveling support for DDR3
• 32-bit and 16-bit bus widths
• Two Chip Selects (CS)
• Supports up to 2 Gb devices
• Maximum of eight banks per CS to support bank
interleave operation
• DRAM self-refresh support
• Programmable pad calibration and driving strength
control
• Open pages support
• Auto pre-charge support
„
Graphics Processing Unit (GPU)
• Fully featured 3D pipeline
- Unified vertex and pixel/ fragment shader
- Full support for OpenGL ES 2.0 shading
language
- Transform, lighting and fixed function texture
blending features of OpenGL ES 1.1
- Complete floating point pipeline that generates
high quality images
- High quality anti-aliasing with one quarter the
memory and processing
- High Dynamic Range (HDR) texture operation;
support for eight simultaneous textures
- Point-sample, bi-linear, tri-linear and cubic
textures
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FEATURES
• Fully featured 2D pipeline
- Bit, stretch, and pattern BLITs
- Fast clear
- Rectangle fill and line primitives
- Mono-expansion for text rendering
- Alpha blending
- 90 degree rotation
- Maximum frame size of 32K x 32K pixels
- Clipping window
• Video Post Processing
- High quality image scaling using 9-tap filter
- Color space conversion
- Alpha blending/hardware overlay for up to eight
• Dedicated DMA for data movement between
memory and port
• Dual display with independent frame buffers
• SPI controller supports display control
• PWM control
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Audio Controller
• I2S, Sony/Philips Digital Interface (S/PDIF), and
Audio Codec ‘97 (AC ’97) support
• Two independent audio ports:
- Port 1 can be configured as either I2S or AC ‘97
- Port 2 can be configured as either I2S or S/PDIF
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planes/surfaces
• Performance
- 10 million polygons per second
- 200 million pixels per second in depth only mode
- 100 million pixels per second in texture/ color
I2S specific features
• I2S playback and recording support
• Sample rates of 44.1/48/96 kHz
• I2S input and I2S output operate at the same
sample rate
• 16/24-bit depths
• I2S in and I2S out support independent bit depths
and depth mode
• API and driver support
- OpenGL ES 1.1 and 2.0
- OpenVG 1.1
(16/24-bit)
• Supports plain I2S, right justified, and left justified
formats
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Video Decode Engine
• Supports a single high-definition (HD) stream, or up
to four simultaneous standard definition streams
• HD content resolution up to 1080p at 30 frames per
second
• Supported formats:
- H.264 MP/[email protected]
- VC-1 MP@HL, AP@L3
- MPEG-1/2 MP@ML/HL
- DivX compliant (MPEG4 ASP without GMC)
• Low host CPU overhead per bit-stream
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Display Controller
• TFT panel support
• Video Graphics Array (VGA) out support with
integrated DACs
• HD 1080p maximum resolution
• Parallel interface up to 24-bit RGB
• YCbCr to RGB conversion
• YCbCr 4:4:4, 4:2:2, 4:2:0 input support.
• Color management: brightness, contrast, hue
• Up-scaling and down-scaling support
• Linear horizontal and vertical up-scaling
• Horizontal and vertical mirroring options
• 90 or 270 degree full screen rotation
• Three overlay layers—video, graphics, and cursor
NOTE: Supports hardware cursor with up to
24-bpp RGB and alpha blending.
• Color palette—three 256 entries (2, 4, 8 bpp) for
video and graphics overlay channels
• Alpha blending support for color panels
„
AC ‘97 Version 2.3 features
• AC ’97 playback and recording support
• Multiple codec support
• Independent channels for:
- Stereo PCM in
- Stereo PCM out
- Surround PCM out
- Center/LFE PCM out
- MODEM out
- MODEM-in
- Mono Mic-in
• 16-bit sample support
• Multiple sample rate (48 kHz and lower).
• Supports one primary codec and up to three
secondary codecs
• Optional AC97_SYSCLK output (support for
codecs without oscillators or crystals)
„
Sony/Philips Digital Interface (S/PDIF) Specific
Features
• Compliant to 60958-1, 60958-3, and IEC61937
specifications
• S/PDIF playback support
• Sample rates of 44.1/48/96 kHz
• 16/20/24-bit depths
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PCI Express (PCIe) 1.1 Ports with Integrated PHY
• PCI Express Base Specification 1.1 compatible
• Integrated low power SERDES PHY
• Root Complex or Endpoint port support
• Can also be configured as an Endpoint port
• Two x1 PCIe ports
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July 13, 2011, Preliminary
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Hardware Specifications
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2.5 GHz/s signalling
Generates PCIe clock out (100 MHz)
Lane polarity reversal support
Maximum payload size of 128 Bytes
Single Virtual Channel (VC-0)
Replay buffer support
Extended PCI Express configuration space
Advanced Error Reporting (AER) support
Power management support
Interrupt emulation message support
Error message support
PCI Express master specific features
- Single outstanding read transaction
- Maximum read request of up to 128 bytes
- Maximum write request of up to 128 bytes
- Up to four outstanding read transactions in
Endpoint mode
• PCI Express target specific features
- Supports up to eight read request transactions
- Maximum read request of up to 4 KB
- Maximum write request of up to 128 bytes
- Supports PCI Express access to all of the
device’s internal registers
„
USB 2.0 Port with Integrated PHY
• Serves as a host or peripheral port
• USB 2.0 compliant
• Integrated USB 2.0 PHY
• EHCI compatible as a host
• As a host, supports direct connection to all
peripheral types (LS, FS, HS)
• As a peripheral, supports all host types (HS, FS)
and hubs
• Up to four independent Endpoints supporting
control, interrupt, bulk, and isochronous data
transfers
• Suspend and resume mode support
• Dedicated DMA for data movement between
memory and port
„
Gigabit MAC Controller
• Supports 10/100/1000 Mbps MACs
• RGMII support
• Dedicated DMA for data movement between
memory and port
• Priority queuing on receive, based on DA, VLAN
Tag, and IP TOS
• Layer 2/3/4 frame encapsulation detection
• TCP/IP checksum on receive and transmit
• DA address filtering
„
SATA II Interface
• Integrates Marvell® 3 Gbps SATA PHY
• Compliant with SATA II specifications
•
•
•
•
•
•
•
•
•
•
Supports SATA II Native Command Queuing (NCQ)
Support eSATA
Supports ATAPI devices
Backwards compatible with SATA I devices
Supports device 48-bit addressing
Enhanced-DMA (EDMA) for data transfer to and
from memory
Automatic command execution without host
intervention
Advanced drive diagnostics via the ATA SMART
command
FIS-based switching
Port multiplier support
„
Cryptographic Engine
• Hardware implementation of encryption and
authentication engines to boost packet processing
speed
• Implements AES, DES, and 3DES encryption
algorithms
• Implements SHA1 and MD5 authentication
algorithms
• Dedicated DMA for data movement between either
internal SRAM memory or DDR memory and the
engines
„
XOR DMA Engines
• Two XOR/DMA Engines for a total of four high
performance DMA channels
• Supports XOR operation for up to eight source
blocks
• Useful for application acceleration:
- RAID XOR offload
- Memcpy / memset acceleration
- Copy to/from user space
• Supports iSCSI CRC-32 calculation
„
SPI Controller
• Two SPI controllers (SPI0, SPI1)
• Direct boot from external SPI on SPI0 port
• Supports timing mode CPOL=CPHA=0
„
NAND Flash Controller
• Supports 8/16-bit wide NAND flash devices
• Ganged mode: Two 8-bit wide identical flash
devices used in parallel to support 16-bit wide
operation
• Support for small and large page sizes
• 3 to 7 address cycles
• Four Chip Selects (CEn)
• Ready/Busy counters for wear leveling
• Boot from NAND
• Hardware ECC
- Small page: Single bit error correction and two
bit error detection per page using hamming
Doc. No. MV-S105141-U0 Rev. F
Page 12
Copyright © 2011 Marvell
Document Classification: Proprietary Information
July 13, 2011, Preliminary
FEATURES
- Large page: 4-bit error correction per 512 Bytes
„
using BCH
Secure Digital Input/Output (SDIO) Card
Controller
• 1-bit/4-bit SDmem, SDIO, and MMC cards
• Up to 50 MHz (SD PHY rev. 1.1 High Speed)
• Support SDHC (SD PHY rev. 2.0)
• Supports interrupts for information exchange
between host and cards
• Supports read wait commands
• Hardware generate/check CRC on all command
and data transaction on card bus
• Supports DMA and PIO operations
• Suspend and Resume support for SDIO cards
„
Camera Interface
• ITU BT-656 compliant
• High-resolution CMOS camera interface
• Up to 50 MHz pixel clock
• Up to 2.0 megapixels still images
• Standard 8-bit camera interface with
HSYNC/VSYNC
• Embedded HSYNC/VSYNC format support
• Both RGB and YUV format support
• Capture modes
- RGB 4:4:4, 5:5:5, 5:6:5
- YCbCr 4:2:2
- Raw capture mode: Bayer
• Output formats
- RGB 16-bit/pixel (4:4:4, 5:5:5, 5:6:5)
- YCbCr 4:2:2 (planar or packed format)
- YCbCr 4:2:0 (only planar format)
- Raw Bayer packed: 8-bit/pixel
• 2x downscale on RGB and YCbCr output formats
• DMA pixel data transfer
• Programmable pixel clock
• TWSI controller
„
UART Ports
• 16550 UART compatible
• Four UART ports
• Support for boot from UART0 via internal BootROM
„
TWSI Controller
• TWSI0 controller support Master/slave operation
• Running up to 100 kHz
• Up to three TWSI interfaces supported through an
internal port expander
• Supports DDC2 monitor interface for Extended
Display Identification Data (EDID)
„
Multi-Purpose Pins
• 72 MPPs configurable as functional or GPIO.
• GPIO inputs can be used to register interrupts from
external devices and to generate maskable
interrupts
„
Advanced Interrupt Controller
• Maskable interrupts to the Sheeva™ CPU core
„
Timers
• Two general purpose 32-bit timers/counters
• One 32-bit watchdog timer
„
Integrated Real Time Clock (RTC)
JTAG Port
Advanced Power Management
• Power Management Unit (PMU) controlling device
power modes
• Six device level power modes
- Run―Includes CPU dynamic frequency and
dynamic voltage control
- Idle―CPU wait for interrupt
- eBook (LCD on)
- Deep Idle (LCD off)
- Standby (DRAM in self refresh)
- Hibernate (Suspend to disk)
• Separate power islands for CPU, GPU, VMeta™,
SoC core logic, PMU, and the various IO PHYs
• On-die Temperature Detector support
• PCI Express power modes
- Software controlled D1, D2, D3hot, or D3cold
states
- Hardware controlled Active-State Power
Management—L0s and L1
- PHY power-down
• SATA Power modes
- Slumber mode support
- Partial state mode support
- PHY power down
• DDR Power modes
- Self-Refresh mode
- Dynamic frequency scaling
• USB Power modes
- PHY power-down modes
- Suspend/Resume
• Remote wake-up
• Clock gating control for various interfaces and
engines
• IO power control for various interfaces
568-pin HSBGA package, 27 x 27 mm, 1 mm pitch
„
„
„
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
Document Classification: Proprietary Information
Page 13
88AP510
Hardware Specifications
88AP510 Based Smartbook System Example
88AP510
DDR2/3
(up to 2 GB)
DDR2/3
NAND
(up to 32
GB)
NAND Flash
VGA
Display
SPI
SD Card
External
Display
SDIO
LCD Panel
Touch Screen
Controller
Camera
Camera
Marvell WiFi
b/g + BT
Marvell
3.5G/
WiMAX
SDIO
Microphone
Audio
Audio
Codec
Speaker
USB 2.0 HS
Headset
USB (external)
PCI Express
USB 2.0 HS
USB
Hub
USB (external)
Mouse
GPS RF
SSP + SPI
Power Management
Unit
Keyboard
Power Topology
Battery
Doc. No. MV-S105141-U0 Rev. F
Page 14
Copyright © 2011 Marvell
Document Classification: Proprietary Information
July 13, 2011, Preliminary
Table of Contents
Table of Contents
Revision History ....................................................................................................................................... 3
Preface ..................................................................................................................................................... 22
1
Overview ..................................................................................................................................... 24
2
Pin Information .......................................................................................................................... 25
2.1
Pin Logic ....................................................................................................................................................... 26
2.2
Pin Descriptions ............................................................................................................................................ 27
2.3
Internal Pull-up and Pull-down Pins .............................................................................................................. 55
2.4
Pin State During Reset .................................................................................................................................. 58
3
Unused Interface Strapping ...................................................................................................... 59
4
88AP510 Pin Map and Pin List ................................................................................................. 60
5
Multi Purpose and General Purpose Pins Functionality ........................................................ 61
5.1
MPP[71:0] Multiplexing Options .................................................................................................................... 61
5.2
Power Management Unit Multiplexing ........................................................................................................... 63
5.3
LCD Multiplexing Options .............................................................................................................................. 64
5.4
Audio and SSP I/O Multiplexing Options ....................................................................................................... 66
6
Clocking ..................................................................................................................................... 69
6.1
Spread Spectrum Clock Generator (SSCG) .................................................................................................. 70
6.2
Clock Topology ............................................................................................................................................. 71
7
System Power Up/Down and Reset Settings .......................................................................... 72
7.1
Power Sequencing ........................................................................................................................................ 72
7.2
Hardware Reset ............................................................................................................................................ 75
7.3
PCI Express Reset ........................................................................................................................................ 76
7.4
Sheeva™ CPU TAP Controller Reset ............................................................................................................ 76
7.5
Pins Sample Configuration ............................................................................................................................ 76
7.6
Serial ROM Initialization ................................................................................................................................ 77
8
JTAG Interface ........................................................................................................................... 80
8.1
TAP Controller ............................................................................................................................................... 80
8.2
Instruction Register ....................................................................................................................................... 80
8.3
Bypass Register ............................................................................................................................................ 81
8.4
JTAG Scan Chain ......................................................................................................................................... 81
8.5
ID Register .................................................................................................................................................... 81
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
Document Classification: Proprietary Information
Page 15
88AP510
Hardware Specifications
9
Electrical Specifications (Preliminary) .................................................................................... 82
9.1
Absolute Maximum Ratings .......................................................................................................................... 82
9.2
Recommended Operating Conditions ........................................................................................................... 85
9.3
Thermal Power Dissipation ........................................................................................................................... 88
9.4
Maximum Current Consumption .................................................................................................................... 94
9.5
DC Electrical Specifications .......................................................................................................................... 96
9.6
AC Electrical Specifications ........................................................................................................................ 105
9.7
Differential Interface Electrical Characteristics ............................................................................................ 147
10
Thermal Data ............................................................................................................................ 158
11
Package Mechanical Dimensions (Preliminary) ................................................................... 159
12
Part Order Numbering/Package Marking .............................................................................. 161
12.1
Part Order Numbering ................................................................................................................................. 161
12.2
Package Marking ........................................................................................................................................ 162
Doc. No. MV-S105141-U0 Rev. F
Page 16
Copyright © 2011 Marvell
Document Classification: Proprietary Information
July 13, 2011, Preliminary
List of Tables
List of Tables
Revision History ....................................................................................................................................... 3
Table 1:
Revision History ................................................................................................................................ 3
Preface ..................................................................................................................................................... 22
1
Overview .......................................................................................................................................... 24
2
Pin Information ............................................................................................................................... 25
3
Table 2:
Pin Functions and Assignments Table Key .................................................................................... 27
Table 3:
Interface Pin Prefixes ...................................................................................................................... 27
Table 4:
Gigabit Ethernet Controller Pin Assignments ................................................................................ 29
Table 5:
DDR SDRAM Interface Pin Assignments ....................................................................................... 30
Table 6:
Audio Port0 (I2S/AC ‘97) Controller Pin Assignments .................................................................... 32
Table 7:
Audio Port1 (I2S / S/PDIF) Controller Pin Assignments ................................................................. 32
Table 8:
SDIO Interface Pin Assignments ................................................................................................... 34
Table 9:
Serial Peripheral Interface (SPI) Interface Pin Assignments .......................................................... 35
Table 10:
LCD Serial Peripheral Interface Pin Assignments .......................................................................... 36
Table 11:
TWSI Interface Pin Assignments .................................................................................................... 37
Table 12:
Camera TWSI Interface Pin Assignments ...................................................................................... 37
Table 13:
Camera Interface Pin Assignments ............................................................................................... 38
Table 14:
JTAG Pin Assignments .................................................................................................................. 39
Table 15:
PCI Express Port 0/1 Interface Pin Assignments ........................................................................... 40
Table 16:
SATA II Interface Pin Assignments ................................................................................................ 41
Table 17:
USB 2.0 Interface Pin Assignments ............................................................................................... 42
Table 18:
MPP Pin Assignments .................................................................................................................... 43
Table 19:
LCD Dumb Panel Pin Assignments ................................................................................................ 44
Table 20:
VGA Channel Controller Pin Assignments ..................................................................................... 45
Table 21:
NAND Flash Interface Pin Assignments ........................................................................................ 46
Table 22:
UART Interface Pin Assignments .................................................................................................. 47
Table 23:
SSP Interface Pin Assignments Option 1 ....................................................................................... 48
Table 24:
SSP Interface Pin Assignments Option 2 ....................................................................................... 49
Table 25:
Power Management Unit Interface ................................................................................................. 50
Table 26:
Miscellaneous Pin Assignments ..................................................................................................... 51
Table 27:
Reserved Pin Assignments ............................................................................................................. 52
Table 28:
Power Supply Pin Assignments ...................................................................................................... 53
Table 29:
Internal Pull-up and Pull-down Pins ................................................................................................ 55
Table 30:
Pin State During Reset ................................................................................................................... 58
Unused Interface Strapping ........................................................................................................... 59
Table 31:
4
Unused Interface Strapping ............................................................................................................ 59
88AP510 Pin Map and Pin List ....................................................................................................... 60
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
Document Classification: Proprietary Information
Page 17
88AP510
Hardware Specifications
5
6
7
8
9
Multi Purpose and General Purpose Pins Functionality ............................................................. 61
Table 32:
LCD IO Pin [27:0] Allocation ........................................................................................................... 64
Table 33:
LCD Color Resolution per Mode ..................................................................................................... 65
Table 34:
Peripheral Cross-Configuration Options ......................................................................................... 67
Clocking ........................................................................................................................................... 69
Table 35:
88AP510 Clocks ............................................................................................................................. 69
Table 36:
Supported Clock Combinations ...................................................................................................... 70
System Power Up/Down and Reset Settings ............................................................................... 72
Table 37:
I/O, Analog, and Core Voltages ...................................................................................................... 73
Table 38:
88AP510 Power Modes .................................................................................................................. 75
JTAG Interface ................................................................................................................................ 80
Table 39:
Supported JTAG Instructions .......................................................................................................... 80
Table 40:
IDCODE Register Map ................................................................................................................... 81
Electrical Specifications (Preliminary) ......................................................................................... 82
Table 41:
Absolute Maximum Ratings ............................................................................................................ 82
Table 42:
Recommended Operating Conditions ............................................................................................. 85
Table 43:
CPU Subsystem Power Dissipation ................................................................................................ 88
Table 44:
SoC Core Power Dissipation .......................................................................................................... 89
Table 45:
I/O Interfaces Power Dissipation .................................................................................................... 89
Table 46:
SoC Power Dissipation for Low Power Modes ............................................................................... 93
Table 47:
Maximum Current Consumption ..................................................................................................... 94
Table 48:
General 3.3V Interface (CMOS) DC Electrical Specifications ......................................................... 96
Table 49:
General 2.5V Interface (CMOS) DC Electrical Specifications ......................................................... 97
Table 50:
General 1.8V Interface (CMOS) DC Electrical Specifications ......................................................... 98
Table 51:
SDRAM DDR2 1.5V Interface DC Electrical Specifications ............................................................ 99
Table 52:
SDRAM DDR2 1.8V Interface DC Electrical Specifications .......................................................... 100
Table 53:
SDRAM DDR3 1.35V Interface DC Electrical Specifications ........................................................ 101
Table 54:
SDRAM DDR3 1.5V Interface DC Electrical Specifications .......................................................... 102
Table 55:
TWSI Interface 3.3V DC Electrical Specifications ......................................................................... 103
Table 56:
SPI Interface 3.3V DC Electrical Specifications ............................................................................ 103
Table 57:
NAND Flash 3.3V DC Electrical Specification .............................................................................. 104
Table 58:
NAND Flash 1.8V DC Electrical Specification .............................................................................. 104
Table 59:
Reference Clock and Reset AC Timing Specifications ................................................................. 105
Table 60:
RGMII 10/100/1000 Mbps AC Timing Table ................................................................................. 108
Table 61:
SMI Master Mode AC Timing Table .............................................................................................. 110
Table 62:
NAND Flash AC Timing Table ...................................................................................................... 112
Table 63:
SDRAM DDR2 400 MHz 1.8V Interface AC Timing Table ........................................................... 114
Table 64:
SDRAM DDR2 400 MHz 1.5V Interface AC Timing Table ........................................................... 115
Table 65:
SDRAM DDR2 400 MHz Clock Specifications .............................................................................. 116
Table 66:
SDRAM DDR3 1.5V Interface AC Timing Table ........................................................................... 119
Table 67:
SDRAM DDR3 1.35V Interface AC Timing Table ......................................................................... 120
Table 68:
SDRAM DDR3 Clock Specifications ............................................................................................. 121
Doc. No. MV-S105141-U0 Rev. F
Page 18
Copyright © 2011 Marvell
Document Classification: Proprietary Information
July 13, 2011, Preliminary
List of Tables
10
Table 69:
SDRAM DDR2/3 Derating Values Table ...................................................................................... 122
Table 70:
Inter-IC Sound (I2S) AC Timing Table .......................................................................................... 124
Table 71:
SDIO Host in High Speed Mode AC Timing Table ....................................................................... 126
Table 72:
S/PDIF AC Timing Table .............................................................................................................. 128
Table 73:
SPI (Master Mode) AC Timing Table ............................................................................................ 129
Table 74:
TWSI Master AC Timing Table ..................................................................................................... 131
Table 75:
TWSI Slave AC Timing Table ....................................................................................................... 131
Table 76:
JTAG Interface AC Timing Table .................................................................................................. 133
Table 77:
AC-Link AC Timing Table ............................................................................................................. 135
Table 78:
Camera AC Timing Table ............................................................................................................. 137
Table 79:
LCD AC Timing Table ................................................................................................................... 139
Table 80:
VGA AC Timing Table .................................................................................................................. 141
Table 81:
SSP Clock Master Frame Master AC Timing Table ...................................................................... 143
Table 82:
SSP Clock Master Frame Slave AC Timing Table ........................................................................ 144
Table 83:
SSP Clock Slave Frame Master AC Timing Table ........................................................................ 144
Table 84:
SSP Slave Frame Slave AC Timing Table ................................................................................... 145
Table 85:
PCI Express Interface Differential Reference Clock Characteristics ............................................ 147
Table 86:
PCI Express Interface Spread Spectrum Requirements ............................................................... 148
Table 87:
PCI Express Interface Driver and Receiver Characteristics ......................................................... 149
Table 88:
SATA I Interface Gen1m Mode Driver and Receiver Characteristics ........................................... 152
Table 89:
SATA II Interface Gen2 Mode Driver and Receiver Characteristics ............................................. 153
Table 90:
USB Low Speed Driver and Receiver Characteristics .................................................................. 154
Table 91:
USB Full Speed Driver and Receiver Characteristics ................................................................... 155
Table 92:
USB High Speed Driver and Receiver Characteristics ................................................................. 156
Thermal Data ................................................................................................................................. 158
Table 93:
11
12
Thermal Data for the 88AP510 in (Package Type) Package ........................................................ 158
Package Mechanical Dimensions (Preliminary) ........................................................................ 159
Part Order Numbering/Package Marking .................................................................................... 161
Table 94:
88AP510 Part Order Options ........................................................................................................ 161
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
Document Classification: Proprietary Information
Page 19
88AP510
Hardware Specifications
List of Figures
1
Overview .......................................................................................................................................... 24
2
Pin Information ............................................................................................................................... 25
Figure 1:
88AP510 Pin Logic Diagram ........................................................................................................... 26
3
Unused Interface Strapping ........................................................................................................... 59
4
88AP510 Pin Map and Pin List ....................................................................................................... 60
5
Multi Purpose and General Purpose Pins Functionality ............................................................. 61
6
Figure 2:
Multi Purpose Pins [23:0] Selection Scheme .................................................................................. 62
Figure 3:
Multi Purpose Pins [71:24] Selection Scheme ................................................................................ 63
Figure 4:
Peripheral Multiplexing ................................................................................................................... 67
Clocking ........................................................................................................................................... 69
Figure 5:
7
Device Clock Topology ................................................................................................................... 71
System Power Up/Down and Reset Settings ............................................................................... 72
Figure 6:
Power Up Sequence ....................................................................................................................... 73
Figure 7:
Serial ROM Data Structure ............................................................................................................. 78
Figure 8:
Serial ROM Read Example ............................................................................................................. 79
8
JTAG Interface ................................................................................................................................ 80
9
Electrical Specifications (Preliminary) ......................................................................................... 82
Figure 9:
88AP510 Power Domains ............................................................................................................... 92
Figure 10:
I2SMCLK/CAM_PIXMCLK/SYSCLK_OUT Reference Clock Test Circuit .................................... 107
Figure 11:
I2SMCLK/CAM_PIXMCLK/SYSCLK_OUT AC Timing Diagram ................................................... 107
Figure 12:
RGMII Test Circuit ........................................................................................................................ 108
Figure 13:
RGMII AC Timing Diagram ........................................................................................................... 109
Figure 14:
MDIO Master Mode Test Circuit ................................................................................................... 110
Figure 15:
MDC Master Mode Test Circuit .................................................................................................... 111
Figure 16:
SMI Master Mode Output AC Timing Diagram ............................................................................. 111
Figure 17:
SMI Master Mode Input AC Timing Diagram ................................................................................ 111
Figure 18:
NAND Flash Test Circuit ............................................................................................................... 112
Figure 19:
NAND Flash Input AC Timing Diagram ......................................................................................... 113
Figure 20:
NAND Flash Output AC Timing Diagram ...................................................................................... 113
Figure 21:
SDRAM DDR2 Interface Test Circuit ............................................................................................ 117
Figure 22:
SDRAM DDR2 Interface Write AC Timing Diagram ..................................................................... 117
Figure 23:
SDRAM DDR2 Interface Address and Control AC Timing Diagram ............................................. 118
Figure 24:
SDRAM DDR2 Interface Read AC Timing Diagram ..................................................................... 118
Figure 25:
SDRAM DDR3 Interface Test Circuit ............................................................................................ 122
Figure 26:
SDRAM DDR3 Interface Write AC Timing Diagram ..................................................................... 123
Doc. No. MV-S105141-U0 Rev. F
Page 20
Copyright © 2011 Marvell
Document Classification: Proprietary Information
July 13, 2011, Preliminary
List of Figures
10
11
12
Figure 27:
SDRAM DDR3 Interface Address and Control AC Timing Diagram ............................................. 123
Figure 28:
SDRAM DDR3 Interface Read AC Timing Diagram ..................................................................... 123
Figure 29:
Inter-IC Sound (I2S) Test Circuit .................................................................................................. 124
Figure 30:
Inter-IC Sound (I2S) Output Delay AC Timing Diagram ............................................................... 125
Figure 31:
Inter-IC Sound (I2S) Input AC Timing Diagram ............................................................................ 125
Figure 32:
Secure Digital Input/Output (SDIO) Test Circuit ........................................................................... 126
Figure 33:
SDIO Host in High Speed Mode Output AC Timing Diagram ....................................................... 127
Figure 34:
SDIO Host in High Speed Mode Input AC Timing Diagram .......................................................... 127
Figure 35:
S/PDIF Test Circuit ....................................................................................................................... 128
Figure 36:
SPI (Master Mode) Test Circuit .................................................................................................... 129
Figure 37:
SPI (Master Mode) AC Timing Diagram ....................................................................................... 130
Figure 38:
TWSI Test Circuit .......................................................................................................................... 132
Figure 39:
TWSI Output Delay AC Timing Diagram ....................................................................................... 132
Figure 40:
TWSI Input AC Timing Diagram ................................................................................................... 132
Figure 41:
JTAG Interface Test Circuit .......................................................................................................... 133
Figure 42:
JTAG Interface Output Delay AC Timing Diagram ....................................................................... 134
Figure 43:
JTAG Interface Input AC Timing Diagram .................................................................................... 134
Figure 44:
AC-LinkTest Circuit ....................................................................................................................... 135
Figure 45:
AC-Link Output AC Timing Diagram ............................................................................................. 136
Figure 46:
AC-Link Input AC Timing Diagram ................................................................................................ 136
Figure 47:
Camera Test Circuit ...................................................................................................................... 137
Figure 48:
Camera Input AC Timing Diagram ................................................................................................ 138
Figure 49:
LCD Test Circuit ........................................................................................................................... 139
Figure 50:
LCD Transmit AC Timing Diagram ............................................................................................... 140
Figure 51:
VGA Hsync/Vsync Test Circuit ..................................................................................................... 142
Figure 52:
VGA R/G/B Test Circuit ................................................................................................................ 142
Figure 53:
SSP Test Circuit ........................................................................................................................... 145
Figure 54:
SSP Master Data Tx AC Timing Diagram ..................................................................................... 146
Figure 55:
SSP Data Rx AC Timing Diagram ................................................................................................ 146
Figure 56:
PCI Express Interface Test Circuit ................................................................................................ 150
Figure 57:
Low/Full Speed Data Signal Rise and Fall Time .......................................................................... 156
Figure 58:
High Speed TX Eye Diagram Pattern Template ........................................................................... 157
Figure 59:
High Speed RX Eye Diagram Pattern Template ........................................................................... 157
Thermal Data ................................................................................................................................. 158
Package Mechanical Dimensions (Preliminary) ........................................................................ 159
Figure 60:
568-Pin BGA Package and Dimensions ....................................................................................... 159
Figure 61:
Package Drawing Key .................................................................................................................. 160
Part Order Numbering/Package Marking .................................................................................... 161
Figure 62:
Sample Part Number .................................................................................................................... 161
Figure 63:
Commercial Package Marking and Pin 1 Location ....................................................................... 162
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
Document Classification: Proprietary Information
Page 21
88AP510
Hardware Specifications
Preface
About this Document
This datasheet provides the hardware specifications for the Marvell® 88AP510 high-performance
SoC with integrated CPU, 2D/3D graphics processor, and high-definition video decoder device. The
hardware specifications include detailed pin information, configuration settings, electrical
characteristics and physical specifications.
The information in this document is subject to change. Contact your Marvell sales representative to
ensure that you are using the latest revision.
This datasheet is intended to be the basic source of information for designers of new systems.
Related Documentation
For the latest revision, contact a Marvell representative.
„
88AP510 Functional Specifications (Doc No. MV-S105142-U0)
„
88AP510 Design Guide (Doc No. MV-S301669-U0)
Document Conventions
The following conventions are used in this document:
Signal Range
A signal name followed by a range enclosed in brackets represents a range of logically related
signals. The first number in the range indicates the most significant bit (MSb) and the last
number indicates the least significant bit (LSb).
Active Low Signals #
An n letter at the end of a signal name indicates that the signal’s active state occurs when
voltage is low.
Example: DB_Addr[12:0]
Example: INTn
State Names
State names are indicated in italic font.
Example: linkfail
Register Naming
Conventions
Register field names are indicated by angle brackets.
Example: <RegInit>
Register field bits are enclosed in brackets.
Example: Field [1:0]
Register addresses are represented in hexadecimal format.
Example: 0x0
Reserved: The contents of the register are reserved for internal use only or for future use.
A lowercase <n> in angle brackets in a register indicates that there are multiple registers with
this name.
Example: Multicast Configuration Register<n>
Reset Values
Reset values have the following meanings:
0 = Bit clear
1 = Bit set
Doc. No. MV-S105141-U0 Rev. F
Page 22
Copyright © 2011 Marvell
Document Classification: Proprietary Information
July 13, 2011, Preliminary
Preface
Document Conventions
Abbreviations
Gb: gigabit
GB: gigabyte
Kb: kilobit
KB: kilobyte
Mb: megabit
MB: megabyte
Numbering Conventions
Unless otherwise indicated, all numbers in this document are decimal (base 10).
An 0x prefix indicates a hexadecimal number.
An 0b prefix indicates a binary number.
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
Document Classification: Proprietary Information
Page 23
88AP510
Hardware Specifications
1
Overview
The Marvell® 88AP510 integrates an ARMv6/v7-compliant, high-speed dual-issue Sheeva™ CPU
core with double precision integrated Floating Point Unit (FPU) and WMMX2 instruction set, 32-KB
L1 I-cache, 32-KB D-cache, and 512-KB L2 cache. It also includes an advanced Power
Management Unit (PMU), advanced 2D/3D graphics processing unit, high definition video decoding,
display controllers and a broad range of peripherals.
The 88AP510 supports the following interfaces:
Tightly coupled 16-bit/32-bit DDR2/3 controller
„
LCD Display controller with parallel 24-bit RGB interface
„
LCD Display controller with VGA out port
„
Two Audio interfaces supporting AC ‘97 v2.3, I2S, or S/PDIF1 protocols
„
Two PCI Express (PCIe) x1 interfaces with integrated PHYs
„
Two USB 2.0 ports with integrated PHYs
„
SATA II port with integrated PHY
„
Gigabit Ethernet (GbE) MAC
„
Two SDIO ports
„
Two SPI ports
„
8-bit/16-bit NAND Flash interface
„
Four TWSI ports
„
Four 16550-compatible UART ports
„
Synchronous Serial Protocol (SSP) controller
„
Parallel BT-656/601 camera interface
„
72 Multi-Purpose-Pins (MPPs)
„
JTAG port
„
Additionally, the 88AP510 integrates the following hardware engines and accelerators to enhance
performance:
„
2D/3D Graphic Processing Unit
„
High definition Video Decoding Unit
„
Power management supporting SoC low power states, Dynamic Frequency Scaling (DFS) and
Dynamic Voltage Scaling (DVS)
„
Cryptographic Engine and Security Accelerator
„
Two XOR DMA engines (total of 4 high performance channels)
„
16 channels of Peripheral DMA Engines
„
Two general purpose timers/counters
„
Watchdog timer
„
Interrupt controller
„
Real Time Clock with external battery backup
1. S/PDIF playback only
Doc. No. MV-S105141-U0 Rev. F
Page 24
Copyright © 2011 Marvell
Document Classification: Proprietary Information
July 13, 2011, Preliminary
Pin Information
2
Pin Information
This section provides the pin logic diagram for the 88AP510 and a detailed description of the pin
assignments and their functionality.
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
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Page 25
88AP510
Hardware Specifications
2.1
Pin Logic
Figure 1: 88AP510 Pin Logic Diagram1
PEX<n>_CLK_P/N
PEX<n>_TX_P/N
PEX<n>_RX_P/N
PCI Express
Interface
VGA Interface
PEX<n>_ISET
<n> = 0–1
USB<n>_D_P/N
<n> = 0–1
USB 2.0 Interface
S_TX_P/N
S_RX_P/N
SATA_PRESENTn
SATA_ACTn
SATA II Interface
LCD Interface
GE_TXCLK
GE_TXD[3:0]
GE_TXCTL
GE_RXD[3:0]
GE_RXCTL
GE_RXCLK
GE_MDC
GE_MDIO
Gigabit Ethernet
Controller
DDR Memory
Controller Interface
LCD_CLK
LCD_EXT_REF_CLK[1:0]
LCD_HSYNC
LCD_VSYNC
LCD_D[23:0]
M_A[15:0]
M_BA[2:0]
M_CASn
M_CKE[1:0]
M_CSn[1:0]
M_WEn
M_ODT[1:0]
M_RASn
M_CLKOUT[1:0]/M_CLKOUTn[1:0]
M_DM[3:0]
M_DQ[31:0]
M_DQS[3:0]/M_DQSn[3:0]
M_RESETn
M_CAL
JT_CLK
JT_RSTn
JT_TMS_CPU
VGA_R/G/B
VGA_HSYNC
VGA_VSYNC
VGA_REXT
JTAG Interface
JT_TMS_CORE
JT_TDO
JT_TDI
SD<n>_CLK
SDIO Interface
MPP[23:0]
RTC_XIN
RTC_XOUT
Real Time Clock
Interface
SPI_MOSI
SPI_MISO
SPI_SCK
SPI_CS
SPI Interface
TWSI Interface
Camera Interface
AU0_I2SDI_DIN
AU0_I2SBCLK_DOUT
AU0_I2SLRCLK_SYNC
AU0_I2SDO_BCLK
AU0_I2SMCLK_RSTN
AU0_SYSCLK_OUT
AU0_I2S_EXT_MCLK
AC_SDATA_IN1/2/3
AU1_I2SDI
AU1_I2SDO
AU1_I2SBCLK
AU1_I2SMCLK
AU1_I2SLRCLK
AU1_SPDIFO
AU1_I2S_EXT_MCLK
UA0_RXD
UA0_TXD
UA0_CTSn
UA0_RTSn
SD<n>_CMD
SD<n>_DATA[3:0]
<n> = 0–1
MPP Pins
TW_SDA
TW_SCK
CAM_HSYNC
CAM_VSYNC
CAM_PIXDATA[7:0]
CAM_PIXCLK
CAM_PIXMCLK
CAM_SNSR_CTL[1:0]
CAM_TW_SCK
CAM_TW_SDA
NF_IO[15:0]
NF_CEn[3:0]
Audio Controllers
NF_WEn
NAND Flash Interface
NF_REn
NF_ALE
NF_CLE
NF_RDY[1:0]
REFCLK_XIN
REFCLK_XOUT
Miscellaneous Pins
UART Interface
SYSRST_INn
SYSRST_OUTn
MRn
REFCLK_ISET
1. The SSP, UART Ports 1/2/3, PMU, SPI_1 functional units are multiplexed over MPP[23:0] pins, see Section 5, Multi
Purpose and General Purpose Pins Functionality, on page 61.
Doc. No. MV-S105141-U0 Rev. F
Page 26
Copyright © 2011 Marvell
Document Classification: Proprietary Information
July 13, 2011, Preliminary
Pin Information
Pin Descriptions
2.2
Pin Descriptions
This section details all the pins for the different interfaces providing a functional description of each
pin and pin attributes.
Table 2 defines the abbreviations and acronyms used in the pin description tables.
Table 2:
Pin Functions and Assignments Table Key
Te r m
D e fi n it io n
Analog
Analog Driver/Receiver or Power Supply
Calib
Calibration pad type
CML
Common Mode Logic
CMOS
Complementary Metal-Oxide-Semiconductor
DDR
Double Data Rate
GND
Ground Supply
HCSL
High-speed Current Steering Logic
I
Input
I/O
Input/Output
O
Output
o/d
Open Drain pin
The pin allows multiple drivers simultaneously (wire-OR connection).
A pull-up is required to sustain the inactive value.
Power
Power Supply
SSTL
Stub Series Terminated Logic
t/s
Tri-State pin
XXXn
n - Suffix represents an Active Low Signal
Table 3:
Interface Pin Prefixes
In t e r f a c e
P re fi x
Audio Controller
AU_
Camera
CAM_
DDR SDRAM
M_
Gigabit Ethernet
GE_
JTAG
JT_
LCD
LCD_
NAND Flash
NF_
PCI Express
PEX_
Secure Digital Input/Output
SD_
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July 13, 2011, Preliminary
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88AP510
Hardware Specifications
Table 3:
Interface Pin Prefixes (Continued)
In t e r f a c e
P re fi x
Serial Peripheral Interface
SPI_
SATA II
S_
Synchronous Serial Protocol
SSP_
Two Wire Serial Interface
TW_
UART
UA_
USB 2.0
USB_
Video Graphics Array
VGA_
Power Management Unit
PMU_
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Pin Information
Pin Descriptions
2.2.1
Table 4:
Gigabit Ethernet Controller Pin Assignments
Gigabit Ethernet Controller Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
GE_TXCLK
O
CMOS
VDDO_GIGA
RGMII Transmit Clock
RGMII transmit reference output clock for GE_TXD[3:0] and
GE_TXCTL.
Provides 125 MHz, 25 MHz or 2.5 MHz clock.
NOTE: This pin has an integrated pullup/pulldown resistor.
See details in Section 2.3, Internal Pull-up and
Pull-down Pins, on page 55.
GE_TXD[3:0]
t/s O
CMOS
VDDO_GIGA
RGMII Transmit Data
Contains the transmit data nibble outputs that run at double
data rate with bits [3:0] presented on the rising edge and bits
[7:4] presented on the falling edge.
NOTE: This pin has an integrated pullup/pulldown resistor.
See details in Section 2.3, Internal Pull-up and
Pull-down Pins, on page 55.
GE_TXCTL
t/s O
CMOS
VDDO_GIGA
RGMII Transmit Control
Transmit control synchronous to the GE_TXCLK output
rising/falling edge.
NOTE: This pin has an integrated pullup/pulldown resistor.
See details in Section 2.3, Internal Pull-up and
Pull-down Pins, on page 55.
GE_RXCLK
I
CMOS
VDDO_GIGA
RGMII Receive Clock
RGMII receive reference input clock for GE_RXD[3:0] and
GE_RXCTL.
The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz
reference clock derived from the received data stream.
GE_RXD[3:0]
I
CMOS
VDDO_GIGA
RGMII Receive Data
Contains the receive data nibble outputs that run at double
data rate with bits [3:0] presented on the rising edge and bits
[7:4] presented on the falling edge.
GE_RXCTL
I
CMOS
VDDO_GIGA
RGMII Receive Control
GE_RXCTL is presented on the rising edge of GE_RXCLK.
A logical derivative of GE_RXDV and GE_RXERR is
presented on the falling edge of RXCLK.
GE_MDC
O
CMOS
VDDO_GIGA
Serial Management Interface Clock
MDC is derived from TCLK divided by 128.
Provides the timing reference for the transfer of the MDIO
signal.
GE_MDIO
t/s
I/O
CMOS
VDDO_GIGA
Serial Management Interface Input/Output Data.
Used to transfer control information and status between PHY
devices and the GbE controller.
NOTE: A pullup is required.
RGMII
SMI
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88AP510
Hardware Specifications
2.2.2
Table 5:
DDR Memory Controller Interface Pin Assignments
DDR SDRAM Interface Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
M_A[15:0]
O
SSTL
VDDO_M
SDRAM Address
Driven with M_BA[2:0] during RASn and CASn cycles to
generate the SDRAM row/column address
M_BA[2:0]
O
SSTL
VDDO_M
SDRAM Bank address
Selects the bank when an ACTIVE, READ, WRITE, or
PRECHARGE command is applied.
NOTE: If the SDRAM device does not support the M_BA[2]
pin, leave it not connected.
M_CASn
O
SSTL
VDDO_M
SDRAM Column Address Select (Command Output)
M_RASn, M_CASn, and M_WEn (along with M_CS[1:0])
defines the command being entered.
M_CKE[1:0]
O
SSTL
VDDO_M
SDRAM Clock Enable
The SDRAM clock enables for chip select 0 and 1.
Driven high to enable SDRAM clock.
Driven low when setting the SDRAM to Self-refresh mode.
NOTE: To support the Standby mode, see the 88AP510
Design Guide.
M_CSn[1:0]
O
SSTL
VDDO_M
SDRAM Chip select (Command Output)
Asserted to select a specific SDRAM Physical bank.
When asserted, enables the command decoder in the
SDRAM for an SDRAM access.
M_WEn
O
SSTL
VDDO_M
SDRAM Write Enable (Command Output)
This signals is part of the SDRAM Command. It is asserted
for write operations.
M_RASn, M_CASn, and M_WEn (along with M_CS[1:0])
defines the command being entered.
M_ODT[1:0]
O
SSTL
VDDO_M
SDRAM On Die Termination control for chip select 0 and 1.
Driven high to connect the SDRAM on die termination.
Driven low to disconnect the SDRAM’s termination.
M_RASn
O
SSTL
VDDO_M
SDRAM Row Address Select (Command Output)
M_RASn, M_CASn, and M_WEn (along with M_CS[1:0])
defines the command being entered.
M_CLKOUT[1:0]
M_CLKOUTn[1:0]
O
SSTL
VDDO_M
SDRAM Differential Clock Pair
M_CLKOUT[1:0] and M_CLKOUTn[1:0] are differential clock
outputs for the DDR SDRAM.
Both clocks are identical, and are used to reduce the load on
the clock.
M_DM[3:0]
O
SSTL
VDDO_M
SDRAM Data Mask
Asserted to select the specific byte out of the 32-bit data
written to the SDRAM.
DM is sampled on both edges of DQS.
In DDR 32-bit mode:
• M_DM[0] is DM for DQ0–DQ7
• M_DM[1] is DM for DQ8–DQ15
• M_DM[2] is DM for DQ16–DQ23
• M_DM[3] is DM for DQ24–DQ31
Doc. No. MV-S105141-U0 Rev. F
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July 13, 2011, Preliminary
Pin Information
Pin Descriptions
Table 5:
DDR SDRAM Interface Pin Assignments (Continued)
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
M_DQ[31:0]
I/O
SSTL
VDDO_M
SDRAM Data Input/Output
Driven during write.
Driven by SDRAM during reads.
M_DQS[3:0]
M_DQSn[3:0]
I/O
SSTL
VDDO_M
SDRAM Data Strobe
Output with write data, input with read data.
It is used to capture data.
In DDR 32-bit mode:
• M_DQS[0] is strobe for DQ0–DQ7
• M_DQS[1] is strobe for DQ8–DQ15
• M_DQS[2] is strobe for DQ16–DQ23
• M_DQS[3] is strobe for DQ24–DQ31
NOTE: A 1 Kilohm pull-down resistor must be connected to
DQS. A 1 Kilohm pull-up resistor must be connected
to DQSn. Both resistors must be a least 500 mils
from the 88AP510. For more information, see the
88AP510 Design Guide.
Calib
VDDO_M
SDRAM interface output driver and input ODT calibration.
For DDR2, connect to VSS through a 300 ohm (1%) resistor.
For DDR3, connect to VSS through a 240 ohm (1%) resistor.
CMOS
VDDO_M
SDRAM Reset (DDR3 only)
Leave unconnected for DDR2.
NOTE: For DDR3, a pull-up is required. To support the
Standby mode, see the 88AP510 Design Guide.
M_CAL
M_RESETn
O
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July 13, 2011, Preliminary
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88AP510
Hardware Specifications
2.2.3
Table 6:
Audio Controller Pin Assignments
Audio Port0 (I2S/AC ‘97) Controller Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
AU0_I2SDI_DIN
I
CMOS
VDDO_AUD
I2S: Receiver Data In
AC ‘97: Serial audio input data, from primary codec
AU0_I2SBCLK_
DOUT
O
CMOS
VDDO_AUD
I2S: Bit clock (64 x Fs), Output
AC ‘97: Serial audio output data to codec
AU0_I2SLRCLK_
SYNC
O
CMOS
VDDO_AUD
I2S: Left/Right Clock (1 x Fs)
AC ‘97: 48-kHz frame indicator and synchronizer
NOTE: This pin has an integrated pullup/pulldown resistor.
See details in Section 2.3, Internal Pull-up and
Pull-down Pins, on page 55.
AU0_I2SDO_
BCLK
I/O
CMOS
VDDO_AUD
I2S: Transmitter Data Out
AC ‘97: 12.288 MHz bit-rate clock, Input
AU0_I2SMCLK_
RSTN
O
CMOS
VDDO_AUD
I2S: Master Clock (256 x Fs)
AC ‘97: Asynchronous, active-low codec reset
AU0_SYSCLK_
OUT
O
CMOS
VDDO_AUD
AC ‘97: System Clock Output
AU0_I2S_EXT_
MCLK
I
CMOS
VDDO_MPP
External Master Clock
NOTE: The signal is multiplexed on MPP[12].
AC_SDATA_IN
1/2/3
I
CMOS
VDDO_MPP
Serial audio input data from secondary codecs.
NOTE: AC_SDATA_IN1 is multiplexed on MPP[16].
AC_SDATA_IN2 is multiplexed on MPP[17].
AC_SDATA_IN3 is multiplexed on MPP[18].
The Audio Port1 interface pins are multiplexed on the indicated MPP pins.
Table 7:
Audio Port1 (I2S / S/PDIF) Controller Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
AU1_I2SDI
I
CMOS
VDDO_AUD
I2S: Receiver Data In
NOTE: The signal is multiplexed on MPP[52].
AU1_I2SDO
O
CMOS
VDDO_AUD
I2S: Transmitter Data Out
NOTE: The signal is multiplexed on MPP[55].
AU1_I2SBCLK
O
CMOS
VDDO_AUD
I2S: Bit Clock (64 x Fs)
NOTE: The signal is multiplexed on MPP[53].
AU1_I2SMCLK
O
CMOS
VDDO_AUD
I2S: Master Clock (256 x Fs)
NOTE: The signal is multiplexed on MPP[54].
This pin has an integrated pullup/pulldown resistor.
See details in Section 2.3, Internal Pull-up and
Pull-down Pins, on page 55.
AU1_I2SLRCLK
O
CMOS
VDDO_AUD
I2S: Left/Right Clock (1 x Fs)
NOTE: The signal is multiplexed on MPP[56].
This pin has an integrated pullup/pulldown resistor.
See details in Section 2.3, Internal Pull-up and
Pull-down Pins, on page 55.
Doc. No. MV-S105141-U0 Rev. F
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Document Classification: Proprietary Information
July 13, 2011, Preliminary
Pin Information
Pin Descriptions
Table 7:
Audio Port1 (I2S / S/PDIF) Controller Pin Assignments (Continued)
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
AU1_SPDIFO
O
CMOS
VDDO_AUD
S/PDIF: Transmitter Data Out
NOTE: The signal is multiplexed on MPP[57].
AU1_I2S_EXT_
MCLK
I
CMOS
VDDO_MPP
External Master Clock
NOTE: The signal is multiplexed on MPP[13].
Copyright © 2011 Marvell
July 13, 2011, Preliminary
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88AP510
Hardware Specifications
2.2.4
Table 8:
Secure Digital Input/Output (SDIO) Interface Pin
Assignments
SDIO Interface Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r i p t io n
SD<n>_CLK
O
CMOS
VDDO_SDIO0
VDDO_SDIO1
SDIO Clock Output
NOTE: SD0_CLK is also multiplexed on MPP[40].
SD1_CLK is multiplexed on MPP[46].
SD<n>_CMD
I/O
CMOS
VDDO_SDIO0
VDDO_SDIO1
SDIO Command
NOTE: SD0_CMD is also multiplexed on MPP[41].
SD1_CMD is multiplexed on MPP[47].
Must be pulled up through a 4.7–100 kΩ
resistor.
SD<n>_DATA[3:0]
I/O
CMOS
VDDO_SDIO0
VDDO_SDIO1
SDIO Data Line [3:0]
NOTE: SD0_DATA[3:0] are also multiplexed on
MPP[45:42].
SD1_DATA[3:0] are multiplexed on
MPP[51:48].
Must be pulled up through a 4.7–100 kΩ
resistor.
SD<n> Card
Detect
I
CMOS
SDIO Card Detection
NOTE: SDIO0 is multiplexed on MPP[0], MPP[16], and
MPP[20].
SDIO1 is multiplexed on MPP[4], MPP[12], and
MPP[20].
SD<n> Write
Protect
I
CMOS
For the MPP[n]
power rail
information, see
Table 18, MPP Pin
Assignments, on
page 43.
SD<n> LED
Control
O
CMOS
<n>=0–1
SDIO Write Protection on the SD card.
NOTE: SDIO0 is multiplexed on MPP[1], MPP[17], and
MPP[21].
SDIO1 is multiplexed on MPP[5], MPP[13], and
MPP[21].
SDIO LED Control
NOTE: SDIO0 is multiplexed on MPP[3], MPP[11], and
MPP[19].
SDIO1 is multiplexed on MPP[7], MPP[11], and
MPP[15].
Doc. No. MV-S105141-U0 Rev. F
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Pin Information
Pin Descriptions
2.2.5
Serial Peripheral Interface (SPI) Pin Assignments
The SPI interface pins are multiplexed on the indicated MPP pins.
Table 9:
Serial Peripheral Interface (SPI) Interface Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r i p t io n
SPI_MOSI
SPI_1_MOSI
O
CMOS
SPI Data Output
Data is output from the master and input to the slave.
NOTE: SPI_MOSI is multiplexed on MPP[59].
SPI_1_MOSI is multiplexed on MPP[6] or
MPP[22]
SPI_MISO
SPI_1_MISO
I
CMOS
For the MPP[n]
power rail
information, see
Table 18, MPP Pin
Assignments, on
page 43.
SPI_SCK
SPI_1_SCK
O
CMOS
SPI Clock
NOTE: SPI_SCK is multiplexed on MPP[61].
SPI_1_SCK is multiplexed on MPP[7] or
MPP[23].
SPI_CS
SPI_1_CS
O
CMOS
SPI Chip Select
NOTE: SPI_CS is multiplexed on MPP[58].
SPI_1_CS is multiplexed on MPP[5] or
MPP[21].
SPI Data Input
Data is input to the master and output from the slave.
NOTE: SPI_MISO is multiplexed on MPP[60].
SPI_1_MISO is multiplexed on MPP[4] or
MPP[20].
The LCD Serial Peripheral interface pins are multiplexed on the indicated MPP pins.
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88AP510
Hardware Specifications
Table 10: LCD Serial Peripheral Interface Pin Assignments
Pin Name
SPI_2_MOSI
I /O
O
Pi n Ty pe
Power Rail
D e s c r i p t io n
CMOS
VDDO_LCD1
LCD SPI Data Output
Data is output from the master and input to the slave.
For the MPP[n]
power rail
information2, see
Table 18, MPP Pin
Assignments, on
page 43.
NOTE: A pull-down is required.
The signal is multiplexed on LCD_D[21] or
MPP[22].
SPI_2_MISO
I
CMOS
LCD SPI Data Input
Data is input to the master and output from the slave.
NOTE: The signal is multiplexed on LCD_D[20] or
MPP[20].
SPI_2_SCK
O
CMOS
LCD SPI Clock
This signal requires a pull-up or pull-down based on
the operation mode set by the CFG_CLKINV bit[7] in
the LCD_SPU_SPI_CTRL register.
• If set to 1 (CPOH), a pull-up is required.
• If leared to 0 (CPOL), a pull-down is required.
NOTE: The signal is multiplexed on LCD_D[22] or
MPP[23].
SPI_2_CS[1:0]
O
CMOS
LCD SPI Chip Select 0/1
NOTE: SPI_2_CS0 is multiplexed on LCD_D[19] or
MPP[21].
SPI_2_CS1 is multiplexed on MPP[3] or
MPP[16].
1. If multiplexed on LCD_D[23:0], refer to pull-down/pull-up requirements in the reset strapping table.
2. If multiplexed on MPP[23:0]
Doc. No. MV-S105141-U0 Rev. F
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Pin Information
Pin Descriptions
2.2.6
TWSI and Camera TWSI Interfaces Pin Assignments
The TWSI Option2, Option3, and camera TWSI interface pins are multiplexed on the indicated MPP
pins.
Table 11: TWSI Interface Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r i p t io n
TW_SDA
o/d
I/O
CMOS
TWSI Serial Data
Address or write data driven by the TWSI master or
read response data driven by the TWSI slave.
NOTE: A pull-up is required.
The signal is also multiplexed on MPP[17] or
MPP[56].
TW_SCK
o/d
I/O
CMOS
VDDO_JTAG
For the MPP[n]
power rail
information, see
Table 18, MPP Pin
Assignments, on
page 43.
TWSI Serial Clock
Serves as output when acting as an TWSI master.
Serves as input when acting as an TWSI slave.
NOTE: A pull-up is required.
The signal is also multiplexed on MPP[19] or
MPP[57].
Table 12: Camera TWSI Interface Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r i p t io n
CAM_TW_SDA
o/d
I/O
CMOS
VDDO_CAM
Camera Serial Data
Address or write data driven by the master or read
response data driven by the slave.
NOTE: A pull-up is required.
The signal is multiplexed on MPP[37].
CAM_TW_SCK
o/d
O
CMOS
VDDO_CAM
Camera Serial Clock
Serves as output when acting as a master.
NOTE: A pull-up is required.
The signal is multiplexed on MPP[36].
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88AP510
Hardware Specifications
2.2.7
Camera Interface Pin Assignments
Table 13: Camera Interface Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
CAM_HSYNC
I
CMOS
VDDO_CAM
Horizontal Sync driven by external CMOS sensor
NOTE: The signal is also multiplexed on MPP[33].
CAM_VSYNC
I
CMOS
VDDO_CAM
Vertical Sync driven by external CMOS sensor
NOTE: The signal is also multiplexed on MPP[34].
CAM_PIXDATA
[7:0]
I
CMOS
VDDO_CAM
Pixel Data
Synchronous to PIXCLK.
NOTE: The signals are also multiplexed on MPP[31:24].
CAM_PIXCLK
I
CMOS
VDDO_CAM
Pixel Clock
NOTE: The signal is also multiplexed on MPP[35].
CAM_PIXMCLK
O
CMOS
VDDO_CAM
Pixel Master Clock
NOTE: The signal is also multiplexed on MPP[32].
CAM_SNSR_CTL
[1:0]
O
CMOS
VDDO_CAM
Sensor Control 0/1
NOTE: The signals are also multiplexed on MPP[39:38].
These pins have integrated pullup/pulldown
resistors. See details in Section 2.3, Internal Pull-up
and Pull-down Pins, on page 55.
Doc. No. MV-S105141-U0 Rev. F
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Copyright © 2011 Marvell
Document Classification: Proprietary Information
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Pin Information
Pin Descriptions
2.2.8
JTAG Interface Pin Assignments
Table 14: JTAG Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
JT_CLK
I
CMOS
VDDO_JTAG
JTAG Clock
Clock input for the JTAG controller.
NOTE: This pin is internally pulled down.1
JT_RSTn2
I
CMOS
VDDO_JTAG
JTAG Reset
When asserted, resets the JTAG controller.
NOTE: This pin is internally pulled down.
JT_TMS_CPU
I
CMOS
VDDO_JTAG
CPU JTAG Mode Select
Controls CPU JTAG controller state.
Sampled with the rising edge of JT_CLK.
NOTE: This pin is internally pulled up.
JT_TMS_CORE
I
CMOS
VDDO_JTAG
Core JTAG Mode Select
Controls the Core JTAG controller state.
Sampled with the rising edge of JT_CLK.
NOTE: This pin is internally pulled up.
JT_TDO
O
CMOS
VDDO_JTAG
JTAG Data Out
Driven on the falling edge of JT_CLK.
JT_TDI
I
CMOS
VDDO_JTAG
JTAG Data In
JTAG serial data input. Sampled with the JT_CLK rising
edge.
NOTE: This pin is internally pulled up.
1. For information about signals internally pulled up or pulled down, see Section 2.3, Internal Pull-up and Pull-down Pins,
on page 55.
2. If this pull-down conflicts with other devices, the JTAG tool must not use this signal. This signal is not mandatory for the
JTAG interface, since the TAP (Test Access Port) can be reset by driving the JT_TMS signal HIGH for 5 JT_CLK cycles.
If JT_RSTn isn't used it should be connected to reset signal. Otherwise the internal pull-down will keep the TAP
controller in reset.
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
Document Classification: Proprietary Information
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88AP510
Hardware Specifications
2.2.9
PCI Express Interface Pin Assignments
Table 15: PCI Express Port 0/1 Interface Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
PEX<n>_CLK_
P/N
I/O
HCSL
PEX0_AVDD
PEX1_AVDD
PCI Express Reference Clock
Differential pair of PCI Express 100 MHz reference clocks.
The PCI Express clock direction is determined according to
the reset strapping.
When configured as an output, these signals must be pulled
down separately through a 49.9 Ω (1%) resistor.
PEX<n>_TX_P/N
O
CML
PEX0_AVDD
PEX1_AVDD
Transmit Lane
Differential pair of PCI Express transmit data
PEX<n>_RX_P/N
I
CML
PEX0_AVDD
PEX1_AVDD
Receive Lane
Differential pair of PCI Express receive data
Analog
PEX0_AVDD
PEX1_AVDD
Current Reference
Pull down to VSS through a 4.99 kΩ (1%) resistor.
<n>=0–1
PEX<n>_ISET
Doc. No. MV-S105141-U0 Rev. F
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Copyright © 2011 Marvell
Document Classification: Proprietary Information
July 13, 2011, Preliminary
Pin Information
Pin Descriptions
2.2.10
Serial-ATA II Interface Pin Assignments
Table 16: SATA II Interface Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
S_TX_P/N
O
CML
S_AVDD
Transmit data: Differential analog pair output of SATA II port
S_RX_P/N
I
CML
S_AVDD
Receive data: Differential analog pair input of SATA II port
SATA_
PRESENTn
O
CMOS
When this signal is asserted there is an active link between
the SATA II port and the external device (disk).
NOTE: This signal is multiplexed on MPP[2] and MPP[11].
SATA_ACTn
O
CMOS
For the
MPP[n]
power rail
information,
see Table 18,
MPP Pin
Assignments,
on page 43.
When this signal is asserted, there is an active and used link
between the SATA II port and the external device (disk).
NOTE: This signal is multiplexed on MPP[3], MPP[11], and
MPP[12].
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
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88AP510
Hardware Specifications
2.2.11
USB 2.0 Interface Pin Assignments
Table 17: USB 2.0 Interface Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
I/O
CML
USB0_AVDD
USB1_AVDD
USB 2.0 Differential Data+/- Pair
<n>=0–1
USB<n>_D_P/N
Doc. No. MV-S105141-U0 Rev. F
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Pin Information
Pin Descriptions
2.2.12
MPP Pin Assignments
Table 18: MPP Pin Assignments
Pin Name
I/ O
P in Ty p e
P o w e r R ai l
D e s c r i p t io n
MPP[7:0]
t/s
I/O
CMOS
VDDO_PMU
Multi Purpose Pin
Various functionalities for the PMU power domain.
NOTE: These pins have internal pull-up resistors.1
MPP[23:8]
t/s
I/O
CMOS
VDDO_MPP
Multi Purpose Pin
Various functionalities for the core power domain.
NOTE: These pins have internal pull-up resistors.
MPP[39:24]
t/s
I/O
CMOS
VDDO_CAM
Multi Purpose Pin
Various functionalities for the camera interface.
MPP[45:40]
t/s
I/O
CMOS
VDDO_SDIO0
Multi Purpose Pin
Various functionalities for the SDIO0 interface.
MPP[51:46]
t/s
I/O
CMOS
VDDO_SDIO1
Multi Purpose Pin
Various functionalities for the SDIO1 interface.
MPP[57:52]
t/s
I/O
CMOS
VDDO_AUD
Multi Purpose Pin
Various functionalities for the AU1 interface.
MPP[63:58]
t/s
I/O
CMOS
VDDO_MPP
Multi Purpose Pin
Various functionalities for the SPI0 and UART1
interfaces.
MPP[71:64]
O
CMOS
VDDO_NF
Multi Purpose Pin
Functionalities for NF_IO[15:8].
1. For information about signals internally pulled up or pulled down, see Section 2.3, Internal Pull-up and Pull-down Pins,
on page 55.
Note
A full description of the MPP pins functionality, and additional general purpose pins, is
in Section 5, Multi Purpose and General Purpose Pins Functionality, on page 61.
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
Document Classification: Proprietary Information
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88AP510
Hardware Specifications
2.2.13
LCD Interface Pin Assignments
Table 19: LCD Dumb Panel Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r i p t io n
LCD_CLK
O
CMOS
VDDO_LCD
LCD Pixel Clock
LCD_D, LCD_E, VSYNC and HSYNC signals change
at the rising or falling edge of this clock
(programmable).
LCD_E
O
CMOS
VDDO_LCD
LCD Data Enable Signal (Pixel valid indication)
When asserted, the LCD interface data bus is valid.
When de-asserted, the LCD interface data bus is
invalid.
Active high
LCD_HSYNC
O
CMOS
VDDO_LCD
Horizontal (line) synchronization signal
Active high or low (programmable).
LCD_VSYNC
O
CMOS
VDDO_LCD
Vertical (frame) synchronization signal
Active high or low (programmable).
LCD_D[23:0]
IO
CMOS
VDDO_LCD
LCD Data Bus
Pixel is encoded as RGB with 12, 16, 18, or 24-bits per
pixel.
R and B can swap. Bus bit order can reverse.
• 12-bit (RGB444 Mode)
• 16-bit (RGB565 Mode)
• 18-bit (RGB666 Mode)
• 24-bit (RGB888 Mode)
See Table 33, LCD Color Resolution per Mode, on
page 65 for the specific usage of LCD_D[23:0] in each
mode.
NOTE: In 12, 16, or 18-bit RGB modes, LCD_D[23] is
controlled as Pulse Width Modulation or as
BIAS (GPO).
These pins have integrated pull-down/pull-up
resistors. See details in Section 7.5, Pins
Sample Configuration, on page 76.
LCD_EXT_REF_
CLK[1:0]
I
CMOS
VDDO_VGA
External reference clocks to LCD controller. The pixel
clock of both LCD0/LCD1 controllers can be derived
from the external clock inputs.
NOTE: If a single external reference clock is used,
Marvell® recommends to use
LCD_EXT_REF_CLK[1].
Doc. No. MV-S105141-U0 Rev. F
Page 44
Copyright © 2011 Marvell
Document Classification: Proprietary Information
July 13, 2011, Preliminary
Pin Information
Pin Descriptions
2.2.14
Video Graphics Array (VGA) Controller Digital Interface Pin
Assignments
Table 20: VGA Channel Controller Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r i p t io n
VGA_HSYNC
O
CMOS
VDDO_VGA
VGA Horizontal Synchronization
VGA_VSYNC
O
CMOS
VDDO_VGA
VGA Vertical Synchronization
VGA_R
O
Analog
VGA_RGB_AVDD
Red Video Signal
VGA_G
O
Analog
VGA_RGB_AVDD
Green Video Signal
VGA_B
O
Analog
VGA_RGB_AVDD
Blue Video Signal
Analog
VGA_DAC_AVDDL
Current Reference
Pull down to VSS through a 150 kΩ (0.5%) resistor.
VGA_REXT
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
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Page 45
88AP510
Hardware Specifications
2.2.15
NAND Flash Interface Pin Assignments
Note
These pins have integrated pullup/pulldown resistor. See details in Section 2.3, Internal
Pull-up and Pull-down Pins, on page 55.
Table 21: NAND Flash Interface Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
NF_IO[15:0]
I/O
CMOS
VDDO_NF
NAND Flash Data bus
NF_CEn[3:0]
O
CMOS
VDDO_NF
NAND Flash Chip Enable
NF_WEn
O
CMOS
VDDO_NF
NAND Flash Write Enable
NF_REn
O
CMOS
VDDO_NF
NAND Flash Read Enable
NF_ALE
O
CMOS
VDDO_NF
NAND Flash Address Latch Enable
NF_CLE
O
CMOS
VDDO_NF
NAND Flash Command Latch Enable
NF_RDY[1:0]
I
CMOS
VDDO_NF
NAND Flash Ready/Busy_n (Low when Busy)
• NF_CEn[0] = RDY[0]
• NF_CEn[1] = RDY[1]
• NF_CEn[2] = RDY[0]
• NF_CEn[3] = RDY[1]
Doc. No. MV-S105141-U0 Rev. F
Page 46
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Document Classification: Proprietary Information
July 13, 2011, Preliminary
Pin Information
Pin Descriptions
2.2.16
UART Interface Pin Assignments
UART Port 1/2/3 pins are multiplexed on the MPP pins (see Section 5, Multi Purpose and General
Purpose Pins Functionality, on page 61).
Table 22: UART Interface Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
UA0_RXD
I
CMOS
VDDO_JTAG
RX Data
UA0_TXD
O
CMOS
VDDO_JTAG
TX Data
UA0_CTSn
I
CMOS
VDDO_JTAG
Clear To Send
Must be pulled down.
UA0_RTSn
O
CMOS
VDDO_JTAG
Request To Send
UA<n>_RXD
I
CMOS
RX Data
NOTE: UA1_RXD is multiplexed on MPP[62].
UA2_RXD is multiplexed on MPP[3] or MPP[15].
UA3_RXD is multiplexed on MPP[7] or MPP[19].
UA<n>_TXD
O
CMOS
For the
MPP[n]
power rail
information,
see Table 18,
MPP Pin
Assignments,
on page 43.
UA<n>_CTSn
I
CMOS
Clear To Send
NOTE: UA1_CTSn is multiplexed on MPP[22].
UA2_CTSn is multiplexed on MPP[1] or MPP[13].
UA3_CTSn is multiplexed on MPP[5] or MPP[17].
UA<n>_RTSn
O
CMOS
Request To Send
NOTE: UA1_RTSn is multiplexed on MPP[21].
UA2_RTSn is multiplexed on MPP[0] or MPP[12].
UA3_RTSn is multiplexed on MPP[4] or MPP[16].
<n>=1–3
TX Data
NOTE: UA1_TXD is multiplexed on MPP[63].
UA2_TXD is multiplexed on MPP[2] or MPP[14].
UA3_TXD is multiplexed on MPP[6] or MPP[18].
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
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Page 47
88AP510
Hardware Specifications
2.2.17
Synchronous Serial Protocol (SSP) Interface Pin
Assignments
All of the SSP pins are multiplexed on the MPP pins (see Section 5, Multi Purpose and General
Purpose Pins Functionality, on page 61). There are two options for selecting the multiplexing, as
described in the tables below.
Table 23: SSP Interface Pin Assignments Option 1
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
SSP_SCLK
I/O
CMOS
VDDO_AUD
SSP Serial Clock
Controls the timing of a serial transfer.
The SSP_SCLK can be generated internally (master mode)
or from an external source (slave mode).
NOTE: The signal is multiplexed on MPP[54].
SSP_SFRM
I/O
CMOS
VDDO_AUD
SSP Serial Frame Indicator
Indicates the beginning and the end of a serialized data
sample.
The SSP_SFRM can be generated internally (master mode)
or from an external source (slave mode).
NOTE: The signal is multiplexed on MPP[53].
SSP_TXD
O
CMOS
VDDO_AUD
SSP Transmit Data
Serial data out.
NOTE: The signal is multiplexed on MPP[52].
SSP_RXD
I
CMOS
VDDO_AUD
SSP Receive Data
Serial data in.
NOTE: The signal is multiplexed on MPP[55].
SSP_EXTCLK
I
CMOS
VDDO_MPP
SSP External Clock
A selectable external clock that replaces the internal
generated clock when SSP_SCLK is an output.
NOTE: The signal is multiplexed on MPP[13].
Doc. No. MV-S105141-U0 Rev. F
Page 48
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Pin Information
Pin Descriptions
Table 24: SSP Interface Pin Assignments Option 2
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
SSP_SCLK
I/O
CMOS
SSP Serial Clock
Controls the timing of a serial transfer.
The SSP_SCLK can be generated internally (master mode)
or from an external source (slave mode).
NOTE: The signal is multiplexed on MPP[23].
SSP_SFRM
I/O
CMOS
For the
MPP[n]
power rail
information,
see Table 18,
MPP Pin
Assignments,
on page 43.
SSP_TXD
O
CMOS
SSP Transmit Data
Serial data out.
NOTE: The signal is multiplexed on MPP[22].
SSP_RXD
I
CMOS
SSP Receive Data
Serial data in.
The signal is multiplexed on MPP[14].
SSP_EXTCLK
I
CMOS
SSP External Clock
A selectable external clock that replaces the internal
generated clock when SSP_SCLK is an output.
The signal is multiplexed on MPP[13].
SSP Serial Frame Indicator
Indicates the beginning and the end of a serialized data
sample.
The SSP_SFRM can be generated internally (master mode)
or from an external source (slave mode).
NOTE: The signal is multiplexed on MPP[21].
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
Document Classification: Proprietary Information
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88AP510
Hardware Specifications
2.2.18
Power Management Unit (PMU) Interface Pin Assignments
All of the PMU pins are multiplexed on the MPP pins. For information about using the MPP pins as
PMU pins, see Section 5.2, Power Management Unit Multiplexing, on page 63.
Table 25: Power Management Unit Interface
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r ip t io n
PMU_CPU_
PWRDWN
O
CMOS
MPP[15:8]:
VDDO_MPP
MPP[7:0]:
VDDO_PMU
CPU_PWRDWN1: CPU external voltage supplier powering
down.
PMU_CORE_
PWR_GOOD
I
CMOS
VDDO_PMU
CORE_PWR_GOOD1: VDD_CORE external voltage
supplier power good indication.
PMU_SDI
O
CMOS
MPP[15:8]:
VDDO_MPP
MPP[7:0]:
VDDO_PMU
SDI1: Serial interface for programming the Marvell®’s PMIC.
NOTE: The relevant power rail for this signal depends on
which MPP pin is used. It can be multiplexed on
MPP[15:8] or MPP[7:0].
PMU_STBY_
PWRDWN
O
CMOS
VDDO_PMU
STBY_PWRDWN1: Standby Power Down for disabling
external regulators.
PMU_EXT<n>_
WU2
I
CMOS
VDDO_PMU
EXT_WU1: External low-power modes wake-up pins.
PMU_BAT_
FAULT
I
CMOS
VDDO_PMU
BAT_FAULT1: Battery Fault external indication.
PMU_BLINK
O
CMOS
MPP[15:8]:
VDDO_MPP
MPP[7:0]:
VDDO_PMU
BLINK1: Blink option with configurable duty cycle for LED
control.
PMU_GPO
O
CMOS
VDDO_PMU
Drive_0 or Drive_11: General Purpose Output
1. Name of signal control option in “PM Signal Selectors Control 0” and “PM Signal Selectors Control 1” registers.
2. <n> represents 0–2.
Doc. No. MV-S105141-U0 Rev. F
Page 50
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Pin Information
Pin Descriptions
2.2.19
Miscellaneous Pin Assignments
The Miscellaneous signal list contains clocks, reset, and PLL related signals.
Table 26: Miscellaneous Pin Assignments
Pin Name
I /O
Pi n Ty pe
Power Rail
D e s c r i p t io n
REFCLK_XIN
I
CMOS
REFCLK_AVDD
Crystal input for main 25 MHz reference clock serving
USB 2.0 PHY, GbE interface, SATA PHY, CPU PLL,
Core PLL.
REFCLK_XOUT
O
Analog
REFCLK_AVDD
Crystal output for main 25 MHz reference clock.
Analog
REFCLK_AVDD
Current reference for crystal, SATA, USB, and PEX
Clock. Connect to VSS through a 6.04 Kilohm
pull-down resistor.
REFCLK_ISET
SYSRST_INn
I
CMOS
VDDO_JTAG
System Reset
Main reset signal of the device.
Used to reset all units, except for PMU, to their initial
state.
NOTE: Must be pulled down through a resistor.
SYSRST_OUTn
O
CMOS
VDDO_JTAG
System Reset Output
Main reset signal for the board. When asserted it
remains low for 20 ms.
NOTE: It is controlled by the internal Power On Reset
(POR) unit. See details in Section 7.2.2,
System Reset Output, on page 75.
RTC_XIN
I
Analog
RTC_AVDD
Crystal input for real time clock (32.768 kHz).
NOTE: A 10 Mohm resistor is required between
RTC_XIN and RTC_XOUT.
RTC_XOUT
O
Analog
RTC_AVDD
Crystal output for real time clock (32.768 kHz).
NOTE: A 330 Kilohm resistor is required between
RTC_XOUT and the crystal
MRn
I
CMOS
VDDO_PMU
Manual Reset Input.
Used to reset all units (including PMU and POR) to
their initial state.
SYSRST_OUTn is asserted low as long as the MRn
signal is asserted low, and for additional 20 msec after
MRn de-assertion.
NOTE: Must be pulled up through a resistor.
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
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88AP510
Hardware Specifications
2.2.20
Reserved Pin Assignments
Table 27: Reserved Pin Assignments
P in N a m e
D e s c r ip t i o n
RSVD_NC[11:0]
These pins should be left not connected.
RSVD_VDD_
CORE[0]
Connect to VDD_CORE.
NOTE: Listed in the pin map Excel file attached to Section 4, 88AP510 Pin Map
and Pin List, on page 60 as pin AB17.
RSVD_VDD_
CORE[1]
Connect to VDD_CORE.
NOTE: Listed in the pin map Excel file attached to Section 4, 88AP510 Pin Map
and Pin List, on page 60 as pin J22.
Doc. No. MV-S105141-U0 Rev. F
Page 52
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Pin Information
Pin Descriptions
2.2.21
Power Supply Pin Assignments
Table 28 provides the voltage levels for the various interface pins. These do not include the analog
power supplies for the PLLs or PHYs which are explicitly mentioned in the other pin description
tables.
Table 28: Power Supply Pin Assignments
Pin Name
Pi n Ty pe
D e s c r ip t io n
VDD_CORE
Power
1.0V digital core voltage (including VMeta™ and GPU)
VDD_CPU
Power
1.1V digital CPU core power for the CPU, L1/2 Cache, and FPU, and WMMX2 units
VDD_PMU
Power
1.0V digital power supply for the Power Management Unit (PMU).
VDDO_AUD
Power
3.3V I/O supply voltage for the Audio interface (S/PDIF, AC ‘97, I2S, SSP)
VDDO_CAM
Power
1.8V or 3.3V I/O supply voltage for the Camera interface
VDDO_GIGA
Power
1.8V, 2.5V, or 3.3V I/O supply voltage for the RGMII and SMI interfaces
VDDO_JTAG
Power
3.3V I/O supply voltage for the TWSI, JTAG, and UART interfaces
VDDO_LCD
Power
1.8V, 2.5V, or 3.3V I/O supply voltage for the LCD interfaces
VDDO_VGA
Power
1.8V, 2.5V, or 3.3V I/O supply voltage for the VGA (digital signals) interfaces
VDDO_M
Power
1.35 (DDR3), 1.5V (DDR3/DDR2), or 1.8V (DDR2) I/O supply for DRAM interface
M_AVDD
Analog
Power
Connect to GND.
M_VREFS
Power
Voltage Reference for DDR Data Strobe (M_DQS)
Voltage reference equals 0.5*VDDO_M.
M_VREFD
Power
Voltage Reference for DDR Data (M_DQ)
Voltage reference equals 0.5*VDDO_M.
VDDO_PMU
Power
3.3V I/O supply voltage for the MPP[7:0] and PMU related signals
VDDO_MPP
Power
3.3V I/O supply voltage for the MPP[23:8] and SPI interfaces
VDDO_NF
Power
1.8V or 3.3V I/O supply voltage for the NAND interface
VDDO_SDIO0
VDDO_SDIO1
Power
1.8V or 3.3V I/O supply voltage for the SDIO interface
PEX0_AVDD
PEX1_AVDD
Analog
Power
1.8V PCI Express PHY quiet power supply
NOTE: See the 88AP510 Design Guide for power supply filtering recommendations.
USB0_AVDD
USB1_AVDD
Analog
Power
3.3V USB 2.0 PHY quiet power supply
NOTE: See the 88AP510 Design Guide for power supply filtering recommendation.
S_AVDD
Analog
Power
2.5V SATA II quiet power supply
NOTE: See 88AP510 Design Guide for power supply filtering recommendation.
Copyright © 2011 Marvell
July 13, 2011, Preliminary
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88AP510
Hardware Specifications
Table 28: Power Supply Pin Assignments (Continued)
Pin Name
Pi n Ty pe
D e s c r ip t io n
VGA_RGB_AVDD
Analog
Power
2.5V analog power for channels red, green, and blue
VGA_DAC_AVDD
Analog
Power
2.5V analog power supply for the gain DACs
VGA_DAC_AVDDL
Analog
Power
1.8V VDD analog for reference generator
VGA_VSS
Analog
Ground
Analog ground supply for the VGA DAC digital circuit.
REFCLK_AVDD
Analog
Power
2.5V Crystal Controller quiet power supply
REFCLK_AVSS
Analog
Ground
Ground supply for the Crystal Controller, Spread Spectrum, and System PLL
SOC_PLL_AVDD
Analog
Power
1.8V Spread Spectrum and System PLL quiet power supply
RTC_AVDD
Analog
Power
1.8V RTC unit quiet power supply from backup battery
THERM_AVDD
Analog
Power
1.8V Thermal sensor quiet power supply
CPU_PLL_AVDD
Analog
Power
1.8V CPU PLL quiet power supply
NOTE: Implement the PLL filter as described in the 88AP510 Design Guide.
CPU_PLL_AVSS
Analog
Ground
Ground supply for the CPU PLL
NOTE: Implement the PLL filter as described in the 88AP510 Design Guide.
AU_AVDD
Analog
Power
1.8V Audio unit quiet power supply and SSCG quiet power supply.
VSS
GND
Ground
Doc. No. MV-S105141-U0 Rev. F
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Copyright © 2011 Marvell
Document Classification: Proprietary Information
July 13, 2011, Preliminary
Pin Information
Internal Pull-up and Pull-down Pins
2.3
Internal Pull-up and Pull-down Pins
Some pins of the device package are connected to internal pull-up and pull-down resistors. When
these pins are Not Connected (NC) on the system board, these resistors set the default value for
input and sample at reset configuration pins.
The internal pull-up and pull-down resistor value is approximately 50 Kilohm. An external resistor
with a lower value can override this internal resistor.
Table 29: Internal Pull-up and Pull-down Pins
S ig na l
P i n N um be r
Pu l l-u p /P u ll -d o w n
AU0_I2SLRCLK_SYNC
J23
Pull-down
AU0_SYSCLK_OUT
G26
Pull-down
AU1_I2SDO
H22
Pull-down
AU1_I2SLRCLK
G23
Pull-down
AU1_I2SMCLK
H24
Pull-down
AU1_SPDIFO
G22
Pull-down
CAM_SNSR_CTL0
AC21
Pull-up
CAM_SNSR_CTL1
AB21
Pull-down
GE_TXCLK
AC03
Pull-down
GE_TXCTL
AD01
Pull-down
GE_TXD[0]
AB03
Pull-down
GE_TXD[1]
AA04
Pull-down
GE_TXD[2]
AD02
Pull-down
GE_TXD[3]
AE02
Pull-down
JT_CLK
AC16
Pull-down
JT_RSTn
AF16
Pull-down
JT_TDI
AC17
Pull-up
JT_TMS_CORE
AD16
Pull-up
JT_TMS_CPU
AE16
Pull-up
RSVD_NC[0]
N26
Pull-up
LCD_D[0]
G03
Pull-down
LCD_D[1]
G04
Pull-down
LCD_D[2]
F01
Pull-up
LCD_D[3]
G02
Pull-down
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
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88AP510
Hardware Specifications
Table 29: Internal Pull-up and Pull-down Pins (Continued)
S ig na l
P i n N um be r
Pu l l-u p /P u ll -d o w n
LCD_D[4]
G01
Pull-down
LCD_D[5]
J05
Pull-down
LCD_D[6]
H04
Pull-down
LCD_D[7]
H03
Pull-down
LCD_D[8]
H02
Pull-down
LCD_D[9]
J04
Pull-down
LCD_D[10]
J03
Pull-down
LCD_D[11]
J02
Pull-down
LCD_D[12]
J01
Pull-down
LCD_D[13]
K05
Pull-up
LCD_D[14]
L04
Pull-down
LCD_D[15]
K03
Pull-up
LCD_D[16]
L03
Pull-up
LCD_D[17]
K01
Pull-down
LCD_D[18]
L02
Pull-down
LCD_D[19]
L05
Pull-up
MPP[16]
T26
Pull-up
MPP[17]
T25
Pull-up
MPP[18]
U24
Pull-up
MPP[19]
T23
Pull-down
MPP[20]
T22
Pull-down
MPP[21]
U26
Pull-up
MPP[22]
U23
Pull-down
MPP[23]
U22
Pull-up
NF_ALE
AB24
Pull-down
NF_CEn[0]
AE26
Pull-up
NF_CEn[1]
AF25
Pull-up
NF_CEn[2]
AD25
Pull-up
NF_CEn[3]
AD24
Pull-up
Doc. No. MV-S105141-U0 Rev. F
Page 56
Copyright © 2011 Marvell
Document Classification: Proprietary Information
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Pin Information
Internal Pull-up and Pull-down Pins
Table 29: Internal Pull-up and Pull-down Pins (Continued)
S ig na l
P i n N um be r
Pu l l-u p /P u ll -d o w n
NF_CLE
AC24
Pull-down
NF_IO[0]
AB26
Pull-down
NF_IO[1]
AA23
Pull-down
NF_IO[2]
AA26
Pull-down
NF_IO[3]
Y22
Pull-down
NF_IO[4]
Y24
Pull-down
NF_IO[5]
Y23
Pull-up
NF_IO[6]
Y25
Pull-up
NF_IO[7]
Y26
Pull-down
NF_IO[8]
W22
Pull-up
NF_IO[9]
W23
Pull-down
NF_IO[10]
W24
Pull-up
NF_IO[11]
W25
Pull-down
NF_IO[12]
V23
Pull-down
NF_IO[13]
V24
Pull-up
NF_IO[14]
V25
Pull-down
NF_IO[15]
V26
Pull-down
NF_RDY[0]
AA24
Pull-up
NF_RDY[1]
AB25
Pull-up
NF_REn
AD26
Pull-down
NF_WEn
AC25
Pull-up
RSVD_NC[1]
Y03
Pull-down
SPI_SCK
N23
Pull-down
SPI_MOSI
N24
Pull-down
UA0_TXD
AF17
Pull-up
UA1_TXD
AC18
Pull-up
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
Document Classification: Proprietary Information
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88AP510
Hardware Specifications
2.4
Pin State During Reset
During reset (while SYSRST_INn is asserted) all external pins are inputs except for the pins listed in
Table 30.
Table 30: Pin State During Reset
S ig na l
P i n N um be r
Sta t e a t R e s e t
SYSRST_OUTn
AB15
Output Low
NF_CEn[0]
AE26
Output (Drive high)
NF_CEn[1]
AF25
Output (Drive high)
NF_CEn[2]
AD25
Output (Drive high)
NF_CEn[3]
AD24
Output (Drive high)
DDR Interface
HiZ
Doc. No. MV-S105141-U0 Rev. F
Page 58
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Document Classification: Proprietary Information
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Unused Interface Strapping
3
Unused Interface Strapping
Table 31 lists the signal strapping to be used for systems in which some of the device interfaces are
unused (not connected).
Table 31: Unused Interface Strapping
Unused Interface
Str a pp i ng
Gigabit Ethernet RGMII
If not using the Gigabit Ethernet port, pull down: GE_RXCLK, GE_RXD[3:0], and
GE_RXCTL.
Gigabit Ethernet SMI
Pull up GE_MDIO.
MPP[23:0]
Configure any other unused MPP pins to GPIO output.
Connect VDDO_MPP and VDDO_PMU.
USB
Discard the power filter.
Leave USB_AVDD connected to 3.3V.
All other signals can be left unconnected.
PCI Express
Discard the analog power filters.
Leave PEX_AVDD connected to 1.8V.
Pull down the PEX_CLK_N signal to GND.
Pull up the PEX_CLK_P signal to 1.8V.
All other signals, including PEX<n>_ISET, can be left unconnected.
Configure the PEX_CLK_P and PEX_CLK_N signals as inputs, as indicated in Section 7.5,
Pins Sample Configuration, on page 76.
SATA
Discard the analog power filters.
S_AVDD can be left unconnected.
RTC
The RTC must be connected to an external 32.768 KHz crystal to ensure proper operation.
NAND Flash
Connect VDDO_NF to 3.3V.
SDIO
VDDO_SDIO0 can be left unconnected.
Connect VDDO_SDIO1 to 3.3V.
Audio 0, 1, and SSP units
Connect VDDO_AUD to 3.3V.
LCD Interface
Connect VDDO_LCD to 3.3V.
VGA port
VGA_RGB_AVDD, VGA_DAC_AVDD and VGA_DAC_AVDDL can be left unconnected.
Camera
Connect VDDO_CAM to 3.3V.
Pull up CAM_TW_SDA and CAM_TW_SCK.
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
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88AP510
Hardware Specifications
4
88AP510 Pin Map and Pin List
The attached pin map and pin list is PRELIMINARY and SUBJECT TO CHANGE.
Note
The 88AP510 pin lists are provided as Excel file attachments.
To open the attached Excel pin list files, double-click the pin icon below:
88AP510 Pin Map
File attachments are only supported by Adobe Reader 6.0 and above.
Note
To download the latest version of free Adobe Reader go to http://www.adobe.com.
Doc. No. MV-S105141-U0 Rev. F
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Multi Purpose and General Purpose Pins Functionality
MPP[71:0] Multiplexing Options
5
Multi Purpose and General Purpose Pins
Functionality
This section details the MPP signals and PMU, LCD, and Audio/SSP interfaces multiplexing options.
5.1
MPP[71:0] Multiplexing Options
The 88AP510 device contains 72 Multi Purpose Pins (MPP). Each one can be assigned to a
different functionality through MPP Control 0/1/2/4 registers, the General MPP Configuration
register, and the General PMU MPP Control Register. The multiplexing schemes are shown in
Figure 2, “Multi Purpose Pins [23:0] Selection Scheme and Figure 3, “Multi Purpose Pins [71:24]
Selection Scheme.
„
General Purpose pins: GPIO [63:0] (input/output) and GPO [71:64] (output only)
„
SATA active and SATA present indications—see the SATA section in the 88AP510 User Manual
„
SPI interface (port 1): SPI_1_MISO, SPI_1_MOSI, SPI_1_SCK, SPI_1_CSn.
„
UART interface (port 2 and port 3): Transmit and receive functions: UA2_TXD, UA2_RXD,
UA3_TXD, UA3_RXD, and Modem control functions (includes port 1): UA1_RTSn, UA1_CTSn,
UA2_RTSn, UA2_CTSn, UA3_RTSn, UA3_CTSn
„
SDIO interface (port 0 and port 1): Card Detect, Write Protect, Bus Power, LED Control
„
Audio interface (port 0 and port 1): AU_EXTCLK (Adunit 0 ext_mclk and Adunit 1 ext_mclk)
„
Audio AC ‘97 Interface: System clock output for external CODEC, AC97_DATA_IN1,
AC97_DATA_IN2, AC97_DATA_IN3
„
SSP Interface: SSP_RXD, SSP_TXD, SSP_SFRM, SSP_SCLK, SSP_EXTCLK
„
TWSI interface option 2 and option 3: TW_SDA, TW_SCK, TW_SDA, TW_SCK
„
LCD Pulse Width Modulation signal LCD0_PWM and LCD1_PWM.
„
LCD SPI Interface: SPI_2_MISO, SPI_2_MOSI, SPI_2_SCK, SPI_2_CS0, and SPI_2_CS1.
Note
When a functionality has multiple pin multiplexing options, only one of the possible
options can be selected. Selecting more then one option results in unpredictable
behavior.
Copyright © 2011 Marvell
July 13, 2011, Preliminary
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88AP510
Hardware Specifications
Figure 2: Multi Purpose Pins [23:0] Selection Scheme
MPP Control 0/1 register used to select
the MPP configuration option type.
Option 0
Option 1
Option F
MPP [15:0]/
PMU[15:0]
Option 0
Option 1
Option F
PM Signal Selectors Control 0/1 register
used to select PMU[15:0] signal
functionality.
General PMU MPP Control register used
to select between the MPP and PMU
domain, per MPP.
PMU Interface Control register used by
PMU to control signals during reset.
MPP Control 2 register to select the MPP
configuration option type.
Option 0
Option 1
MPP[23:16]
Option F
Doc. No. MV-S105141-U0 Rev. F
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Document Classification: Proprietary Information
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Multi Purpose and General Purpose Pins Functionality
Power Management Unit Multiplexing
Figure 3: Multi Purpose Pins [71:24] Selection Scheme
Hardware Controller Interface
(Camera, SDIO 0/1, SPI, UART1,
Audio 1, NAND Flash I/O)
MPP/GPIO[71:24]
GPIO 0 and 1 registers
Controller/GPIO Select per interface
Use the MPP 4 Control register to
select between a hardware
controller’s interface or GPIO per
interface.
The Multi Purpose Pin Functional Summary table is provided as an Excel file attachment. It shows
the functionality of the MPP pins as determined by the MPP Control registers, see the MPP
Registers appendix in the 88AP510 Functional Specifications.
To open the attached Excel Multi Purpose Pin Functional Summary file,
double-click the pin icon below:
88AP510 Multi Purpose Pin Functional Summary
File attachments are only supported by Adobe Reader 6.0 and above.
Note
5.2
To download the latest version of free Adobe Reader go to http://www.adobe.com.
Power Management Unit Multiplexing
The MPP[15:0] signals can also be used to control power management functionality by setting the
<MPPx_Gen/PMU_Sel> bits[15:0] in the General PMU MPP Control register, see the MPP
Registers appendix in the 88AP510 Functional Specifications.
If an <MPPx_Gen/PMU_Sel> field is cleared to 0x0, the MPP functionality is according to the Multi
Purpose Pin Functional Summary table in the attached Excel file.
Copyright © 2011 Marvell
July 13, 2011, Preliminary
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88AP510
Hardware Specifications
If an <MPPx_Gen/PMU_Sel> field is set to 0x1, the signal is used to control the power management
functionality. The power management functionality for each MPP signal is set by the
<PM_SIG_x_CTRL> fields in the PM Signal Selectors Control 0 register (for MPP[7:0]) and the PM
Signal Selectors Control 1 register (for MPP[15:8]), see the Power Management Unit Registers
appendix in the 88AP510 Functional Specifications.
Note
5.3
As specified in Table 28, Power Supply Pin Assignments, on page 53, the MPP[7:0]
signals are internally powered by VDDO_PMU, and the MPP[15:8] signals are internally
powered by VDDO_MPP.
LCD Multiplexing Options
LCD port A support various multiplexing options for eight different operating modes.
Table 32 lists the LCD port A I/O pin allocation per mode.
„
Note
„
„
Mode 0, 2, and 4 have no SPI allocated pins. The SPI I/O is multiplexed with MPP
pins.
Mode 5 only supports 12-bit color.
Mode 6 has one chip select for SPI.
Table 32: LCD IO Pin [27:0] Allocation
I/O name
and
Mode 0
M od e 1
Mode 2
Mo d e 3
M o de 4
Mode 5
Mo d e 6
Mode 7
Mo d e 8
D u m b LC D
2 4- b i t
Color
w i th o u t
S PI
D um b L C D
18 -b it
C ol or w i th
SPI
Dumb LCD
1 8- bi t
Color
w i th o u t
S PI
Du m b L CD
16- b i t
Color with
SPI
Dumb LCD
16 -b it
Color
w i t h ou t
SPI
D u m b LC D
1 2- b i t
Color
Sma r t
Pa ne l
18-bit Bus
S m ar t
P an el
1 6- bi t B us
Sma r t
P an e l 8- b i t
Bu s
LCD_D[0]
LCD_D[0]
LCD_D[0]
LCD_D[0]
LCD_D[0]
LCD_D[0]
SMPN_DB[0]
SMPN_DB[0]
SMPN_DB[0]
LCD_D[1]
LCD_D[1]
LCD_D[1]
LCD_D[1]
LCD_D[1]
LCD_D[1]
SMPN_DB[1]
SMPN_DB[1]
SMPN_DB[1]
LCD_D[2]
LCD_D[2]
LCD_D[2]
LCD_D[2]
LCD_D[2]
LCD_D[2]
SMPN_DB[2]
SMPN_DB[2]
SMPN_DB[2]
LCD_D[3]
LCD_D[3]
LCD_D[3]
LCD_D[3]
LCD_D[3]
LCD_D[3]
SMPN_DB[3]
SMPN_DB[3]
SMPN_DB[3]
LCD_D[4]
LCD_D[4]
LCD_D[4]
LCD_D[4]
LCD_D[4]
LCD_D[4]
SMPN_DB[4]
SMPN_DB[4]
SMPN_DB[4]
LCD_D[5]
LCD_D[5]
LCD_D[5]
LCD_D[5]
LCD_D[5]
LCD_D[5]
SMPN_DB[5]
SMPN_DB[5]
SMPN_DB[5]
LCD_D[6]
LCD_D[6]
LCD_D[6]
LCD_D[6]
LCD_D[6]
LCD_D[6]
SMPN_DB[6]
SMPN_DB[6]
SMPN_DB[6]
LCD_D[7]
LCD_D[7]
LCD_D[7]
LCD_D[7]
LCD_D[7]
LCD_D[7]
SMPN_DB[7]
SMPN_DB[7]
SMPN_DB[7]
LCD_D[8]
LCD_D[8]
LCD_D[8]
LCD_D[8]
LCD_D[8]
LCD_D[8]
SMPN_DB[8]
SMPN_DB[8]
LCDGPIO[0]
LCD_D[9]
LCD_D[9]
LCD_D[9]
LCD_D[9]
LCD_D[9]
LCD_D[9]
SMPN_DB[9]
SMPN_DB[9]
LCDGPIO[1]
LCD_D[10]
LCD_D[10]
LCD_D[10]
LCD_D[10]
LCD_D[10]
LCD_D[10]
SMPN_
DB[10]
SMPN_DB
[10]
LCDGPIO[2]
LCD_D[11]
LCD_D[11]
LCD_D[11]
LCD_D[11]
LCD_D[11]
LCD_D[11]
SMPN_
DB[11]
SMPN_DB
[11]
LCDGPIO[3]
LCD_D[12]
LCD_D[12]
LCD_D[12]
LCD_D[12]
LCD_D[12]
LCDGPIO[0]
SMPN_
DB[12]
SMPN_DB
[12]
LCDGPIO[4]
LCD_D[13]
LCD_D[13]
LCD_D[13]
LCD_D[13]
LCD_D[13]
LCDGPIO[1]
SMPN_
DB[13]
SMPN_
DB[13]
LCDGPIO[5]
Doc. No. MV-S105141-U0 Rev. F
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Copyright © 2011 Marvell
Document Classification: Proprietary Information
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Multi Purpose and General Purpose Pins Functionality
LCD Multiplexing Options
Table 32: LCD IO Pin [27:0] Allocation (Continued)
I/O name
and
Mode 0
M od e 1
Mode 2
Mo d e 3
M o de 4
Mode 5
Mo d e 6
Mode 7
Mo d e 8
D u m b LC D
2 4- b i t
Color
w i th o u t
S PI
D um b L C D
18 -b it
C ol or w i th
SPI
Dumb LCD
1 8- bi t
Color
w i th o u t
S PI
Du m b L CD
16- b i t
Color with
SPI
Dumb LCD
16 -b it
Color
w i t h ou t
SPI
D u m b LC D
1 2- b i t
Color
Sma r t
Pa ne l
18-bit Bus
S m ar t
P an el
1 6- bi t B us
Sma r t
P an e l 8- b i t
Bu s
LCD_D[14]
LCD_D[14]
LCD_D[14]
LCD_D[14]
LCD_D[14]
LCDGPIO[2]
SMPN_
DB[14]
SMPN_
DB[14]
LCDGPIO[6]
LCD_D[15]
LCD_D[15]
LCD_D[15]
LCD_D[15]
LCD_D[15]
LCDGPIO[3]
SMPN_
DB[15]
SMPN_
DB[15]
LCDGPIO[7]
LCD_D[16]
LCD_D[16]
LCD_D[16]
LCDGPIO[0]
LCDGPIO[0]
LCDGPIO[4]
SMPN_
DB[16]
SMPN_CS1
SMPN_CS1
LCD_D[17]
LCD_D[17]
LCD_D[17]
LCDGPIO[1]
LCDGPIO[1]
LCDGPIO[5]
SMPN_
DB[17]
SMPN_CS0
SMPN_CS0
LCD_D[18]
SPI_2_CS1
LCDGPIO[0]
SPI_2_CS1
LCDGPIO[2]
SPI_2_CS1
SMPN_CS0
SPI_2_CS1
SPI_2_CS1
LCD_D[19]
SPI_2_CS0
LCDGPIO[1]
SPI_2_CS0
LCDGPIO[3]
SPI_2_CS0
SPI_2_CS0
SPI_2_CS0
SPI_2_CS0
LCD_D[20]
SPI_2_MISO
LCDGPIO[2]
SPI_2_MISO
LCDGPIO[4]
SPI_2_MISO
SPI_2_MISO
SPI_2_MISO
SPI_2_MISO
LCD_D[21]
SPI_2_MOSI
LCDGPIO[3]
SPI_2_MOSI
LCDGPIO[5]
SPI_2_MOSI
SPI_2_MOSI
SPI_2_MOSI
SPI_2_MOSI
LCD_D[22]
SPI_2_SCK
LCDGPIO[4]
SPI_2_SCK
LCDGPIO[6]
SPI_2_SCK
SPI_2_SCK
SPI_2_SCK
SPI_2_SCK
LCD_D[23]
PWM
PWM
PWM
PWM
PWM
SMPN_RSTB
SMPN_RSTB
SMPN_RSTB
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
SMPN_A0
SMPN_A0
SMPN_A0
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
SMPN_RDB
SMPN_RDB
SMPN_RDB
LCD_CLK
LCD_CLK
LCD_CLK
LCD_CLK
LCD_CLK
LCD_CLK
SMPN_WRB
SMPN_WRB
SMPN_WRB
LCD_E
LCD_E
LCD_E
LCD_E
LCD_E
LCD_E
SMPN_VSYN
C
SMPN_VSYN
C
SMPN_VSYN
C
Table 33 lists the LCD color resolution per mode used by the LCD_D[23:0] signals. Use
<CFG_DUMBMODE> bits[31:28] in the LCD_SPU_DUMB_CTRL register to select the mode.
Table 33: LCD Color Resolution per Mode
LCD_D[23:0]
R G B 4 4 4 M od e
RGB565 Mode
RGB666 Mode
RGB888 Mode
LCD_D[0]
Red[4]
Red[3]
Red[2]
Red[0]
LCD_D[1]
Red[5]
Red[4]
Red[3]
Red[1]
LCD_D[2]
Red[6]
Red[5]
Red[4]
Red[2]
LCD_D[3]
Red[7]
Red[6]
Red[5]
Red[3]
LCD_D[4]
Green[4]
Red[7]
Red[6]
Red[4]
LCD_D[5]
Green[5]
Green[2]
Red[7]
Red[5]
LCD_D[6]
Green[6]
Green[3]
Green[2]
Red[6]
LCD_D[7]
Green[7]
Green[4]
Green[3]
Red[7]
LCD_D[8]
Blue[4]
Green[5]
Green[4]
Green[0]
Copyright © 2011 Marvell
July 13, 2011, Preliminary
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88AP510
Hardware Specifications
Table 33: LCD Color Resolution per Mode (Continued)
LCD_D[23:0]
R G B 4 4 4 M od e
RGB565 Mode
RGB666 Mode
RGB888 Mode
LCD_D[9]
Blue[5]
Green[6]
Green[5]
Green[1]
LCD_D[10]
Blue[6]
Green[7]
Green[6]
Green[2]
LCD_D[11]
Blue[7]
Blue[3]
Green[7]
Green[3]
LCD_D[12]
-
Blue[4]
Blue[2]
Green[4]
LCD_D[13]
-
Blue[5]
Blue[3]
Green[5]
LCD_D[14]
-
Blue[6]
Blue[4]
Green[6]
LCD_D[15]
-
Blue[7]
Blue[5]
Green[7]
LCD_D[16]
-
-
Blue[6]
Blue[0]
LCD_D[17]
-
-
Blue[7]
Blue[1]
LCD_D[18]
-
-
-
Blue[2]
LCD_D[19]
-
-
-
Blue[3]
LCD_D[20]
-
-
-
Blue[4]
LCD_D[21]
-
-
-
Blue[5]
LCD_D[22]
-
-
-
Blue[6]
LCD_D[23]
-
-
-
Blue[7]
5.4
Audio and SSP I/O Multiplexing Options
The AC ’97 and SSP interfaces are both connected to the Peripheral DMA through the same, shared
peripheral bus.
The AC ’97 interface shares the DCO (Digital Controlled Oscillator) with the Audio0 (AU0) unit
(I2S / S/PDIF). The AC ’97 interface derives the clock from the DCO in AU0.
Figure 4 shows the peripheral multiplexing options for the Audio0/1, AC ’97, and SSP interfaces.
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Multi Purpose and General Purpose Pins Functionality
Audio and SSP I/O Multiplexing Options
When the AC ’97 interface is not used, the peripheral bus clock can be derived from a PLL divider
instead of DCO0.
Figure 4: Peripheral Multiplexing
I2S
AU0/DCO0
AU0/AC ‘97
Dedicated interface
AC ‘97
AC ‘97
SSP/PSP
SSP
MPP[57:52]
I2S, S/PDIF
AU1/DCO1
„
Note
„
To select between AU0 or AC ‘97, see CAM_SNSR_CTL1 in the Section 7.5, Pins
Sample Configuration, on page 76.
To select between SSP or AU1, see the “General Purpose I/O Port Interface”
section in the 88AP510 Functional Specifications.
Table 34 shows the cross-configuration option settings for the Audio0/1, AC ‘97, and SSP interfaces.
For each option, the configuration requirements for each of the interfaces is indicated.
Table 34: Peripheral Cross-Configuration Options
Option
AU0
A C ’9 7
S SP 1, 2
AU1
1
I2S / S/PDIF;
DCO0
Not used
I/O: MPP[63:32];
Peripheral bus clock: PLL Divider
Serial: PLL divider.
S/PDIF;
DCO1
2
Not Used
AC ’97;
DCO0
I/O: MPP[63:32];
Peripheral bus clock: DCO0
Serial: PLL divider or DCO0
S/PDIF;
DCO1
3
I2S / S/PDIF;
DCO0
Not used
I/O: MPP[31:0];
Peripheral bus clock: PLL Divider
Serial: PLL divider
I2S / S/PDIF;
DCO1
4
Not Used
AC ’97;
DCO0
I/O: MPP[31:0];
Peripheral bus clock: DCO0
Serial: PLL divider or DCO0
I2S / S/PDIF;
DCO1
1. Lists the SSP I/O option, the Peripheral bus clock source option, and the Serial clock source option.
2. SSP I/O may be configured on either MPP[31:0] or MPP[63:32], but must not be configured on both
segments.
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88AP510
Hardware Specifications
Note
For further information about working with the SSP serial clock, see the “Audio and
SSP Clocking” section in the 88AP510 Functional Specifications.
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Clocking
6
Clocking
Table 35 lists the clocks in the 88AP510. Clocking scheme details are included in the 88AP510
Design Guide.
Table 35: 88AP510 Clocks
C l o ck Ty p e
R e f er e n c e C l o c k
D e r i ve d C l oc k
CPU PLL
•
REFCLK_XIN (25 MHz)
• CPU clock
• L2 cache clock
• DDR clock
See Table 36, Supported Clock Combinations, on
page 70 for CPU, L2 cache, and DDR frequency
configuration.
L2 cache clock frequency must be equal or
higher then DDR clock frequency.
If the <SSCG_en> bit (sampled at reset) is set,
then the SSCG circuit is applied for the CPU PLL
reference clock.
Core PLL
(2 GHz)
•
REFCLK_XIN (25 MHz)
•
•
•
•
•
•
•
•
•
•
PEX PHY
USB PHY PLL
•
•
PEX_CLK_N/PEX_CLK_P (100 MHz)
The reference clock is either external or
driven by the core PLL.
REFCLK_XIN (25 MHz)
•
TCLK (core clock)
SPI clock (Divided TCLK)
SMI clock (TCLK/128 MHz)
TWSI clock
(up to TCLK/1600)
NAND Flash Controller
PMU Clock (TCLK)
AXI Interconnect Clock
SDIO clock (up to 50 MHz)
PEX_CLK_N/PEX_CLK_P
(100 MHz)
Gigabit Ethernet clock
(125 MHz)
SSP controller interface or SSP external
reference clock
Camera clock
(up to 50MHz)
LCD and VGA clocks
Graphic Processor clock
Video Processor clock
•
A 250 MHz clock used by the PCI Express
interface (transaction layer, link layer, and
PHY MAC layer)
A 2.5 GHz clock for the PHY analog part.
•
USB clock (60 MHz)
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88AP510
Hardware Specifications
Table 35: 88AP510 Clocks (Continued)
C l o ck Ty p e
R e f er e n c e C l o c k
D e r i ve d C l oc k
SATA PHY PLL
•
REFCLK_XIN (25 MHz)
•
RTC
•
RTC_XIN (32.768 kHz)
• RTC Clock (32.768 KHz)
• PMU Clock (32.768 KHz)
NOTE: Used for the RTC and PMU, see the Real
Time Clock section in the 88AP510
Functional Specifications.
Audio PHY PLL
•
REFCLK_XIN (25 MHz)
•
•
•
Audio Controller 0/1
Audio AC ‘97 external codec reference clock
SSP controller interface or SSP external
reference clock
LCD Controller
•
LCD_EXT_REF_CLK[1:0]
•
•
LCD Pixel Clock
VGA Pixel Clock
SATA clock (150 MHz)
Table 36 lists the supported combinations of the CPU_CLK Frequency select, CPU_CLK to DDR
CLK ratio, and to CPU_CLK to CPU L2 clock ratio (see Section 7.5, Pins Sample Configuration,
on page 76).
Table 36: Supported Clock Combinations
CPU Clock
(MHz)
CPU to DDR
C l o c k R a t io
CPU to L2
Clock Ratio
D D R C lo c k
(MHz)
400
400
1
1
400
500
500
1
1
500
800
400
2
2
400
1000
500
2
2
500
Note
6.1
L2 Clock
(MHz)
The 400 and 500 MHz clock combinations use the DFS power saving mode that is
configured by the software. For more information, see the “Power Management Unit”
section in the 88AP510 Functional Specifications.
Spread Spectrum Clock Generator (SSCG)
Spread Spectrum Clock generation (SSCG) may be used to generate the spread spectrum clock for
the CPU PLL input. See Section 7.5, Pins Sample Configuration, on page 76, for the
CAM_SNSR_CTL[0] SSCG enable/bypass setting.
SSCG parameters:
„
Down spread 1%, up spread 1%, or +/- 1% center spread
„
Triangular spreading
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Clocking
Clock Topology
6.2
Clock Topology
Figure 5 shows all of the required clocks for the device.
Figure 5: Device Clock Topology
CPU_CLK
SSCG
(optional)
CPU
PLL
CPU
L2 CLK
M_CLK_OUT[1:0]/
M_CLK_OUT[1:0]n
DDR 2/3
Controller
DDR CLK
CORE
PLL
REFCLK_XIN:
25 MHz XTAL
SATA
PHY PLL
AXI
Interconnect
Clock
SDIO Clock
GE Clock
USB PHY
PLL
PEX[1:0]_CLK_P
PEX[1:0]_CLK_N
PCIe
VMeta™
SSP Clock
GPU
LCD_CLK
LCD
LCD_EXT_REF_CLK[1:0]
Camera Clock
TCLK
(Mbus Interconnect Clock)
PMU
SMI Clock
RTC_XIN
RTC
TWSI Clock
SPI Clock
NF Clock
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88AP510
Hardware Specifications
7
System Power Up/Down and Reset
Settings
This section provides information about the 88AP510 power up and power down sequence
requirements and reset behavior.
7.1
Power Sequencing
The following sections provide specific power-up and power-down recommendations for the
88AP510.
7.1.1
Power Up Sequence Requirements
These requirements must be applied to meet the 88AP510 device power-up requirements (system
power off to power on). The reference of the power rail rising point is 70% of the nominal power. For
example, if VDDO_PMU and RTC_AVDD are powered up before VDD_PMU, the VDDO_PMU and
RTC_AVDD power must reach 70% of their nominal power level before VDD_PMU reaches 70% of
its nominal power level.
VDDO_PMU and RTC_AVDD must be powered up before VDD_PMU is powered up.
VDD_PMU must be powered up before VDD_CORE and VDD_CPU. The power up sequence
order between VDD_PMU and the remaining IO/Analog power is not important.
„
VDD_CORE voltage must be powered up within 20 ms after VDDO_M is powered up. VDDO_M
can be powered up after VDD_CORE.
„
VDD_CPU and VDDO_M must be powered up within 10 ms after VDD_CORE is powered up.
„
The remaining I/O and analog voltages listed in Table 37 on page 73 must be powered up
before VDD_CORE voltage is powered up. The power up sequence of the I/O voltages is not
important.
„
VDD_CORE voltage rise time should be less than 2 ms.
„
RTC_XIN must toggle before VDD_PMU is powered up.
„
REFCLK_XIN must toggle before VDD_CORE is powered up.
„
SYSRST_INn must be asserted before the VDD_CORE voltage is powered up. SYSRST_INn
must remain asserted for at least 10 ms after all voltages reach their nominal level.
Figure 6 on page 73 shows an example of the device power up sequence.
„
„
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System Power Up/Down and Reset Settings
Power Sequencing
Table 37: I/O, Analog, and Core Voltages
N o n - C o r e Vol ta g e s
C o r e Vol ta g e s
I/ O Vo lta ge s
A n a lo g P o w e r S up p li e s
VDDO_M
VDDO_PMU
VDDO_AUD
VDDO_CAM
VDDO_GIGA
VDDO_JTAG
VDDO_LCD
VDDO_MPP
VDDO_NF
VDDO_SDIO0/1
RTC_AVDD1
AU_AVDD
CPU_PLL_AVDD
PEX0/1_AVDD
REFCLK_AVDD
S_AVDD
SOC_PLL_AVDD
THERM_AVDD
USB0/1_AVDD
VGA_DAC_AVDD
VGA_DAC_AVDDL
VGA_RGB_AVDD
VDD_PMU
VDD_CORE
VDD_CPU
1. Always on and has a backup battery.
Figure 6: Power Up Sequence
Analog/IO Non-Core
VDDO_PMU/RTC_AVDD
VDD_PMU
VDDO_M
VDD_CORE
VDD_CPU
< 20 ms
< 10 ms
RTC_XIN
>10 ms
SYSRST_INn
REFCLK_XIN
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88AP510
Hardware Specifications
Note
7.1.2
It is the designer's responsibility to verify that the power sequencing requirements of
other components are also met.
Resume Power Up Sequence from Standby Mode
To resume a power up sequence when the device is in Standby mode:
„
VDDO_PMU I/O, VDD_PMU, and RTC_AVDD are already powered up (see Table 38).
„
VDD_CORE voltage must be powered up within 20 ms after VDDO_M is powered up. VDDO_M
can be powered up after VDD_CORE.
„
The remaining I/O and analog voltages listed in Table 37 on page 73 must be powered up
before VDD_CORE core voltage is powered up. The power up sequence of the I/O voltages is
not important.
„
VDD_CORE voltage rise time should be less than 2 ms.
„
VDD_CPU core and VDDO_M IO power good state must be guaranteed within 10 ms after
VDD_CORE power good indication.
„
REFCLK_XIN must toggle before VDD_CORE is powered up.
„
SYSRST_INn must be asserted before the core voltages are powered up, and must remain
asserted for at least 10 ms after all voltages reach their nominal level.
7.1.3
Power Down Requirements
To reduce power consumption, the 88AP510 can be partially powered down, Table 38 lists the power
modes and the supplies that are powered up or powered down in each mode.
There are no sequence requirements to power down the I/O, analog or core supplies, or to assert
SYSRST_INn when powering down.
In Standby mode, when I/O voltages are powered up and the core voltages are powered down:
There is no current drawn by the IO or ESD diodes.
„
The I/O is floating. There is no contention with external inputs.
„
The PMU controls MPP[7:0].
„
The following power supplies must be powered down when the SoC core voltage is powered down:
„
SoC Core PLL (SOC_PLL_AVDD).
„
CPU PLL (CPU_PLL_AVDD)
„
SDRAM DDR interface (VDDO_M)
„
DDR PHY PLL (M_AVDD)
The following PHY AVDD voltages can be powered up while the core voltages are powered down.
Although, it is recommended to power them down to reduce the power consumption.
„
„
„
„
SATA (S_AVDD)
USB (USB<n>_AVDD)
PEX (PEX<n>_AVDD)
REFCLK (REFCLK_AVDD)
Table 38 lists the power supplies status depending on the power mode.
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System Power Up/Down and Reset Settings
Hardware Reset
Table 38: 88AP510 Power Modes
Mode
P ow e r e d U p
P ow e r e d D ow n
Run/Idle
All voltages
None
Deep Idle/eBook
All voltages except for the VDD_CPU
and VDDO_M
VDD_CPU
VDDO_M
Standby
VDDO_PMU
VDD_PMU
RTC_AVDD
All remaining voltages are powered
down. The SDRAM power has to be kept
Hibernate/Off
7.2
RTC_AVDD
powered up to keep it in Self-refresh
mode.
All remaining voltages are powered
down.
Hardware Reset
The 88AP510 includes the following reset pins:
MRn
Manual Reset Input
SYSRST_INn
System Reset Input
SYSRST_OUTn System Reset Output
It can be connected to SYSRST_INn
7.2.1
Reset Inputs
The device has two reset inputs, MRn and SYSRST_INn.
When MRn is asserted, all of the device units, including the PMU, are reset to their default state, and
most of the outputs are at High-Z. SYSRST_OUTn is asserted as long as MRn is asserted.
When SYSRST_INn is asserted, all of the device units except the PMU are reset to their default
state, and most of the outputs are at High-Z.
7.2.2
System Reset Output
The device has a dedicated system reset out signal (SYSRST_OUTn) to reset the board. When
asserted, it remains low for 20 msec.
It is controlled by the internal Power On Reset (POR) unit, and by the MRn signal.
7.2.3
Power On Reset
The 88AP510 has an internal POR circuitry that holds the SYSRST_OUTn signal asserted for
approximately 20 ms when one of the following events occurs:
„
VDD_CORE reaches 40% of its nominal value.
„
Deassertion of MRn. If MRn is asserted, The 88AP510 asynchronously asserts
SYSRST_OUTn, and maintains its assertion until approximately 20 ms after the deassertion of
MRn.
„
The watchdog timer expires.
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88AP510
Hardware Specifications
7.3
PCI Express Reset
The PCI Express interface requires a reset procedure if it is configured as a Root Complex or an
Endpoint.
7.3.1
PCI Express Root Complex Reset
As a Root Complex, the device may generate a Hot Reset to the PCI Express port. Upon CPU
setting the PCI Express Control register’s <ConfMstrHotReset> bit, the PCI Express unit sends a
Hot Reset indication to the Endpoint, see the PCI Express Interface section in the 88AP510
Functional Specifications.
7.3.2
PCI Express Endpoint Reset
When a Hot Reset packet is received:
„
A maskable interrupt is asserted.
„
If the <ConfDisHotResetRegRst> field in the PCI Express Debug Control register is cleared, the
device also resets the PCI Express register file to its default values.
„
The device triggers an internal reset, if not masked by the <ConfMskHotReset> field in the PCI
Express Debug Control register.
Link failure is detected if the PCI Express link was up (LTTSSM L0 state) and dropped back to an
inactive state (LTSSM Detect state). When Link failure is detected:
„
A maskable interrupt is asserted.
„
If the <ConfDisLinkFailRegRst> field in the PCI Express Debug Control register is cleared, the
device also resets the PCI Express register file to its default values.
„
The device triggers an internal reset, if the <ConfMskLinkFail> field is not masked by PCI
Express Debug Control register.
Both link fail and hot reset conditions trigger a chip internal reset (if not masked in the PCI Express
interface). All the chip logic is reset to the default values, except for sticky registers and the sample
on reset logic. In addition, these events can trigger reset to the board, using the SYSRST_OUTn
output—if it is not masked by the <PexRstOutEn> field.
The external reset logic (on the board) may assert the SYSRST_INn input pin and reset the entire
chip.
7.4
Sheeva™ CPU TAP Controller Reset
The Sheeva™ CPU Test Access Port (TAP) controller is reset when JT_RSTn is set and
JT_TMS_CPU is active.
7.5
Pins Sample Configuration
The reset pins are sampled upon SYSRST_INn de-assertion.
External pull up/down resistors are required to change the default mode of operation.
These signals must remain pulled up or down until SYSRST_INn de-assertion (zero hold time in
respect to SYSRST_INn de-assertion).
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System Power Up/Down and Reset Settings
Serial ROM Initialization
Note
If external logic is used instead of pull-up and pull-down resistors, the logic must drive
all of these signals to the desired values during SYSRST_INn assertion. To prevent bus
contention on these pins, the external logic must float the bus no later than the third
TCLK cycle after SYSRST_INn de-assertion.
All reset sampled values are registered in Reset Sample (Low) and Reset Sample
(High) registers (see the CPU Interface Registers in the 88AP510 Functional
Specifications). This is useful for board debug purposes and identification of board and
system settings for the host software.
The reset pins are provided in an Excel file attachment
To open the attached reset pin Excel file, double-click the pin icon below:
88AP510 Reset Strapping
File attachments are only supported by Adobe Reader 6.0 and above.
Note
7.6
To download the latest version of free Adobe Reader go to http://www.adobe.com.
Serial ROM Initialization
TWSI debug port is not mentioned here. It moved to the functional spec.
Note
The 88AP510 device supports initialization of ALL of its internal and configuration registers through
the TWSI0 master interface. If serial ROM initialization is enabled, the 88AP510 TWSI0 master
starts reading initialization data from serial ROM and writes it to the appropriate registers upon
deassertion of SYSRSTn.
7.6.1
Serial ROM Data Structure
Serial ROM data structure consists of a sequence of 32-bit address and 32-bit data pairs, as shown
in Figure 7.
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88AP510
Hardware Specifications
Figure 7: Serial ROM Data Structure
Start
MSB
LSB
address0[31:24]
address0[23:16]
address0[15:8]
address0[7:0]
data0[31:24]
data0[23:16]
data0[15:8]
data0[7:0]
address1[31:24]
address1[23:16]
address1[15:8]
address1[7:0]
data1[31:24]
data1[23:16]
data1[15:8]
data1[7:0]
The serial ROM initialization logic reads eight bytes at a time. It performs address decoding on the
32-bit address being read, and based on address decoding result, writes the next four bytes to the
required target. This scheme enables not only programming of the 88AP510 internal registers, but
also initialization of other system components. The only limitation is that it supports only single 32-bit
writes (no byte enables nor bursts are supported).
The Serial Initialization Last Data Register contains the expected value of last serial data item
(default value is 0xFFFFFFFF). When the 88AP510 device reaches last data, it stops the
initialization sequence.
Note
7.6.2
Users must not generate requests through the TWSI auto-loader to addresses that are
not 32-bit aligned.
Serial ROM Initialization Operation
On SYSRSTn de-assertion, the 88AP510 device starts the initialization process. It first performs a
dummy write access to the serial ROM, with data byte(s) of 0x0, to set the ROM byte offset to 0x0.
Then, it performs the sequence of reads, until it reaches last data item, as shown in Figure 8.
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System Power Up/Down and Reset Settings
Serial ROM Initialization
Figure 8: Serial ROM Read Example
s
t
a
r
t
w
r
i
t
e
s 1 0 1 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Data from
ROM
r
e
a
d
s 1 0 1 0 0 0 0 1
a
c
k
a
c
k
a
c
k
s
t
a
r
t
Lower Byte Offset
Upper Byte Offset
A A A A A A A A
a
c
k
A A A A
a
c
k
ROM
Address
ROM
Address
Last Data
from ROM
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
a
c
k
1 1 1 1 1 1 1 1
a
c
k
s
t
o
p
1 1 1 1 1 1 1 1
a
c
k
x x x x x x x x
a
c
k
p
n
a
c
k
For a detailed description of TWSI implementation, see the Two-Wire Serial Interface section in the
88AP510 Functional Specifications.
„
„
„
„
Initialization data must be programmed in the serial ROM starting at offset 0x0.
The 88AP510 device assumes 7-bit serial ROM address of ‘b1010000.
After receiving the last data identifier (default value is 0xFFFFFFFF), the 88AP510 device
receives an additional byte of dummy data. It responds with no-ack and then asserts the stop
bit.
The serial EEPROM must contain two address offset bytes (It must not be less than a 256 byte
ROM.).
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88AP510
Hardware Specifications
8
JTAG Interface
To enable board testing, the device supports a test mode operation through its JTAG boundary scan
interface.
The JTAG interface is IEEE 1149.1 standard compliant. It supports mandatory and optional
boundary scan instructions.
8.1
TAP Controller
The Test Access Port (TAP) is constructed with a 5-pin interface and a 16-state Finite State Machine
(FSM), as defined by IEEE JTAG standard 1149.1.
To place the device in a functional mode, reset the JTAG state machine to disable the JTAG
interface.
According to the IEEE 1149.1 standard, the JTAG state machine is not reset when the 88AP510
SYSRST_INn is asserted. The JTAG state machine can only be reset by one of the following
methods:
„
Asserting JT_RSTn.
„
Setting JT_TMS_CORE for at least five JT_CLK cycles.
To place the device in one of the boundary scan test mode, the JTAG state machine must be moved
to its control states. JT_TMS_CORE and JT_TDI inputs control the state transitions of the JTAG
state machine, as specified in the IEEE 1149.1 standard. The JTAG state machine will shift
instructions into the Instruction register while in SHIFT-IR state and shift data into and from the
various data registers when in SHIFT-DR state.
8.2
Instruction Register
The Instruction register (IR) is a 4-bit, two-stage register. It contains the command that is shifted in
when the TAP FSM is in the Shift-IR state. When the TAP FSM is in the Capture-IR state, the IR
outputs all four bits in parallel.
Table 39 lists the instructions supported by the device.
Table 39: Supported JTAG Instructions
In s t r u c t io n
C o de
D es c r ip t i o n
HIGHZ
0011
Select the single bit Bypass register between TDI and TDO.
Sets the device output pins to high-impedance state.
IDCODE
0010
Selects the Identification register between TDI and TDO. This 32-bit
register is used to identify the device.
EXTEST
0000
Selects the Boundary Scan register between TDI and TDO. Outputs the
boundary scan register cells to drive the output pins of the device. Inputs
the boundary scan register cell to sample the input pin of the device.
SAMPLE/PRE
LOAD
0001
Selects the Boundary Scan register between TDI and TDO. Samples
input pins of the device to input boundary scan register cells.
Preloads the output boundary scan register cells with the Boundary Scan
register value.
BYPASS
1111
Selects the single bit Bypass register between TDI and TDO. This allows
for rapid data movement through an untested device.
Doc. No. MV-S105141-U0 Rev. F
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JTAG Interface
Bypass Register
8.3
Bypass Register
The Bypass register (BR) is a single bit serial shift register that connects TDI to TDO, when the IR
holds the Bypass command, and the TAP FSM is in Shift-DR state. Data that is driven on the TDI
input pin is shifted out one cycle later on the TDO output pin. The Bypass register is loaded with 0
when the TAP FSM is in the Capture-DR state.
8.4
JTAG Scan Chain
The JTAG Scan Chain is a serial shift register used to sample and drive all of the device pins during
the JTAG tests. It is a 2-bit per pin shift register in the device, thereby allowing the shift register to
sequentially access all of the data pins both for driving and strobing data. For further details, refer to
the BSDL Description file for the device.
8.5
ID Register
The ID register is a 32-bit deep serial shift register. The ID register is loaded with vendor and device
information when the TAP FSM is in the Capture-DR state. The Identification code format of the ID
register is shown in Table 40, which describes the various ID Code fields.
Table 40: IDCODE Register Map
B i ts
Va l u e
Description
31:28
88AP510-A0: 0x6
88AP510-A1: 0x7
Version
27:12
88AP510-A0/A1: 0x0510
Part number
11:1
0x1AB
Manufacturer ID
0
1
Mandatory
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88AP510
Hardware Specifications
9
Electrical Specifications (Preliminary)
The numbers specified in this section are PRELIMINARY and SUBJECT TO CHANGE.
Note
9.1
Absolute Maximum Ratings
Table 41: Absolute Maximum Ratings
Parameter
M in
Max
U ni ts
C o m m e n ts
VDD_CPU
-0.5
1.3
V
CPU subsystem core voltage (CPU, L1 and L2
Caches, VFP and WMMX coprocessors)
VDD_CORE
-0.5
1.2
V
SoC core voltage
VDD_PMU
-0.5
1.2
V
PMU core voltage
VDDO_AUD
-0.5
4.0
V
I/O voltage for:
Audio (S/PDIF, AC ‘97, I2S, SSP) interface
VDDO_CAM
-0.5
4.0
V
I/O voltage for:
Camera interface
VDDO_GIGA
-0.5
4.0
V
I/O voltage for:
RGMII and SMI interface
VDDO_JTAG
-0.5
4.0
V
I/O voltage for:
TWSI, JTAG, and UART interfaces
VDDO_LCD
-0.5
4.0
V
I/O voltage for:
LCD (digital signals) interface
VDDO_PMU
-0.5
4.0
V
I/O voltage for:
MPP[7:0] signals
VDDO_MPP
-0.5
4.0
V
I/O voltage for:
MPP[23:8] signals and SPI interface
VDDO_NF
-0.5
4.0
V
I/O voltage for:
NAND interface
VDDO_SDIO0
VDDO_SDIO1
-0.5
4.0
V
I/O voltage for:
SDIO0 and SDIO1 interfaces
VDDO_M
-0.5
2.2
V
I/O voltage for:
SDRAM DDR2/3 interfaces
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Electrical Specifications (Preliminary)
Absolute Maximum Ratings
Table 41: Absolute Maximum Ratings (Continued)
Parameter
M in
Max
U ni ts
C o m m e n ts
M_VREFS,
M_VREFD
-0.5
1.1
V
I/O reference voltage for:
SDRAM DDR2/3 interfaces
VDDO_VGA
-0.5
4.0
V
I/O voltage for:
LCD Port B (VGA digital signals) interface
VGA_RGB_AVDD
-0.5
3.0
V
Analog supply for:
VGA channels
VGA_DAC_AVDD
-0.5
3.0
V
Analog supply for:
VGA gain DAC
VGA_DAC_AVDDL
-0.5
2.2
V
Analog supply for:
VGA DAC reference generator
PEX0_AVDD
PEX1_AVDD
-0.5
2.2
V
Analog supply for:
PCI Express interface
USB0_AVDD
USB1_AVDD
-0.5
4.0
V
Analog supply for:
USB interface
S_AVDD
-0.5
3.0
V
Analog supply for:
SATA interface
REFCLK_AVDD
-0.5
3.0
V
Analog supply for:
Crystal Controller
SOC_PLL_AVDD
-0.5
2.2
V
Analog supply for:
Spread Spectrum Controller and SoC PLL
RTC_AVDD
-0.5
2.2
V
Analog supply for:
RTC unit
THERM_AVDD
-0.5
2.2
V
Analog supply for:
Thermal Sensor
CPU_PLL_AVDD
-0.5
2.2
V
Analog supply for:
CPU PLL
AU_AVDD
-0.5
2.2
V
Analog supply for:
Audio DCO
TC
-40
125
°C
Case temperature
TSTG
-40
125
°C
Storage temperature
„
„
Caution
Exposure to conditions at or beyond the maximum rating may damage the device.
Operation beyond the recommended operating conditions (Table 42) is neither
recommended nor guaranteed.
Copyright © 2011 Marvell
July 13, 2011, Preliminary
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88AP510
Hardware Specifications
Note
Before designing a system, it is recommended that you read application note AN-63:
Thermal Management for Marvell Technology Products. This application note presents
basic concepts of thermal management for integrated circuits (ICs) and includes
guidelines to ensure optimal operating conditions for Marvell Technology's products.
Doc. No. MV-S105141-U0 Rev. F
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Electrical Specifications (Preliminary)
Recommended Operating Conditions
9.2
Recommended Operating Conditions
Table 42: Recommended Operating Conditions
Parameter
Min
Ty p
Max
U ni ts
C o m m e n ts
VDD_CPU
(400/500 MHz)
0.95
1.0
1.05
V
CPU subsystem voltage
VDD_CPU
(800 MHz)
1.05
1.1
1.15
V
VDD_CPU
(1 GHz)
1.1
1.14
1.17
V
VDD_CORE
(800 MHz)
0.95
1.0
1.05
V
VDD_CORE
(1 GHz)
0.975
1.025
1.075
V
VDD_PMU
0.95
1.0
1.05
V
PMU voltage
VDDO_AUD
3.15
3.3
3.45
V
I/O voltage for:
Audio (S/PDIF, AC ‘97, I2S, SSP)
interface
VDDO_CAM
3.15
3.3
3.45
V
I/O voltage for:
Camera interface
2.3
2.5
2.7
V
1.7
1.8
1.9
V
3.15
3.3
3.45
V
2.375
2.5
2.625
V
1.7
1.8
1.9
V
VDDO_JTAG
3.15
3.3
3.45
V
I/O voltage for:
TWSI, JTAG, and UART
interfaces
VDDO_LCD
3.15
3.3
3.45
V
I/O voltage for:
LCD interface
2.3
2.5
2.7
V
1.7
1.8
1.9
V
VDDO_PMU
3.15
3.3
3.45
V
I/O voltage for:
MPP[7:0] (PMU) signals
VDDO_MPP
3.15
3.3
3.45
V
I/O voltage for:
MPP[23:8] signals and SPI
interface
VDDO_NF
3.15
3.3
3.45
V
I/O voltage for:
NAND interface
1.7
1.8
1.9
V
VDDO_GIGA
Copyright © 2011 Marvell
July 13, 2011, Preliminary
SoC Core voltage
I/O voltage for:
RGMII and SMI interfaces
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88AP510
Hardware Specifications
Table 42: Recommended Operating Conditions (Continued)
Parameter
Min
Ty p
Max
U ni ts
C o m m e n ts
VDDO_SDIO0
VDDO_SDIO1
3.15
3.3
3.45
V
I/O voltage for:
SDIO interface
1.7
1.8
1.9
V
1.7
1.8
1.9
V
I/O voltage for:
SDRAM DDR2 interfaces
1.425
1.5
1.575
V
I/O voltage for:
SDRAM DDR3 and DDR2
interfaces
1.283
1.35
1.417
V
I/O voltage for:
SDRAM DDR3 interface
M_VREFS,
M_VREFD
0.49*VDDO_M
0.5*VDDO_M
0.51*VDDO_M
V
I/O reference voltage for:
SDRAM DDR2/3
VDDO_VGA
3.15
3.3
3.45
V
2.3
2.5
2.7
V
1.7
1.8
1.9
V
I/O voltage for:
VGA (digital signals) interface
NOTE: Apply typical 3.3V for
VGA digital signals and
the LCD external
reference clock.
VGA_RGB_AVDD
2.375
2.5
2.625
V
Analog supply for:
VGA channels
VGA_DAC_AVDD
2.375
2.5
2.625
V
Analog supply for:
VGA gain DAC
VGA_DAC_AVDDL
1.7
1.8
1.9
V
Analog supply for:
VGA DAC reference generator
PEX0_AVDD
PEX1_AVDD
1.7
1.8
1.9
V
Analog supply for:
PCI Express interface
USB0_AVDD
USB1_AVDD
3.15
3.3
3.45
V
Analog supply for:
USB interface
S_AVDD
2.375
2.5
2.625
V
Analog supply for:
SATA interface
REFCLK_AVDD
2.375
2.5
2.625
V
Analog supply for:
Crystal Controller
SOC_PLL_AVDD
1.7
1.8
1.9
V
Analog supply for:
Spread Spectrum Controller and
SoC PLL
RTC_AVDD
1.7
1.8
2.0
V
Analog supply for:
RTC unit (Regular mode)
1.2
1.5
1.7
V
Analog supply for:
RTC unit (Battery Back-up mode)
VDDO_M
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Electrical Specifications (Preliminary)
Recommended Operating Conditions
Table 42: Recommended Operating Conditions (Continued)
Parameter
Min
Ty p
Max
U ni ts
C o m m e n ts
THERM_AVDD
1.7
1.8
1.9
V
Analog supply for:
Thermal sensor
CPU_PLL_AVDD
1.7
1.8
1.9
V
Analog supply for:
CPU PLL
AU_AVDD
1.7
1.8
1.9
V
Analog supply for:
Audio analog
TJ
0
105
°C
Junction Temperature
Caution
Operation beyond the recommended operating conditions is neither recommended nor
guaranteed.
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88AP510
Hardware Specifications
9.3
Thermal Power Dissipation
To allow for the continuous operation and long-term reliability of Marvell® 88AP510 based systems,
design the system/device thermal solution so the device remains within the minimum and maximum
junction temperature (Tj) specifications. The average thermal power dissipation values are listed in
the following tables:
„
Table 43, CPU Subsystem Power Dissipation, on page 88
„
Table 44, SoC Core Power Dissipation, on page 89
„
Table 45, I/O Interfaces Power Dissipation, on page 89
„
Table 46, SoC Power Dissipation for Low Power Modes, on page 93
The 88AP510 must maintain the junction temperatures within the operating limits of the
recommended operating conditions listed in Table 42, Recommended Operating Conditions, on
page 85. A thermal solution that does not provide this level of thermal capability can affect the
long-term operation and reliability of the device.
Note
9.3.1
Analysis indicates that under real applications, the device does not consume the
theoretical maximum power dissipation listed in Table 47, Maximum Current
Consumption, on page 94 for sustained time periods.
CPU Subsystem Power Dissipation
Table 43 lists the 88AP510 CPU subsystem power dissipation for several applications when the
device is in the Run power mode.
Table 43: CPU Subsystem Power Dissipation
P VDD_CPU Power2
A p p li c a ti on
C PU
F r e q u en c y 1
(MHz)
EEMBC 1.1 Benchmark Suite
800
1.63 (Tj = 105° C )
1.35 (Tj = 65°C )
W
1000
1.95 (Tj = 105° C )
1.75 (Tj = 65°C )
W
800
0.85 (Tj = 105° C )
0.6 (Tj = 65° C )
W
1000
1.0 (Tj = 105° C )
0.8 (Tj = 65° C )
W
Video Decoding
(Mplayer/GStreamer, Full HD)
U n i ts
Notes:
General Note: The power dissipation values are provided for the specified frequency and under the
nominal recommended voltage.
1.
2.
At CPU:L2 ratio of 2:1.
Average power dissipation values at the specified Tj.
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Electrical Specifications (Preliminary)
Thermal Power Dissipation
9.3.2
SoC Core Power Dissipation
Table 44, lists the 88AP510 SoC Core power dissipation for several applications.
Table 44: SoC Core Power Dissipation
C o nf ig u r a ti on 1
A p p l ic a t io n
PVDD_CORE P o w e r 2
U n i ts
V M e ta ™
G PU
Typical (non-multimedia)
OFF
OFF
0.63 (Tj = 105° C )
0.5 (Tj = 65° C )
W
Video Decoding
(Mplayer/GStreamer, Full HD)
ON
OFF
1.05 (Tj = 105° C )
0.8 (Tj = 65° C )
W
3D Graphics (Full HD)
OFF
ON
1.05 (Tj = 105° C )
0.8 (Tj = 65° C )
W
3D Graphics/Video Decoding
(Full HD)
ON
ON
1.4(Tj = 105° C )
1.0 (Tj = 65° C )
W
Notes:
General Note: The power dissipation values are provided for the specified configuration and under
the nominal recommended voltage.
1.
2.
9.3.3
SoC Core frequency (Tclk) of 166 MHz. ON and OFF refer to power island up and down,
respectively.
Average power dissipation values at the specified Tj.
I/O Power Dissipation per Interface
Table 45 lists the 88AP510 I/O power dissipation per interface under several operating conditions,
when the device is in the Run power mode. The total 88AP510 I/O power dissipation for a given
system can be calculated using this table.
.
Table 45: I/O Interfaces Power Dissipation
In t e r f a c e
Sy m b o l
C o n fi gu ra t io n 1
Typ
Units
RGMII interface
PRGMII_3.3
3.3V interface (1000 Mbps)
90
mW
PRGMII_2.5
2.5V interface (1000 Mbps)
60
mW
PRGMII_1.8
1.8V interface (1000 Mbps)
30
mW
PRGMII_FE
10/100 Mbps
10
mW
PDDR2_1.8V
32-bit, 400 MHz
750
mW
16-bit, 400 MHz
460
mW
32-bit, 400 MHz
500
mW
16-bit, 400 MHz
300
mW
DDR2 SDRAM 1.8V interface2
DDR2 SDRAM 1.5V interface2
PDDR2_1.5V
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88AP510
Hardware Specifications
Table 45: I/O Interfaces Power Dissipation (Continued)
In t e r f a c e
Sy m b o l
C o n fi gu ra t io n 1
Typ
Units
DDR3 SDRAM 1.5V interface2
PDDR3_1.5V
32-bit, 500 MHz
550
mW
32-bit, 400 MHz
500
mW
16-bit, 500 MHz
340
mW
16-bit, 400 MHz
300
mW
32-bit, 400 MHz
400
mW
16-bit, 400 MHz
240
mW
DDR3 SDRAM 1.35V interface2
PDDR3_1.35V
Miscellaneous IO Interface (TWSI, JTAG, UART,
SDIO, SPI, Audio, SSP, and MPP[23:0])
PMISC
3.3V
50
mW
NAND Flash Interface
PNF
3.3V 16-bit I/O 33 MHz
20
mW
PCI Express interface3
PPEX
Power up (with Clock Out)
130
mW
Power up (without Clock Out)
100
mW
Power down
20
mW
Power up
100
mW
Power down
5
mW
Power up
205
mW
Power down
5
mW
3.3 (Up to 100 MHz)
220
mW
2.5V (Up to 100 MHz)
130
mW
1.8V (Up to 166 MHz)
100
mW
USB interface3
PUSB
SATA interface
PSATA
LCD interface
PLCD
VGA interface
PVGA
Power up
375
mW
Camera interface
PCAMERA
1.8/2.5/3.3V (Up to 50 MHz)
15
mW
CPU PLL
PPLL_CPU
30
mW
SoC PLL
PPLL_SOC
30
mW
Notes:
1.
The power dissipation values are provided for the specified configuration and at Tj = 105°C.
2.
The power of the DDR interface includes the 88AP510 consumption, and does not include the
SDRAM device. The power consumption assumes on board SDRAM topology using two Chip
Selects (CS), The power of the DDR interface includes the 88AP510 consumption, and does
not include the SDRAM device, x8 SDRAM devices.
The power is for a single port.
3.
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Electrical Specifications (Preliminary)
Thermal Power Dissipation
9.3.4
SoC Power Dissipation for Power Management Unit Low
Power Modes
The 88AP510 Power Management Unit (PMU) controls power management functions and enables
the optimization of the device’s overall power consumption and performance.
The PMU allows for four low power modes that supply different levels of power consumption with
hardware controlling wake-up events and power mode transitions:
„
Deep Idle
„
eBook
„
Standby
„
Hibernate
For more details on the 88AP510 power modes and additional PMU features, refer to the Power
Management Unit section of the 88AP510 Functional Specifications.
Figure 9 illustrates the core power domains/islands, and the main I/O and PHY power domains. The
full list of core, I/O, and Analog power domains are listed in Table 41.
Copyright © 2011 Marvell
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88AP510
Hardware Specifications
Figure 9: 88AP510 Power Domains
VGA
VGA Analog
CPU Subsystem Power Domain
DDR2/3
VDDO_M
SheevaTM
CPU
ARMv6/v7
VDD_CPU
32-KB L1
I-Cache
FPU V3.0
Display
Controller
VDDO_VGA
VDDO_LCD
32-KB L1
D-Cache
WMMX2
SPI + PWM
SoC Core
Power Domain
VDD_CORE
Camera
VDDO_CAM
512 KB L2 Cache
BootROM
TWSI
NAND Flash
VDDO_NF
GPU
2D/3D Graphics
VDO_MPP
SPI
VMeta™
HD Video Decoder
H264, VC-1,
`
MPEG2
VDD_CORE
Power Island
VDDO_
SDIO0/1
SDIO
VDDO_MPP/
VDDO_AUD
SSP
VDDO_JTAG
TWSI
VDDO_JTAG
UART
VDDO_MPP
MPP[23:8]
VDDO_PMU
MPP[7:0]
VDD_CORE
Power Island
Cryptographic
Engine and
Security
Accelerator
AES, DES, 3DES,
SHA-1, MD5
Two XOR/DMA
Engines
Audio
AC ‘97/I2S
VDDO_AUD
Audio
I2S / S/PDIF
GbE MAC
VDDO_GIGA
USB 2.0 HS
USB0/1_AVDD
PCIe x1
PEX0/1_AVDD
SATA 2.0
S_AVDD
Power Management Unit
Power Domain
RTC
VDD_PMU
Legend
Core Logic Voltage
I/O Voltage or PHY Analog Supply
As illustrated in Figure 9, the 88AP510 includes three core power domains (CPU, SoC core, and
PMU) and five power islands (CPU, Core, VMeta™, GPU, and PMU) that support various power
modes (the Run mode and low power modes). For further information about the PMU, refer to the
Power Management Unit section of the 88AP510 Functional Specifications.
Table 46 lists the 88AP510 power dissipation for the four low power modes.
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Electrical Specifications (Preliminary)
Thermal Power Dissipation
.
Table 46: SoC Power Dissipation for Low Power Modes
D e v ic e c o n f i g u r a t i o n 1
Po w er M o d e
Power2
C PU
SoC
Core
PMU
D D R I/ O
U ni ts
Idle
CPU
Core
PMU
LCD interface
DDR interface4
WFI3
ON
ON
ON
400 MHz
200
400
1
DDR2:
400
DDR3:
270
mW
Deep Idle
CPU
Core
PMU
LCD interface
DDR interface
OFF
ON
ON
OFF
400 MHz
SRM6, 7
0
350
1
DDR2: 60
DDR3: 45
mW
eBook
CPU
Core
PMU
LCD interface
DDR interface
OFF
ON
ON
ON
400 MHz
0
350
1
DDR2:
380
DDR3:
250
mW
Standby
CPU
Core
PMU
LCD interface
DDR interface
OFF
OFF
ON
OFF
SRM6, 7
0
0
1
0
mW
Hibernate
CPU
Core
PMU
LCD interface
DDR interface
RTC
OFF
OFF
OFF
OFF
OFF
ON
0
0
2.59
0
µW
Notes:
General Note: The power dissipation values are provided for the specified frequency and under the
nominal recommended voltage.
1.
2.
3.
4.
5.
6.
7.
ON is for power up according to recommended operating conditions.
OFF is for power down. It is assumed that in all low power modes the VMeta™ and GPU
interfaces are powered down.
At room temperature (ambient).
The CPU is in a Wait for Interrupt (WFI) low power state (also called CPU “sleep” mode). The
context is maintained but clocks are gated.
32-bit DDR2/DDR3.
32-bit DDR configured for Self-refresh Mode (SRM).
VDDO_M is powered down.
Current drawn from the RTC backup battery (RTC_AVDD at 1.5V).
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88AP510
Hardware Specifications
9.4
Maximum Current Consumption
The purpose of this table is to support board power design and power module selection.
Note
.
Table 47: Maximum Current Consumption
C o r e / In t e r f a c e
S y m bo l
O pe r a tin g C o nd i tio n s
Max
Units
CPU
IVDD_CPU
CPU Core @ 800 MHz
L2 cache @ 400 MHz
2000
mA
CPU Core @ 1000 MHz
L2 cache @ 500 MHz
2400
mA
SoC Core (with GPU/VMeta)
IVDD_CORE
2500
mA
SoC Core (without GPU/VMeta)
IVDD_CORE
1500
mA
PMU (including interface)
IPMU
2
mA
RGMII 3.3V interface
IRGMII_3.3
50
mA
RGMII 1.8V interface
IRGMII_1.8
25
mA
DDR2 SDRAM interface (32-bit 400 MHz)
IDDR2
Dual rank SO-DIMM load
1000
mA
DDR3 SDRAM interface (32-bit 400 MHz)
IDDR3_400
Dual rank SO-DIMM load
680
mA
DDR3 SDRAM interface (32-bit 533 MHz)
IDDR3_533
Dual rank SO-DIMM load
800
mA
UART 3.3V interface (Including MPP)
IUART
25
mA
SPI Interface
ISPI
25
mA
TWSI Interface
ITWSI
25
mA
JTAG 3.3V 10 MHz interface
IJTAG
25
mA
PCI Express interface
IPEX
70
mA
USB interface
IUSB
40
mA
SATA interface
ISATA
65
mA
LCD interface
ILCD
70
mA
VGA interface
IVGA
150
mA
Audio digital interface
IAUDIO_D
25
mA
Audio analog interface
IAUDIO_A
20
mA
RTC interface
IRTC
3
µA
20 pf load
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Maximum Current Consumption
Table 47: Maximum Current Consumption (Continued)
C o r e / In t e r f a c e
S y m bo l
Camera interface
O pe r a tin g C o nd i tio n s
Max
Units
ICAMERA
25
mA
SDIO interface
ISDIO
25
mA
NAND interface
INF
25
mA
CPU PLL
IPLL_CPU
20
mA
SoC PLL
IPLL_SOC
20
mA
Notes:
1.
2.
3.
4.
Tj = 105°C.
Current in mA is calculated using maximum recommended VDDO specification for each power
rail.
All output clocks toggling at their specified rate.
Maximum drawn current from the power supply. Do not use these numbers for power
consumption or thermal design.
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Hardware Specifications
9.5
DC Electrical Specifications
See the Pin Description Section for internal pullup/pulldown,
Note
9.5.1
General 3.3V (CMOS) DC Electrical Specifications
The DC electrical specifications in Table 48 are applicable for the following interfaces and signals:
„
RGMII
„
SMI
„
LCD
„
VGA (digital signals)
„
Camera
„
Audio interface (S/PDIF, AC ‘97, I2S)
„
JTAG
„
MPP[23:0]
„
SDIO
„
SSP
„
UART
„
TWSI (port option 2, 3)
„
SPI_1 and SPI_2 interfaces
In Table 48, VDDIO means the VDDO_AUD, VDDO_CAM, VDDO_GIGA, VDDO_JTAG,
VDDO_LCD, VDDO_VGA, VDDO_MPP, VDDO_PMU, and VDDO_SDIO power rails.
Table 48: General 3.3V Interface (CMOS) DC Electrical Specifications
Param eter
Sym bol
Test Condition
Min
Typ
Max
Units Notes
Input low level
VIL
-0.3
0.8
V
-
Input high level
VIH
2.0
VDDIO+0.3
V
-
Output low level
VOL
IOL = 8 mA
-
0.6
V
-
Output high level
VOH
IOH = -8 mA
2.2
-
V
-
0 < VIN < VDDIO
-10
10
uA
1, 2
pF
-
Input leakage current
Pin capacitance
IIL
Cpin
5
Notes:
1. While I/O is in High-Z.
2. This current does not include the current flow ing through the pullup/pulldow n resistor.
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Electrical Specifications (Preliminary)
DC Electrical Specifications
9.5.2
General 2.5V (CMOS) DC Electrical Specifications
The DC electrical specifications in Table 48 are applicable for the following interfaces and signals:
„
RGMII
„
SMI
„
LCD
„
VGA (digital signals)
„
Camera
„
REFCLK_XIN
In Table 49, VDDIO means the VDDO_CAM, VDDO_GIGA, VDDO_LCD and VDDO_VGA power
rails.
Table 49: General 2.5V Interface (CMOS) DC Electrical Specifications
Param eter
Sym bol
Test Condition
Min
Typ
Max
Units Notes
Input low level
VIL
-0.3
0.7
V
-
Input high level
VIH
1.7
VDDIO+0.3
V
-
Output low level
VOL
IOL = 8 mA
-
0.6
V
-
Output high level
VOH
IOH = -8 mA
1.8
-
V
-
Input leakage current
IIL
0 < VIN < VDDIO
-10
10
uA
1, 2
Pin capacitance
Cpin
pF
-
5
Notes:
1. While I/O is in High-Z.
2. This current does not include the current flow ing through the pullup/pulldow n resistor.
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Hardware Specifications
9.5.3
General 1.8V (CMOS) DC Electrical Specifications
The DC electrical specifications in Table 50 are applicable for the following interfaces and signals:
„
RGMII
„
SMI
„
LCD
„
VGA (digital signals)
„
Camera
„
SDIO
In Table 50, VDDIO means the VDDO_GIGA, VDDO_LCD, VDDO_VGA power rails.
Table 50: General 1.8V Interface (CMOS) DC Electrical Specifications
Param eter
Sym bol
Test Condition
Min
Typ
Max
Units Notes
Input low level
VIL
-0.3
0.35*VDDIO
V
-
Input high level
VIH
0.65*VDDIO
VDDIO+0.3
V
-
Output low level
VOL
IOL = 8 mA
-
0.45
V
-
Output high level
VOH
IOH = -8 mA
VDDIO-0.45
-
V
-
Input leakage current
IIL
0 < VIN < VDDIO
10
uA
1, 2
Pin capacitance
Cpin
pF
-
-10
5
Notes:
1. While I/O is in High-Z.
2. This current does not include the current flow ing through the pullup/pulldow n resistor.
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Electrical Specifications (Preliminary)
DC Electrical Specifications
9.5.4
SDRAM DDR2 1.5V Interface DC Electrical Specifications
In Table 52, VDDIO means the VDDO_M power rail, and VREF means M_VREFD.
Table 51: SDRAM DDR2 1.5V Interface DC Electrical Specifications
Param eter
Sym bol
Test Condition
Min
Typ
Max
Units Notes
Input low level
VIL
-
-0.3
VREF - 0.125
V
-
Input high level
VIH
-
VREF + 0.125
VDDIO + 0.3
V
-
Output low level
VOL
IOL = 13.4 mA
0.3
V
-
Output high level
VOH
IOH = -13.4 mA
V
-
Rtt effective impedance value
RTT
See note 2
Deviation of VM w ith respect to VDDQ/2
Input leakage current
Pin capacitance
dVm
IIL
Cpin
1.2
120
150
180
ohm
1,2
60
75
90
ohm
1,2
See note 3
-6
6
%
3
0 < VIN < VDDIO
-10
10
uA
4, 5
pF
-
-
4.5
Notes:
1. See SDRAM functional description section for ODT configuration.
2. Measurement definition for RTT: Apply VREF +/- 0.25 to input pin separately,
then measure current I(VREF + 0.25) and I(VREF - 0.25) respectively.
RTT =
0 .5
I (VREF + 0.25 ) − I (VREF
− 0.25 )
3. Measurement definition for VM: Measured voltage (VM) at input pin (midpoint) w ith no load.
⎛ 2 × Vm
⎞
− 1 ⎟ × 100 %
dVM = ⎜
⎝ VDDIO
⎠
4. While I/O is in High-Z.
5. This current does not include the current flow ing through the pullup/pulldow n resistor.
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Hardware Specifications
9.5.5
SDRAM DDR2 1.8V Interface DC Electrical Specifications
In Table 52, VDDIO means the VDDO_M power rail, and VREF means M_VREFD.
Table 52: SDRAM DDR2 1.8V Interface DC Electrical Specifications
Param eter
Sym bol
Test Condition
Min
Typ
Max
Units Notes
Input low level
VIL
-
-0.3
VREF - 0.125
V
-
Input high level
VIH
-
VREF + 0.125
VDDIO + 0.3
V
-
Output low level
VOL
IOL = 13.4 mA
0.3
V
-
Output high level
VOH
IOH = -13.4 mA
V
-
Rtt effective impedance value
RTT
See note 2
Deviation of VM w ith respect to VDDQ/2
Input leakage current
Pin capacitance
dVm
IIL
Cpin
1.4
120
150
180
ohm
1,2
60
75
90
ohm
1,2
See note 3
-6
6
%
3
0 < VIN < VDDIO
-10
10
uA
4, 5
pF
-
-
4.5
Notes:
1. See SDRAM functional description section for ODT configuration.
2. Measurement definition for RTT: Apply VREF +/- 0.25 to input pin separately,
then measure current I(VREF + 0.25) and I(VREF - 0.25) respectively.
RTT =
0 .5
I (VREF + 0.25 ) − I (VREF
− 0.25 )
3. Measurement definition for VM: Measured voltage (VM) at input pin (midpoint) w ith no load.
⎛ 2 × Vm
⎞
− 1 ⎟ × 100 %
dVM = ⎜
⎝ VDDIO
⎠
4. While I/O is in High-Z.
5. This current does not include the current flow ing through the pullup/pulldow n resistor.
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Electrical Specifications (Preliminary)
DC Electrical Specifications
9.5.6
SDRAM DDR3 1.35V Interface DC Electrical Specifications
In Table 54, VDDIO means the VDDO_M power rail, and VREF means M_VREFD.
Table 53: SDRAM DDR3 1.35V Interface DC Electrical Specifications
Param eter
Sym bol
Test Condition
Min
Typ
Max
Units Notes
Single ended input low level
VIL
-0.3
VREF - 0.100
V
-
Single ended input high level
VIH
VREF + 0.100
VDDIO + 0.3
V
-
Differential input low level
VDIL
Note 6
-0.2
V
6
Differential input high level
VDIH
0.2
Note 6
V
6
Output low level
VOL
See note 7
Output high level
VOH
See note 7
0.8*VDDIO
Rtt effective impedance value
RTT
See note 2
48
Deviation of VM w ith respect to VDDQ/2
dVm
See note 3
-5
0 < VIN < VDDIO
-10
Input leakage current
Pin capacitance
IIL
Cpin
0.2*VDDIO
-
60
4.5
V
7
V
7
72
ohm
1,2
5
%
3
10
uA
4, 5
pF
-
Notes:
1. See SDRAM functional description section for ODT configuration.
2. Measurement definition for RTT: Apply VREF +/- 0.25 to input pin separately,
then measure current I(VREF + 0.25) and I(VREF - 0.25) respectively.
RTT =
0. 35
I (VREF + 0.175 ) − I (VREF −0 .175 )
3. Measurement definition for VM: Measured voltage (VM) at input pin (midpoint) w ith no load.
⎞
⎛ 2 × Vm
dVM = ⎜
− 1 ⎟ × 100 %
⎠
⎝ VDDIO
4. While I/O is in High-Z.
5. This current does not include the current flow ing through the pullup/pulldow n resistor.
6. Limitations are same as for single ended signals.
7. Defined w hen driver impedance is calibrated to 21 Ohm.
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9.5.7
SDRAM DDR3 1.5V Interface DC Electrical Specifications
In Table 54, VDDIO means the VDDO_M power rail, and VREF means M_VREFD.
Table 54: SDRAM DDR3 1.5V Interface DC Electrical Specifications
Param eter
Sym bol
Test Condition
Min
Typ
Max
Units Notes
Single ended input low level
VIL
-0.3
VREF - 0.100
V
-
Single ended input high level
VIH
VREF + 0.100
VDDIO + 0.3
V
-
Differential input low level
VDIL
Note 6
-0.2
V
6
Note 6
V
6
0.2*VDDIO
V
7
V
7
ohm
1,2
Differential input high level
VDIH
Output low level
VOL
See note 7
Output high level
VOH
See note 7
0.8*VDDIO
Rtt effective impedance value
RTT
See note 2
48
Deviation of VM w ith respect to VDDQ/2
dVm
Input leakage current
Pin capacitance
IIL
Cpin
0.2
60
72
See note 3
-5
5
%
3
0 < VIN < VDDIO
-10
10
uA
4, 5
pF
-
-
4.5
Notes:
1. See SDRAM functional description section for ODT configuration.
2. Measurement definition for RTT: Apply VREF +/- 0.25 to input pin separately,
then measure current I(VREF + 0.25) and I(VREF - 0.25) respectively.
RTT =
0. 35
I (VREF + 0.175 ) − I (VREF −0 .175 )
3. Measurement definition for VM: Measured voltage (VM) at input pin (midpoint) w ith no load.
⎛ 2 × Vm
⎞
dVM = ⎜
− 1 ⎟ × 100 %
⎝ VDDIO
⎠
4. While I/O is in High-Z.
5. This current does not include the current flow ing through the pullup/pulldow n resistor.
6. Limitations are same as for single ended signals.
7. Defined w hen driver impedance is calibrated to 21 Ohm.
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DC Electrical Specifications
9.5.8
TWSI 3.3V DC Electrical Specifications
In Table 55, VDDIO means the VDDO_JTAG power rail.
Table 55: TWSI Interface 3.3V DC Electrical Specifications
Param eter
Sym bol
Test Condition
Min
Typ
Max
Units Notes
Input low level
VIL
-0.5
0.3*VDDIO
V
-
Input high level
VIH
0.7*VDDIO
VDDIO+0.5
V
-
Output low level
VOL
IOL = 3 mA
-
0.4
V
-
Input leakage current
IIL
0 < VIN < VDDIO
10
uA
1, 2
Pin capacitance
Cpin
pF
-
-10
5
Notes:
1. While I/O is in High-Z.
2. This current does not include the current flow ing through the pullup/pulldow n resistor.
9.5.9
Serial Peripheral Interface (SPI) 3.3V DC Electrical
Specifications
In Table 56, VDDIO means the VDDO_MPP power rail.
Table 56: SPI Interface 3.3V DC Electrical Specifications
Param eter
Input low level
Sym bol
Test Condition
VIL
Min
Typ
Max
Units Notes
-0.5
0.3*VDDIO
V
-
Input high level
VIH
0.7*VDDIO
VDDIO+0.5
V
-
Output low level
VOL
IOL = 4 mA
-
0.4
V
-
Output high level
VOH
IOH = -4 mA
VDDIO-0.6
-
V
-
Input leakage current
IIL
0 < VIN < VDDIO
-10
10
uA
1, 2
Pin capacitance
Cpin
pF
-
5
Notes:
1. While I/O is in High-Z.
2. This current does not include the current flow ing through the pullup/pulldow n resistor.
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9.5.10
NAND Flash 3.3V DC Electrical Specification
In Table 57, VDDIO means the VDDO_NF power rail.
Table 57: NAND Flash 3.3V DC Electrical Specification
Param eter
Sym bol
Test Condition
Min
Typ
Max
Units Notes
Input low level
VIL
-0.3
0.8
V
-
Input high level
VIH
2.0
VDDIO+0.3
V
-
Output low level
VOL
IOL = 2 mA
-
0.4
V
-
Output high level
VOH
IOH = -2 mA
0.85 * VDDIO
-
V
-
-10
10
uA
1, 2
pF
-
Input leakage current
IIL
Pin capacitance
0 < VIN < VDDIO
Cpin
5
Notes:
1. While I/O is in High-Z.
2. This current does not include the current flow ing through the pullup/pulldow n resistor.
9.5.11
NAND Flash 1.8V DC Electrical Specification
In Table 57, VDDIO means the VDDO_NF power rail.
Table 58: NAND Flash 1.8V DC Electrical Specification
Param eter
Sym bol
Test Condition
Min
Typ
Max
Units Notes
Input low level
VIL
-0.3
0.35*VDDIO
V
-
Input high level
VIH
0.65*VDDIO
VDDIO+0.3
V
-
Output low level
VOL
IOL = 2 mA
-
0.45
V
-
Output high level
VOH
IOH = -2 mA
0.85 * VDDIO
-
V
-
Input leakage current
IIL
0 < VIN < VDDIO
-10
10
uA
1, 2
Pin capacitance
Cpin
pF
-
5
Notes:
1. While I/O is in High-Z.
2. This current does not include the current flow ing through the pullup/pulldow n resistor.
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Electrical Specifications (Preliminary)
AC Electrical Specifications
9.6
AC Electrical Specifications
See 9.7 "Differential Interface Electrical Characteristics" on page 147 for differential interface
specifications.
9.6.1
Reference Clock and Reset AC Timing Specifications
Table 59: Reference Clock and Reset AC Timing Specifications
D e s c r i p t io n
Sy m b o l
Min
Max
U n i ts
Notes
C o r e R e f e r e n c e C l o c k ( C r y s ta l )
25
MHz
Frequency
FREFCLK_XIN
Accuracy
AREFCLK_XIN
-100
100
ppm
Clock duty cycle
DCREFCLK_XIN
40
60
%
RTC Reference Clock
Frequency (Crystal)
FRTC_XIN
32.768
kHz
3
FAU0_I2S_EXT_MCLK
FAU1_I2S_EXT_MCLK
256 X Fs
kHz
4
I2S Bit Clock Frequency
FAU0_I2SBCLK_DOUT
FAU1_I2SBCLK
64 X Fs
kHz
4
I2S Master Clock Frequency
FAU0_I2SMCLK_RSTN
FAU1_I2SMCLK
256 X Fs
kHz
4
24.567
MHz
5
A u d io E x te r na l R e fe r e n c e C lo c k
Audio External Reference Clock
Frequency
I 2 S O u tp u t C l oc k
A C ‘ 9 7 S y s t e m O u t p u t C lo c k
AC ‘97 System Clock Frequency
FAU0_SYSCLK_OUT
AC '97 Bit Clock Frequency
FAU0_I2SDO_BCLK
12.288
MHz
SP I O ut pu t C l o c k
SPI Output Frequency
FSPI_SCK
TCLK/480
41.6
MHz
SPI_1 Output Frequency
FSPI_1_SCK
TCLK/480
27.8
MHz
SPI_2 Output Frequency
FSPI_2_SCK
FLCD_CLK/256
FLCD_CLK/2
MHz
S M I M a s t e r M o d e R e f e r e n c e C l o ck
SMI Output MDC Clock
FGE_MDC
TCLK/128
MHz
TCLK/1,600
MHz
T WS I M a s t er M o d e R e fe re n c e C lo c k
SCK Output Frequency
FTW_SCK
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Table 59: Reference Clock and Reset AC Timing Specifications (Continued)
D e s c r i p t io n
Sy m b o l
Min
Max
U n i ts
Notes
LCD Clocks
LCD PortA Output Frequency (1.8V)
FLCD_CLK
166
MHz
6
LCD PortA Output Frequency (2.5V)
FLCD_CLK
100
MHz
6
LCD PortA Output Frequency (3.3V)
FLCD_CLK
100
MHz
6, 7
LCD External Reference Clock
FLCD_EXT_REF_CLK
166
MHz
Camera Input Frequency
FCAM_PIXCLK
50
MHz
Camera Output Frequency
FCAM_PIXMCLK
50
MHz
Camera TWSI Frequency
FCAM_TW_SCK
Camera Duty Cycle
DCCAM_PIXMCLK
40
Camera Slew Rate
SRCAM_PIXMCLK
0.5
Camera Reference Clock
0.76
TCLK/2,048
60
MHz
8
%
1
V/ns
2
SS P R e fe r e n c e C lo c k
SSP Clock Frequency
FSSP_SCLK
24.567
MHz
SSP External Clock Frequency
FSSP_EXTCLK
24.567
MHz
R e s e t Sp e c if ic a t i o n s
See Section 7, System Power Up/Down and Reset Settings, on page 72.
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
The load is CL = 15 pF.
Slew rate is defined from 20% to 80% of the reference clock signal.
The RTC design was optimized for a standard CL = 12.5 pF crystal. No passive components
are provided internally. Connect the crystal and the passive network as recommended by the
crystal manufacturer.
Fs is the audio sample rate, which can be configured to 44.1 kHz, 48 kHz, or 96 kHz (see the
Audio (I2S / S/PDIF) Interface section in the 88AP510 Functional Specifications.
Output of the internal DC0 to the codec is twice the bit rate clock of the codec driven back to the
AC ‘97 channel.
See the “Core PLL Clock Tree” section in the 88AP510 Functional Specifications.
To achieve 166 MHz, see the 88AP510 Design Guide.
<TWSICLKDIV> is a configurable parameter for the camera interface, see the Camera interface
registers in the 88AP510 Functional Specifications.
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AC Electrical Specifications
Figure 10: I2SMCLK/CAM_PIXMCLK/SYSCLK_OUT Reference Clock Test Circuit
Test Point
CL
Figure 11: I2SMCLK/CAM_PIXMCLK/SYSCLK_OUT AC Timing Diagram
Cycle Time
VDDIO/2
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9.6.2
Reduced Gigabit Media Independent Interface (RGMII) AC
Timing
9.6.2.1
RGMII AC Timing Table
Table 60: RGMII 10/100/1000 Mbps AC Timing Table
Description
Sym bol
Clock frequency
fCK
Data to Clock output skew
Min
Max
125.0
Units Notes
MHz
2
Tskew T
-0.50
0.50
ns
Tskew R
1.00
2.60
ns
-
Tcyc
7.20
8.80
ns
1,2
Duty cycle for Gigabit
Duty_G
0.45
0.55
tCK
2
Duty cycle for 10/100 Megabit
Duty_T
0.40
0.60
tCK
2
Data to Clock input skew
Clock cycle duration
Notes:
General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.
General comment: tCK = 1/fCK.
General comment: If the PHY does not support internal-delay mode, the PC board design requires
routing clocks so that an additional trace delay of greater than 1.5 ns and less
than 2.0 ns is added to the associated clock signal.
For 10/100 Mbps RGMII, the Max value is unspecified.
1. For RGMII at 10 Mbps and 100 Mbps, Tcyc w ill scale to 400 ns +/-40 ns and 40 ns +/-4 ns, respectively.
2. For all signals, the load is CL = 5 pF.
9.6.2.2
RGMII Test Circuit
Figure 12: RGMII Test Circuit
Test Point
CL
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AC Electrical Specifications
9.6.2.3
RGMII AC Timing Diagram
Figure 13: RGMII AC Timing Diagram
TX
CLOCK
(At Transmitter)
TX
DATA
TskewT
RX
CLOCK
(At Receiver)
RX
DATA
TskewR
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9.6.3
Serial Management Interface (SMI) AC Timing
9.6.3.1
SMI Master Mode AC Timing Table
Table 61: SMI Master Mode AC Timing Table
Description
Sym bol
Min
fCK
MDC clock duty cycle
tDC
0.4
MDIO input setup time relative to MDC rise time
tSU
40.0
MDIO input hold time relative to MDC rise time
Max
Units
Notes
MHz
2
0.6
tCK
-
-
ns
-
See note 2
MDC clock frequency
tHO
0.0
-
ns
3
MDIO output valid before MDC rise time
tOVB
15.0
-
ns
1
MDIO output valid after MDC rise time
tOVA
15.0
-
ns
1
Notes:
General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. For MDC signal, the load is CL = 390 pF, and for MDIO signal, the load is CL = 470 pF.
2. See "Reference Clocks" table for more details.
3. For this parameter, the load is CL = 2 pF.
9.6.3.2
SMI Master Mode Test Circuit
Figure 14: MDIO Master Mode Test Circuit
VDDIO
Test Point
2 kilohm
MDIO
CL
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AC Electrical Specifications
Figure 15: MDC Master Mode Test Circuit
Test Point
MDC
CL
9.6.3.3
SMI Master Mode AC Timing Diagrams
Figure 16: SMI Master Mode Output AC Timing Diagram
VIH(min)
MDC
VIH(min)
MDIO
VIL(max)
tOVB tOVA
Figure 17: SMI Master Mode Input AC Timing Diagram
VIH(min)
MDC
VIH(min)
MDIO
VIL(max)
tSU
tHO
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9.6.4
NAND Flash Interface AC Timing
9.6.4.1
NAND Flash AC Timing Table
Table 62: NAND Flash AC Timing Table
Description
Sym bol
Min
Max
Units
Notes
WEn cycle time
tWC
30.0
-
ns
1
WEn minimum low pulse w idth
tWP
10.0
-
ns
1, 2
WEn minimum high pulse w idth
tWH
15.0
-
ns
1, 2
ALE to WEn skew factor
tASK
-
1.5
ns
2, 4
CLE to WEn skew factor
tCLSK
-
1.5
ns
2, 4
CEn to WEn skew factor
tCSK
-
1.5
ns
2, 4
Data output bus to WEn skew factor
tDSK
-
1.5
ns
2, 4
REn cycle time
tRC
30.0
-
ns
1
REn minimum low pulse w idth
tRP
10.0
-
ns
1, 2
REn minimum high pulse w idth
tREH
15.0
-
ns
1, 2
Data input setup time relative to REn rising edge
tIS
tRP - 22
-
ns
1, 2, 5
Data input hold time relative to REn rising edge
tIH
tREH
-
ns
3, 5
Notes:
General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.
1. See functional specifications for configuration options.
2. For all signals, the load is CL = 10 pF.
3. For this parameter, the load is CL = 2 pF.
4. Skew factor should be taken into consideration as a timing degradation in addition to register settings.
Refer to functional specifications for more information about timing adjustment possibilities.
5. tRP & tREH are the values as set in register setting.
9.6.4.2
NAND Flash Test Circuit
Figure 18: NAND Flash Test Circuit
Test Point
CL
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9.6.4.3
NAND Flash AC Timing Diagrams
Figure 19: NAND Flash Input AC Timing Diagram
tRC
tRP
tREH
VIH(min)
REn
VIL(max)
VIH(min)
Data
VIL(max)
tIS
tIH
Figure 20: NAND Flash Output AC Timing Diagram
tWC
tWP
tWH
VIH(min)
WEn
VIL(max)
VIH(min)
Data / CEn /
CLE / ALE
VIL(max)
t*SK
t*SK
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9.6.5
SDRAM DDR2 Interface AC Timing
9.6.5.1
SDRAM DDR2 400 MHz Interface AC Timing Table
Table 63: SDRAM DDR2 400 MHz 1.8V Interface AC Timing Table
400 MHz @ 1.8V
Description
Clock frequency
Sym bol
Min
Max
400.0
fCK
Units
Notes
MHz
-
DQ and DM valid output time before DQS transition
tDOVB
0.42
-
ns
-
DQ and DM valid output time after DQS transition
tDOVA
0.42
-
ns
-
DQ and DM output pulse w idth
tDIPW
0.35
-
tCK(avg)
-
DQS output high pulse w idth
tDQSH
0.45
-
tCK(avg)
-
DQS output low pulse w idth
tDQSL
0.45
-
tCK(avg)
-
DQS falling edge to CLK-CLKn rising edge
tDSS
0.35
-
tCK(avg)
1
DQS falling edge from CLK-CLKn rising edge
tDSH
0.35
-
tCK(avg)
1
CLK-CLKn rising edge to DQS output rising edge
tDQSS
-0.06
0.06
tCK(avg)
-
DQS w rite preamble
tWPRE
0.45
-
tCK(avg)
-
DQS w rite postamble
tWPST
0.45
-
tCK(avg)
-
tCH
0.48
0.52
tCK(avg)
1, 2, 3
CLK-CLKn high-level w idth
CLK-CLKn low -level w idth
tCL
0.48
0.52
tCK(avg)
1, 2, 4
DQ input setup time relative to DQS in transition
tDSI
-0.41
-
ns
5
DQ input hold time relative to DQS in transition
tDHI
0.84
-
ns
5
Address and Control valid output time before CLK-CLkn rising edge
tAOVB
0.90
-
ns
1
Address and Control valid output time after CLK-CLKn rising edge
tAOVA
0.94
-
ns
1
tIPW
0.65
-
tCK(avg)
-
Address and control output pulse w idth
Notes:
General comment: All timing values w ere measured from vref to vref, unless otherw ise specified.
General comment: All timing parameters w ith DQS signal are defined on DQS-DQSn crossing point.
General comment: For Address and Control output timing parameters, refer to the Address Timing table.
General comment: tCK = 1/fCK.
1. This timing value is defined on CLK / CLKn crossing point.
2. Refer to SDRAM DDR2 clock specifications table for more information.
3. tCH(avg) is defined as the average HIGH pulse w idth, as calculated across any consecutive 200 HIGH pulses.
4. tCL(avg) is defined as the average LOW pulse w idth, as calculated across any consecutive 200 LOW pulses.
5. Please see derating tables for input setup/hold calculations. For example, input setup = tDSI + ΔtDSI
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AC Electrical Specifications
Table 64: SDRAM DDR2 400 MHz 1.5V Interface AC Timing Table
400 MHz @ 1.5V
Description
Clock frequency
Sym bol
Min
Max
400.0
fCK
Units
Notes
MHz
-
DQ and DM valid output time before DQS transition
tDOVB
0.40
-
ns
-
DQ and DM valid output time after DQS transition
tDOVA
0.41
-
ns
-
DQ and DM output pulse w idth
tDIPW
0.35
-
tCK(avg)
-
DQS output high pulse w idth
tDQSH
0.45
-
tCK(avg)
-
DQS output low pulse w idth
tDQSL
0.45
-
tCK(avg)
-
DQS falling edge to CLK-CLKn rising edge
tDSS
0.35
-
tCK(avg)
1
DQS falling edge from CLK-CLKn rising edge
tDSH
0.35
-
tCK(avg)
1
CLK-CLKn rising edge to DQS output rising edge
tDQSS
-0.06
0.06
tCK(avg)
-
DQS w rite preamble
tWPRE
0.45
-
tCK(avg)
-
DQS w rite postamble
tWPST
0.45
-
tCK(avg)
-
tCH
0.48
0.52
tCK(avg)
1, 2, 3
CLK-CLKn high-level w idth
CLK-CLKn low -level w idth
tCL
0.48
0.52
tCK(avg)
1, 2, 4
DQ input setup time relative to DQS in transition
tDSI
-0.41
-
ns
5
DQ input hold time relative to DQS in transition
tDHI
0.84
-
ns
5
Address and Control valid output time before CLK-CLkn rising edge
tAOVB
0.88
-
ns
1
Address and Control valid output time after CLK-CLKn rising edge
tAOVA
0.93
-
ns
1
tIPW
0.65
-
tCK(avg)
-
Address and control output pulse w idth
Notes:
General comment: All timing values w ere measured from vref to vref, unless otherw ise specified.
General comment: All timing parameters w ith DQS signal are defined on DQS-DQSn crossing point.
General comment: For Address and Control output timing parameters, refer to the Address Timing table.
General comment: tCK = 1/fCK.
1. This timing value is defined on CLK / CLKn crossing point.
2. Refer to SDRAM DDR2 clock specifications table for more information.
3. tCH(avg) is defined as the average HIGH pulse w idth, as calculated across any consecutive 200 HIGH pulses.
4. tCL(avg) is defined as the average LOW pulse w idth, as calculated across any consecutive 200 LOW pulses.
5. Please see derating tables for input setup/hold calculations. For example, input setup = tDSI + ΔtDSI
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9.6.5.2
SDRAM DDR2 400 MHz Clock Specifications
Table 65: SDRAM DDR2 400 MHz Clock Specifications
Description
Sym bol
Min
Max
Units
Notes
tJIT(per)
-100
100
ps
1
tJIT(per,lck)
-80
80
ps
2
tJIT(cc)
-200
200
ps
3
Cycle to cycle clock period jitter during DLL locking period
tJIT(cc,lck)
-160
160
ps
4
Cumulative error across 2 cycles
tERR(2per)
-150
150
ps
5
Cumulative error across 3 cycles
tERR(3per)
-175
175
ps
5
Cumulative error across 4 cycles
tERR(4per)
-200
200
ps
5
Clock period jitter
Clock perior jitter during DLL locking period
Cycle to cycle clock period jitter
Cumulative error across 5 cycles
tERR(5per)
-200
200
ps
5
Cumulative error across n cycles, n=6...10, inclusive
tERR(6-10per)
-300
300
ps
5
Cumulative error across n cycles, n=11…50, inclusive
tERR(11-50per)
-450
450
ps
5
tJIT(duty)
-100
100
ps
6
Duty cycle jitter
Absolute clock period
tCK(abs)
See note 7
ps
7
Absolute clock high pulse w idth
tCH(abs)
See note 8
ps
8
Absolute clock low pulse w idth
tCL(abs)
See note 9
ps
9
Notes:
General comment: All timing values are defined on CLK / CLKn crossing point, unless otherw ise specified.
1. tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg).
tJIT(per) = Min/max of {tCKi- tCK(avg) w here i=1 to 200}.
tJIT(per) defines the single period jitter w hen the DLL is already locked.
2. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
3. tJIT(cc) is defined as the difference in clock period betw een tw o consecutive clock cycles: tJIT(cc) = Max of |tCKi+1 – tCKi|.
tJIT(cc) defines the cycle to cycle jitter w hen the DLL is already locked.
4. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
5. tERR(nper) is defined as the cumulative error across multiple consecutive cycles from tCK(avg).
Refer to JEDEC Standard No. 79-2 (DDR2 SDRAM Specification) for more information.
6. tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of
any single tCH from tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg).
tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)} w here,
tJIT(CH) = {tCHi- tCH(avg) w here i=1 to 200}; tJIT(CL) = {tCLi- tCL(avg) w here i=1 to 200}.
7. tCK(abs),min = tCK(avg),min + tJIT(per),min; tCK(abs),max = tCK(avg),max + tJIT(per),max.
8. tCH(abs),min = tCH(avg),min x tCK(avg),min + tJIT(duty),min; tCH(abs),max = tCH(avg),max x tCK(avg),max + tJIT(duty),max.
9. tCL(abs),min = tCL(avg),min x tCK(avg),min + tJIT(duty),min; tCL(abs),max = tCL(avg),max x tCK(avg),max + tJIT(duty),max.
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Note
9.6.5.3
For the DDR2 derating values, see Table 69, SDRAM DDR2/3 Derating Values Table,
on page 122.
SDRAM DDR2 Interface Test Circuit
Figure 21: SDRAM DDR2 Interface Test Circuit
VDDIO/2
Test Point
25 ohm
9.6.5.4
SDRAM DDR2 Interface AC Timing Diagrams
Figure 22: SDRAM DDR2 Interface Write AC Timing Diagram
CLK
tCH
tDSH
tDSS
tDQSH
tDQSL
tCL
CLKn
DQS
tWPRE
tWPST
DQSn
tDIPW
DQ
tDOVB tDOVA
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Figure 23: SDRAM DDR2 Interface Address and Control AC Timing Diagram
CLK
tCH
tCL
CLKn
tIPW
ADDRESS/
CONTROL
tAOIB
tAOIA
Figure 24: SDRAM DDR2 Interface Read AC Timing Diagram
DQS
DQSn
DQ
tDSI
tDHI
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9.6.6
SDRAM DDR3 Interface AC Timing
9.6.6.1
SDRAM DDR3 Interface AC Timing Table
Table 66: SDRAM DDR3 1.5V Interface AC Timing Table
500 MHz @ 1.5V
Description
Symbol
Clock frequency
fCK
DQS to CLK write leveling compensation
tWL
Tap granulatiry for leveling compensation
Min
Max
500
-
2.6
Units
Notes
MHz
-
ns
-
tTAP
12
34
ps
-
DQ and DM valid output time before DQS transition
tDOVB
310
-
ps
-
DQ and DM valid output time after DQS transition
tDOVA
321
-
ps
-
DQ and DM output pulse width
tDIPW
552
-
ps
-
DQS output high pulse width
tDQSH
0.47
-
tCK(avg)
-
DQS output low pulse width
tDQSL
0.47
-
tCK(avg)
-
DQS falling edge to CLK-CLKn rising edge
tDSS
0.35
-
tCK(avg)
1
DQS falling edge from CLK-CLKn rising edge
tDSH
0.35
-
tCK(avg)
1
CLK-CLKn rising edge to DQS output rising edge
tDQSS
-0.08
0.08
tCK(avg)
-
DQS write preamble
tWPRE
0.95
-
tCK(avg)
-
DQS write postamble
tWPST
0.45
-
tCK(avg)
-
tCH
0.48
0.52
tCK(avg) 1, 2, 3
tCK(avg) 1, 2, 4
CLK-CLKn high-level width
CLK-CLKn low-level width
tCL
0.48
0.52
DQ input setup time relative to DQS in transition
tDSI
-291
-
DQ input hold time relative to DQS in transition
ps
5
tDHI
690
-
ps
5
Address and Control valid output time before CLK-CLkn rising edge
tAOVB
682
-
ps
1
Address and Control valid output time after CLK-CLKn rising edge
tAOVA
692
-
ps
1
tIPW
1
-
ns
-
Address and control output pulse width
Notes:
General comment: All timing values were measured from vref to vref, unless otherwise specified.
General comment: All timing parameters with DQS signal are defined on DQS-DQSn crossing point.
General comment: For Address and Control output timing parameters, refer to the Address Timing table.
General comment: tCK = 1/fCK.
1. This timing value is defined on CLK / CLKn crossing point.
2. Refer to SDRAM DDR2 clock specifications table for more information.
3. tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
4. tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
5. Please see derating tables for input setup/hold calculations. For example, input setup = tDSI + ΔtDSI
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Table 67: SDRAM DDR3 1.35V Interface AC Timing Table
400 MHz @ 1.35V
Description
Sym bol
Min
Max
400.0
Units
Notes
Clock frequency
fCK
MHz
-
DQS to CLK w rite leveling compensation
tWL
-
2.6
ns
-
Tap granulatiry for leveling compensation
tTAP
12.0
34.0
ps
-
DQ and DM valid output time before DQS transition
tDOVB
0.41
-
ns
-
DQ and DM valid output time after DQS transition
tDOVA
0.43
-
ns
-
DQ and DM output pulse w idth
tDIPW
0.60
-
ns
-
DQS output high pulse w idth
tDQSH
0.47
-
tCK(avg)
-
DQS output low pulse w idth
tDQSL
0.47
-
tCK(avg)
-
DQS falling edge to CLK-CLKn rising edge
tDSS
0.35
-
tCK(avg)
1
DQS falling edge from CLK-CLKn rising edge
tDSH
0.35
-
tCK(avg)
1
CLK-CLKn rising edge to DQS output rising edge
tDQSS
-0.06
0.06
tCK(avg)
-
DQS w rite preamble
tWPRE
0.95
-
tCK(avg)
-
DQS w rite postamble
tWPST
0.45
-
tCK(avg)
-
CLK-CLKn high-level w idth
tCH
0.48
0.52
tCK(avg)
1, 2, 3
CLK-CLKn low -level w idth
tCL
0.48
0.52
tCK(avg)
1, 2, 4
DQ input setup time relative to DQS in transition
tDSI
-0.45
-
ns
5
DQ input hold time relative to DQS in transition
tDHI
0.81
-
ns
5
Address and Control valid output time before CLK-CLkn rising edge
tAOVB
0.91
-
ns
1
Address and Control valid output time after CLK-CLKn rising edge
tAOVA
0.94
-
ns
1
tIPW
1.0
-
ns
-
Address and control output pulse w idth
Notes:
General comment: All timing values w ere measured from vref to vref, unless otherw ise specified.
General comment: All timing parameters w ith DQS signal are defined on DQS-DQSn crossing point.
General comment: For Address and Control output timing parameters, refer to the Address Timing table.
General comment: tCK = 1/fCK.
1. This timing value is defined on CLK / CLKn crossing point.
2. Refer to SDRAM DDR2 clock specifications table for more information.
3. tCH(avg) is defined as the average HIGH pulse w idth, as calculated across any consecutive 200 HIGH pulses.
4. tCL(avg) is defined as the average LOW pulse w idth, as calculated across any consecutive 200 LOW pulses.
5. Please see derating tables for input setup/hold calculations. For example, input setup = tDSI + ΔtDSI
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9.6.6.2
SDRAM DDR3 Clock Specifications
Table 68: SDRAM DDR3 Clock Specifications
Description
Sym bol
Min
Max
Units
Notes
tJIT(per)
-90
90
ps
1
tJIT(per,lck)
-80
80
Clock period jitter
Clock perior jitter during DLL locking period
ps
2
tJIT(cc)
180
ps
3
Cycle to cycle clock period jitter during DLL locking period
tJIT(cc,lck)
160
ps
4
Cumulative error across 2 cycles
tERR(2per)
-132
132
ps
5
Cumulative error across 3 cycles
tERR(3per)
-157
157
ps
5
Cumulative error across 4 cycles
tERR(4per)
-175
175
ps
5
Cumulative error across 5 cycles
tERR(5per)
-188
188
ps
5
Cumulative error across 6 cycles
tERR(6per)
-200
200
ps
5
Cumulative error across 7 cycles
tERR(7per)
-209
209
ps
5
Cumulative error across 8 cycles
tERR(8per)
-217
217
ps
5
Cumulative error across 9 cycles
tERR(9per)
-224
224
ps
5
Cumulative error across 10 cycles
tERR(10per)
-231
231
ps
5
Cumulative error across 11 cycles
tERR(11per)
-237
237
ps
5
Cumulative error across 12 cycles
tERR(12per)
-242
242
ps
5
ps
8
ps
6
Cycle to cycle clock period jitter
Cumulative error across n cycles, n=13…50, inclusive
See note 8
tERR(13-50per)
Duty cycle jitter
tJIT(duty)
-75
75
See note 7
Absolute clock period
tCK(abs)
ps
7
Absolute clock high pulse w idth
tCH(abs)
0.43
-
tCK(avg)
-
Absolute clock low pulse w idth
tCL(abs)
0.43
-
tCK(avg)
-
Notes:
General comment: All timing values are defined on CLK / CLKn crossing point, unless otherw ise specified.
1. tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg).
tJIT(per) = Min/max of {tCKi- tCK(avg) w here i=1 to 200}.
tJIT(per) defines the single period jitter w hen the DLL is already locked.
2. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
3. tJIT(cc) is defined as the difference in clock period betw een tw o consecutive clock cycles: tJIT(cc) = Max of |tCKi+1 – tCKi|.
tJIT(cc) defines the cycle to cycle jitter w hen the DLL is already locked.
4. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
5. tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg).
Please refer to JEDEC Standard No. 79-2C (DDR2 SDRAM Specification), Chapter 5 (page 100) for more information.
6. tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of
any single tCH from tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg).
tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)} w here,
tJIT(CH) = {tCHi- tCH(avg) w here i=1 to 200}; tJIT(CL) = {tCLi- tCL(avg) w here i=1 to 200}.
7. tCK(abs),min = tCK(avg),min + tJIT(per),min; tCK(abs),max = tCK(avg),max + tJIT(per),max.
8. tERR(nper),min = (1+0.68ln(n))*tJIT(per)min; tERR(nper),max = (1+0.68ln(n))*tJIT(per)max
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9.6.6.3
SDRAM DDR2/3 Derating Values Table
Table 69: SDRAM DDR2/3 Derating Values Table
tDSI, tDHI Derating Values for DDR2/DDR3
DQS Differential Slew Rate
1.0 V/ns
2.0 V/ns
4.0 V/ns
6.0 V/ns
8.0 V/ns
10.0 V/ns
ΔtDSI ΔtDHI ΔtDSI ΔtDHI ΔtDSI ΔtDHI ΔtDSI ΔtDHI ΔtDSI ΔtDHI ΔtDSI ΔtDHI
DQ
Slew 0.5
0
0
97
-53
167
-95
202
-115
218
-127
230
-136
rate
1.0 -53
97
0
0
72
-38
108
-58
123
-70
135
-79
[V/ns]
2.0 -95
167
-38
72
0
0
37
-12
53
-25
65
-33
9.6.6.4
3.0
-115
202
-58
108
-12
37
0
0
21
4.0
-127
218
-70
123
-25
5.0
-136
230
-79
135
-33
-4
30
-12
53
-4
21
65
-12
30
0
0
17
0
0
17
0
0
SDRAM DDR3 Interface Test Circuit
Figure 25: SDRAM DDR3 Interface Test Circuit
VDDIO/2
Test Point
25 ohm
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9.6.6.5
SDRAM DDR3 Interface AC Timing Diagrams
Figure 26: SDRAM DDR3 Interface Write AC Timing Diagram
CLK
tCH
tDSH
tDSS
tDQSH
tDQSL
tCL
CLKn
DQS
tWPST
DQSn
tWPRE
DQ
tDOVB tDOVA
Figure 27: SDRAM DDR3 Interface Address and Control AC Timing Diagram
CLK
tCH
tCL
CLKn
ADDRESS/
CONTROL
tAOVB
tAOVA
Figure 28: SDRAM DDR3 Interface Read AC Timing Diagram
DQS
DQSn
DQ
tDSI
tDHI
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9.6.7
Inter-IC Sound Interface (I2S) AC Timing
9.6.7.1
Inter-IC Sound (I2S) AC Timing Table
Table 70: Inter-IC Sound (I2S) AC Timing Table
Description
Sym bol
I2SBCLK clock frequency
fCK
Min
Max
Units
Notes
MHz
2
tCH/tCL
0.37
-
tCK
1
I2SDI input setup time relative to I2SBCLK rise time
tSU
0.10
-
tCK
-
I2SDI input hold time relative to I2SBCLK rise time
tHO
0.0
-
ns
3
I2SDO, I2SLRCLK output delay relative to I2SBCLK rise time
tOD
0.10
0.70
tCK
1
I2SBCLK clock high/low level pulse w idth
See note 2
Notes:
General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. For all signals, the load is CL = 15 pF.
2. See "Reference Clocks" table for more details.
3. For this parameter, the load is CL = 2 pF.
9.6.7.2
Inter-IC Sound (I2S) Test Circuit
Figure 29: Inter-IC Sound (I2S) Test Circuit
Test Point
CL
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AC Electrical Specifications
9.6.7.3
Inter-IC Sound (I2S) AC Timing Diagrams
Figure 30: Inter-IC Sound (I2S) Output Delay AC Timing Diagram
tCL
tCH
VIH(min)
I2SBCLK
VIL(max)
VIH(min)
I2SDO,
I2SLRCLK
VIL(max)
tODmin
tODmax
Figure 31: Inter-IC Sound (I2S) Input AC Timing Diagram
tCL
tCH
VIH(min)
I2SBCLK
VIL(max)
VIH(min)
I2SDI
VIL(max)
tSU
tHO
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9.6.8
Secure Digital Input/Output (SDIO) Interface AC Timing
9.6.8.1
Secure Digital Input/Output (SDIO) AC Timing Table
Table 71: SDIO Host in High Speed Mode AC Timing Table
Description
Symbol
Min
Max
Units
Notes
fCK
0
50
MHz
-
Clock high/low level pulse w idth
tWL/tWH
0.35
-
tCK
1, 3
Clock rise/fall time
tTLH/tTHL
-
3.0
ns
1, 3
CMD, DAT output valid before CLK rising edge
tDOVB
6.5
-
ns
2, 3
CMD, DAT output valid after CLK rising edge
tDOVA
2.5
-
ns
2, 3
CMD, DAT input setup relative to CLK rising edge
tISU
7.0
-
ns
2
CMD, DAT input hold relative to CLK rising edge
tIHD
0.0
-
ns
2, 4
Clock frequency in Data Transfer Mode
Notes:
General comment: tCK = 1/fCK.
1. Defined on VIL(max) and VIH(min) levels.
2. Defined on VDDIO/2 for Clock signal, and VIL(max) / VIH(min) for CMD & DAT signals.
3. For all signals, the load is CL = 10 pF.
4. For this parameter, the load is CL = 2 pF.
9.6.8.2
Secure Digital Input/Output (SDIO) Test Circuit
Figure 32: Secure Digital Input/Output (SDIO) Test Circuit
VDDIO
Test Point
50 KOhm
CL
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AC Electrical Specifications
9.6.8.3
Secure Digital Input/Output (SDIO) AC Timing Diagrams
Figure 33: SDIO Host in High Speed Mode Output AC Timing Diagram
tWL
tWH
VIH(min)
VDDIO/2
CLK
VIL(max)
VIH(min)
DAT,
CMD
VIL(max)
tDOVB tDOVA
Figure 34: SDIO Host in High Speed Mode Input AC Timing Diagram
tWL
tWH
VIH(min)
VDDIO/2
CLK
VIL(max)
VIH(min)
DAT,
CMD
VIL(max)
tISU
tIHD
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9.6.9
Sony/Philips Digital Interface (S/PDIF) AC Timing
9.6.9.1
S/PDIF AC Timing Table
Table 72: S/PDIF AC Timing Table
Sym bol
Min
Max
Units
Notes
Output frequency accuracy
Description
Ftxtol
-50.0
50.0
ppm
1
Output jitter (total peak-to-peak)
Txjit
-
0.05
UI
1, 2
Txjitgain
-
3.0
dB
3
Jitter transfer gain
Notes:
General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.
General comment: For more information, refer to the Digital Audio Interface - Part 3: Consumer Applications,
IEC 60958-3:2003(E), Chapter 7.3, January 2003.
1. For all signals, the load is CL = 10 pF.
2. Using intrinsic jitter filter.
3. Refer to Figure-8 in IEC 60958-3:2003(E), Chapter 7.3, January 2003.
Note
9.6.9.2
For additional information about working with a coaxial connection, see the 88AP510
Design Guide.
S/PDIF Test Circuit
Figure 35: S/PDIF Test Circuit
Test Point
CL
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AC Electrical Specifications
9.6.10
Serial Peripheral Interface (SPI) AC Timing
9.6.10.1
SPI (Master Mode) AC Timing Table
Table 73: SPI (Master Mode) AC Timing Table
SPI
Description
Sym bol
Min
Max
Units
Notes
SCLK clock frequency
fCK
MHz
3
SCLK high time
tCH
0.46
-
tCK
1
SCLK low time
tCL
0.46
-
tCK
1
SCLK slew rate
tSR
0.5
-
V/ns
1
Data out valid relative to SCLK falling edge
tDOV
-2.5
2.5
ns
1
CS active before first SCLK rising edge
tCSB
0.4
-
tCK
1, 4
CS not active after SCLK rising edge
tCSA
0.4
-
tCK
1, 4
Data in setup time relative to SCLK rising edge
tSU
0.2
-
tCK
2
Data in hold time relative to SCLK rising edge
tHD
5.0
-
ns
2
See Note 3
Notes:
General comment: All values w ere measured from 0.3*vddio to 0.7*vddio, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. For all signals, the load is CL = 10 pF.
2. Defined from vddio/2 to vddio/2.
3. See "Reference Clocks" table for more details.
4. When w orking w ith CPOL=1 mode, the CS is relative to first SCLK falling edge.
9.6.10.2
SPI (Master Mode) Test Circuit
Figure 36: SPI (Master Mode) Test Circuit
Test Point
CL
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9.6.10.3
SPI (Master Mode) Timing Diagrams
Figure 37: SPI (Master Mode) AC Timing Diagram
tCL
tCH
CPOL=1
SCLK
CPOL=0
CS
tCSB
MOSI
tCSA
CPHA=0
tDOVmin
tDOVmax
MOSI
CPHA=1
tDOVmin
tDOVmax
MISO
CPHA=0
tSU
tHD
MISO
CPHA=1
tSU
tHD
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AC Electrical Specifications
9.6.11
TWSI AC Timing
9.6.11.1
TWSI AC Timing Table
Table 74: TWSI Master AC Timing Table
Description
Sym bol
SCK clock frequency
fCK
Min
Max
Units
Notes
kHz
1
SCK minimum low level w idth
tLOW
0.47
-
tCK
2
SCK minimum high level w idth
tHIGH
0.40
-
tCK
2
SDA input setup time relative to SCK rising edge
tSU
250.0
-
ns
-
SDA input hold time relative to SCK falling edge
See note 1
tHD
0.0
-
ns
4
SDA and SCK rise time
tr
-
1000
ns
2, 3
SDA and SCK fall time
tf
-
300
ns
2, 3
tOV
0.0
0.4
tCK
2
SDA output delay relative to SCK falling edge
Notes:
General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. See "Reference Clocks" table for more details.
2. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm.
3. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).
4. For this parameter, the load is CL = 10 pF.
Table 75: TWSI Slave AC Timing Table
100 kHz (Max)
Sym bol
Min
Max
Units
Notes
SCK minimum low level w idth
tLOW
4.7
-
us
1
SCK minimum high level w idth
tHIGH
4.0
-
us
1
SDA input setup time relative to SCK rising edge
tSU
250.0
-
ns
-
SDA input hold time relative to SCK falling edge
Description
tHD
0.0
-
ns
-
SDA and SCK rise time
tr
-
1000.0
ns
1, 2
SDA and SCK fall time
tf
-
300.0
ns
1, 2
tOV
0.0
4.0
us
1
SDA output delay relative to SCK falling edge
Notes:
General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified.
1. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm.
2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).
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9.6.11.2
TWSI Test Circuit
Figure 38: TWSI Test Circuit
VDDIO
Test Point
RL
CL
9.6.11.3
TWSI AC Timing Diagrams
Figure 39: TWSI Output Delay AC Timing Diagram
tHIGH
tLOW
Vih(min)
SCK
Vil(max)
Vih(min)
SDA
Vil(max)
tOV(min)
tOV(max)
Figure 40: TWSI Input AC Timing Diagram
tLOW
tHIGH
Vih(min)
SCK
Vil(max)
Vih(min)
SDA
Vil(max)
tSU
tHD
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AC Electrical Specifications
9.6.12
JTAG Interface AC Timing
9.6.12.1
JTAG Interface AC Timing Table
Table 76: JTAG Interface AC Timing Table
30 MHz
Description
Sym bol
Min
Max
Notes
JTClk frequency
fCK
MHz
-
JTClk minimum pulse w idth
Tpw
0.45
0.55
tCK
-
JTClk rise/fall slew rate
Sr/Sf
0.50
-
V/ns
2
JTRSTn active time
Trst
1.0
-
ms
-
TMS, TDI input setup relative to JTClk rising edge
30.0
Units
Tsetup
6.67
-
ns
-
TMS, TDI input hold relative to JTClk rising edge
Thold
13.0
-
ns
-
JTClk falling edge to TDO output delay
Tprop
1.0
8.33
ns
1
Notes:
General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. For TDO signal, the load is CL = 10 pF.
2. Defined from VIL to VIH for rise time, and from VIH to VIL for fall time.
9.6.12.2
JTAG Interface Test Circuit
Figure 41: JTAG Interface Test Circuit
Test Point
CL
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9.6.12.3
JTAG Interface AC Timing Diagrams
Figure 42: JTAG Interface Output Delay AC Timing Diagram
Tprop
(max)
JTCK
VIH
VIL
TDO
Tprop
(min)
Figure 43: JTAG Interface Input AC Timing Diagram
JTCK
TMS,TDI
Tsetup
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AC Electrical Specifications
9.6.13
Audio Codec (AC) Link Digital Serial Interface AC Timing
9.6.13.1
AC-Link AC Timing Table
Table 77: AC-Link AC Timing Table
Description
Sym bol
Min
Max
Units
Notes
BIT_CLK frequency
fCK
12.288
MHz
-
BIT_CLK period
tCK
81.4
ns
-
BIT_CLK total jitter
tCKJ
-
0.75
ns
-
tH
36.0
45.0
ns
-
BIT_CLK high pulse w idth
BIT_CLK low pulse w idth
tL
36.0
45.0
ns
-
Output valid delay from BIT_CLK rising edge
tOV
0.0
15.0
ns
1
Input setup to BIT_CLK falling edge
tSU
10.0
-
ns
-
Input hold from BIT_CLK falling edge
tHD
10.0
-
ns
-
BIT_CLK, SDATA_Out and SYNC rise/fall time
tR/tF
-
6.0
ns
1, 2
Notes:
General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.
1. For all signals, the load is CL = 75 pF.
2. Defined from 10% to 90% of VDDIO.
9.6.13.2
AC-Link Test Circuit
Figure 44: AC-LinkTest Circuit
Test Point
CL
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9.6.13.3
AC-Link AC Timing Diagram
Figure 45: AC-Link Output AC Timing Diagram
tL
tH
tR
tF
Vih(min)
BIT_CLK
Vil(max)
Vih(min)
SDATA_Out, SYNC
Vil(max)
tOV
Figure 46: AC-Link Input AC Timing Diagram
tL
tH
tR
tF
Vih(min)
BIT_CLK
Vil(max)
Vih(min)
SDATA_In
Vil(max)
tHD
tSU
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9.6.14
Camera Interface AC Timing
9.6.14.1
Camera AC Timing Table
Table 78: Camera AC Timing Table
Description
Sym bol
Min
Units
Notes
MHz
2
0.55
tCK
1
4.00
-
ns
-
4.00
-
ns
-
Clock frequency
fCK
Clock duty cycle
tDCTX
0.45
Input data setup time relative to input clock rise time
tSU
Input data hold time relative to input clock rise time
tHD
Max
See note 2
Notes:
General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. For all signals, the load is CL = 10 pF.
2. See "Reference Clocks" table for more details.
9.6.14.2
Camera Test Circuit
Figure 47: Camera Test Circuit
Test Point
CL
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9.6.14.3
Camera AC Timing Diagram
Figure 48: Camera Input AC Timing Diagram
Vih(min)
Input
Clock
Vih(min)
Input
Data
Vil(max)
tSU
tHD
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AC Electrical Specifications
9.6.15
LCD Interface AC Timing
9.6.15.1
LCD AC Timing Table
Table 79: LCD AC Timing Table
Description
Sym bol
DCLK clock frequency
fCK
DCLK clock high time
tWCH
DCLK clock low time
Output Data & Data Enable invalid relative to DCLK rise time
Output Data & Data Enable valid granularity
Min
Max
See note 2
Units
Notes
MHz
2
1
0.45
0.55
tCK
tWCL
0.45
0.55
tCK
1
tOIV
-1.25
1.25
ns
1, 3
tOVG
-
0.1
ns
1, 3
Notes:
General comment: General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. For all signals, the load is CL = 10 pF.
2. See "Reference Clocks" table for more details.
3. The granularity should be considered w hen changing default data w indow position.
See functional specification for more information.
Note
9.6.15.2
The LCD_CLK output can be shifted by 90/180/270 degrees with clock invert mode
and/or the FTDLL.
LCD Test Circuit
Figure 49: LCD Test Circuit
Test Point
CL
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Hardware Specifications
9.6.15.3
LCD AC Timing Diagram
Figure 50: LCD Transmit AC Timing Diagram
tWCL
tWCH
Output
Clock
Output
Data
tOIVmin
tOIVmax
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9.6.16
Video Graphic Array (VGA) Interface AC Timing
9.6.16.1
VGA AC Timing Table
Table 80: VGA AC Timing Table
Description
Sym bol
Pixel clock rate
fCK
Min
Max
See note 1
Units
Notes
Mbps
1
Digital Hsync/Vsync parameters
Output rise/fall time
tDR/tDF
-
0.80
UI
-
Hsync periodic jitter
THjit
-
0.15
UI
2
Analog R/G/B parameters
Maximum luminance voltage
Vomax
665
770
mV
-
Minimum luminance voltage
Vomin
-35
70
mV
-
tAR/tAF
-
0.25
UI
3
INL
-1
1
LSB
-
Output rise/fall time
Integral linearity error
Differential linearity error
DNL
-1
1
LSB
-
Channel to channel mismatch
CTCm
-
0.06
Vomax
-
Video noise injection ratio
Vnoise
-0.025
0.025
Vomax
-
Channel to channel skew
CTCs
-
UI
-
Video signal peak-to-peak jitter
TAjit
-
0.50
Min(0.2,
2*tAR/tAF
)
UI
-
Notes:
General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.
General Comment: For more information, refer to the VESA Video Signal Standard (VSIS), Revision 1.2, December, 2002.
General comment: UI = 1/fCK.
1. See "Reference Clocks" table for more details.
2. Measurement point is 1.5V.
3. Defined from 10% to 90% of Vomax.
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9.6.16.2
VGA Test Circuit
Figure 51: VGA Hsync/Vsync Test Circuit
Test Point
Hsync / Vsync
2.2
kilohm
Figure 52: VGA R/G/B Test Circuit
Test Point
R/G/B
37.5 ohm
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9.6.17
Synchronous Serial Port (SSP) Interface AC Timing
9.6.17.1
SSP AC Timing Table
Table 81: SSP Clock Master Frame Master AC Timing Table
Description
Sym bol
Clock frequency
fCK
Clock high/low level pulse w idth
tWL/tWH
Clock rise/fall time
Min
Max
See note 1
Units
Notes
MHz
1
0.4
0.6
tCK
3
tTLH/tTHL
-
0.06
tCK
2, 3
TX data output valid before clock edge
tDOVB
0.1
-
tCK
3, 4
TX data output valid after clock edge
tDOVA
0.1
-
tCK
3, 4
FRAME output valid before clock edge
tFOVB
0.22
-
tCK
3, 4
FRAME output valid after clock edge
tFOVA
0.15
-
tCK
3, 4
RX data input setup relative to clock edge
tISU
0.19
-
tCK
4
RX data input hold relative to clock edge
tIHD
0.09
-
tCK
4. 5
Notes:
General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. See "Reference Clocks" table for more details.
2. Defined from 10% to 90% of the signal.
3. For all signals, the load is CL = 10 pF.
4. Clock edge can be either rising or falling, according to register settings.
5. For this parameter, the load is CL = 2 pF.
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Hardware Specifications
Table 82: SSP Clock Master Frame Slave AC Timing Table
Description
Sym bol
Clock frequency
fCK
Clock high/low level pulse w idth
tWL/tWH
Clock rise/fall time
Min
Max
See note 1
Units
Notes
MHz
1
0.4
0.6
tCK
3
tTLH/tTHL
-
0.06
tCK
2, 3
TX data output valid before clock edge
tDOVB
0.1
-
tCK
3, 4
TX data output valid after clock edge
tDOVA
0.1
-
tCK
3, 4
FRAME input setup time relative to clock edge
tIFSU
0.22
-
tCK
4
FRAME input hold time relative to clock edge
tIFHD
0.15
-
tCK
4. 5
RX data input setup relative to clock edge
tISU
0.19
-
tCK
4
RX data input hold relative to clock edge
tIHD
0.09
-
tCK
4. 5
Notes:
General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. See "Reference Clocks" table for more details.
2. Defined from 10% to 90% of the signal.
3. For all signals, the load is CL = 10 pF.
4. Clock edge can be either rising or falling, according to register settings.
5. For this parameter, the load is CL = 2 pF.
Table 83: SSP Clock Slave Frame Master AC Timing Table
Description
Sym bol
Clock frequency
fCK
Clock high/low level pulse w idth
tWL/tWH
Clock rise/fall time
Min
Max
Units
Notes
MHz
1
0.6
tCK
3
See note 1
0.4
tTLH/tTHL
-
0.06
tCK
2, 3
TX data output valid relative to clock edge
tDOV
2.0
0.216*tCK
ns
3, 4
Frame output valid relative to clock edge
tFOV
2.0
0.216*tCK
ns
3, 4
RX data input setup relative to clock edge
tISU
0.09
-
tCK
4
RX data input hold relative to clock edge
tIHD
0.09
-
tCK
3
Notes:
General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. See "Reference Clocks" table for more details.
2. Defined from 10% to 90% of the signal.
3. For all signals, the load is CL = 10 pF.
4. Clock edge can be either rising or falling, according to register settings.
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Electrical Specifications
AC Electrical Specifications
Table 84: SSP Slave Frame Slave AC Timing Table
Description
Sym bol
Clock frequency
fCK
Min
Max
See note 1
Units
Notes
MHz
1
Clock high/low level pulse w idth
tWL/tWH
0.4
0.6
tCK
3
Clock rise/fall time
tTLH/tTHL
-
0.06
tCK
2, 3
TX data output valid relative to clock edge
tDOV
2.0
0.216*tCK
ns
3, 4
FRAME input setup time relative to clock edge
tIFSU
0.22
-
tCK
4
FRAME input hold time relative to clock edge
tIFHD
0.15
-
tCK
3
RX data input setup relative to clock edge
tISU
0.09
-
tCK
4
RX data input hold relative to clock edge
tIHD
0.09
-
tCK
3
Notes:
General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. See "Reference Clocks" table for more details.
2. Defined from 10% to 90% of the signal.
3. For all signals, the load is CL = 10 pF.
4. Clock edge can be either rising or falling, according to register settings.
9.6.17.2
SSP Test Circuit
Figure 53: SSP Test Circuit
Test Point
CL
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Hardware Specifications
9.6.17.3
SSP AC Timing Diagrams
Figure 54: SSP Master Data Tx AC Timing Diagram
tWL
tWH
VIH(min)
Clock
VIL(max)
VIH(min)
TX Data
VIL(max)
tDOVB tDOVA
Figure 55: SSP Data Rx AC Timing Diagram
tWL
tWH
VIH(min)
Clock
VIL(max)
VIH(min)
Data
VIL(max)
tISU
tIHD
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Electrical Specifications (Preliminary)
Differential Interface Electrical Characteristics
9.7
Differential Interface Electrical Characteristics
This section provides the reference clock, AC, and DC characteristics for the following differential
interfaces:
„
PCI Express (PCIe) Interface Electrical Characteristics
„
SATA Interface Electrical Characteristics
„
USB Electrical Characteristics
9.7.1
Differential Interface Reference Clock Characteristics
9.7.1.1
PCI Express Interface Differential Reference Clock Characteristics
Table 85 is relevant for the PCI Express PEX0/1_CLK_P/N signals.
Table 85: PCI Express Interface Differential Reference Clock Characteristics
Description
Sym bol
Min
Max
100.0
Units
Notes
Clock frequency
fCK
MHz
-
Clock duty cycle
DCrefclk
0.4
0.6
tCK
-
Differential rising/falling slew rate
SRrefclk
0.6
4.0
V/ns
3
Differential high voltage
VIHrefclk
150.0
-
mV
-
Differential low voltage
VILrefclk
-
-150.0
mV
-
Vcross
250.0
550.0
mV
1
Variation of Vcross over all rising clock edges
Vcrs_dlta
-
140.0
mV
1
Rise-Fall matching
dTRrefclk
-
20.0
%
1
Average differential clock period accuracy
Tperavg
-300.0
2800.0
ppm
-
Absolute differential clock period
Tperabs
9.8
10.2
ns
2
Tccjit
-
150.0
ps
-
Absolute crossing point voltage
Differential clock cycle-to-cycle jitter
Notes:
General Comment: The reference clock timings are based on 100 ohm test circuit.
General Comment: Refer to the PCI Express Card Electromechanical Specification, Revision 1.1,
March 2005, section 2.1.3 for more information.
1. Defined on a single-ended signal.
2. Including jitter and spread spectrum.
3. Defined from -150 mV to +150 mV on the differential w aveform.
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Hardware Specifications
PCI Express Interface Spread Spectrum Requirements
Table 86: PCI Express Interface Spread Spectrum Requirements
Sym bol
Min
Max
Units
Notes
Fmod
0.0
33.0
kHz
1
Fspread
-0.5
0.0
%
1
Notes:
1. Defined on linear sw eep or “Hershey’s Kiss” (US Patent 5,631,920) modulations.
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Electrical Specifications (Preliminary)
Differential Interface Electrical Characteristics
9.7.2
PCI Express (PCIe) Interface Electrical Characteristics
9.7.2.1
PCI Express Interface Driver and Receiver Characteristics
Table 87: PCI Express Interface Driver and Receiver Characteristics
Description
Sym bol
Min
Max
Units
Notes
Baud rate
BR
2.5
Gbps
-
Unit interval
UI
400.0
ps
-
Baud rate tolerance
Bppm
-300.0
300.0
ppm
2
Driver parameters
Differential peak to peak output voltage
VTXpp
0.8
1.2
V
-
Minimum TX eye w idth
TTXeye
0.75
-
UI
-
Differential return loss
TRLdiff
10.0
-
dB
1
Common mode return loss
TRLcm
6.0
-
dB
1
DC differential TX impedance
ZTXdiff
80.0
120.0
Ohm
-
Receiver parameters
Differential input peak to peak voltage
VRXpp
0.175
1.2
V
-
Minimum receiver eye w idth
TRXeye
0.4
-
UI
-
Differential return loss
RRLdiff
10.0
-
dB
1
Common mode return loss
RRLcm
6.0
-
dB
1
DC differential RX impedance
ZRXdiff
80.0
120.0
Ohm
-
DC single-ended input impedance
ZRXcm
40.0
60.0
Ohm
-
Notes:
General Comment: For more information, refer to the PCI Express Base Specification, Revision 1.1, March, 2005.
1. Defined from 50 MHz to 1.25 GHz.
Return loss includes contributions from on-chip circuitry, chip packaging,
and any off-chip components related to the driver/receiver.
2. Does not account for SSC dictated variations.
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9.7.2.2
PCI Express Interface Test Circuit
Figure 56: PCI Express Interface Test Circuit
Test Points
+
C_TX
D+
D-
C_TX
50 ohm
50 ohm
When measuring Transmitter output parameters, C_TX is an optional portion of the
Test/Measurement load. When used, the value of C_TX must be in the range of 75 nF to 200 nF.
C_TX must not be used when the Test/Measurement load is placed in the Receiver package
reference plane.
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Differential Interface Electrical Characteristics
9.7.3
SATA Interface Electrical Characteristics
9.7.3.1
SATA I Interface Gen Mode Driver and Receiver
Characteristics
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Hardware Specifications
Table 88: SATA I Interface Gen1m Mode Driver and Receiver Characteristics
Description
Sym bol
Baud Rate
Min
Max
BR
Baud rate tolerance
Bppm
1.5
-350.0
350.0
Units
Notes
Gbps
-
ppm
-
Spread spectrum modulation frequency
Fssc
30.0
33.0
kHz
-
Spread spectrum modulation Deviation
SSCtol
-5000.0
0.0
ppm
-
ps
-
Unit Interval
UI
666.67
Driver Parameters
Differential impedance
Zdifftx
85.0
115.0
Ohm
-
Single ended impedance
Zsetx
40.0
-
Ohm
-
Differential return loss (75 MHz-150 MHz)
RLOD
14.0
-
dB
-
Differential return loss (150 MHz-300 MHz)
RLOD
8.0
-
dB
-
Differential return loss (300 MHz-1.2 GHz)
RLOD
6.0
-
dB
-
Differential return loss (1.2 GHz-2.4 GHz)
RLOD
3.0
-
dB
-
Output differential voltage
Vdifftx
400.0
600.0
mV
2
Total jitter at connector data-data, 5UI
TJ5
-
0.355
UI
1, 3
Deterministic jitter at connector data-data, 5UI
DJ5
-
0.175
UI
3
Total jitter at connector data-data, 250UI
TJ250
-
0.470
UI
1, 3
Deterministic jitter at connector data-data, 250UI
DJ250
-
0.220
UI
3
Receiver Parameters
Differential impedance
Zdiffrx
85.0
115.0
Ohm
-
Single ended impedance
Zsetx
40.0
-
Ohm
-
Differential return loss (75 MHz-150 MHz)
RLID
18.0
-
dB
-
Differential return loss (150 MHz-300 MHz)
RLID
14.0
-
dB
-
Differential return loss (300 MHz-600 MHz)
RLID
10.0
-
dB
-
Differential return loss (600 MHz-1.2 GHz)
RLID
8.0
-
dB
-
Differential return loss (1.2 GHz-2.4 GHz)
RLID
3.0
-
dB
-
Vdiffrx
240.0
600.0
mV
-
Total jitter at connector data-data, 5UI
TJ5
-
0.430
UI
1, 3
Deterministic jitter at connector data-data, 5UI
DJ5
-
0.250
UI
3
Total jitter at connector data-data, 250UI
TJ250
-
0.600
UI
1, 3
Deterministic jitter at connector data-data, 250UI
DJ250
-
0.350
UI
3
Input differential voltage
Notes:
General Comment: For more information, refer to SATA II Revision 2.6 Specification, February, 2007.
General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.
General Comment: To comply w ith the values presented in this table, refer to your local
Marvell representative for register settings.
1. Total jitter is defined as TJ = (14 * RJσ) + DJ w here Rjσ is random jitter.
2. Output Differential Amplitude and Pre-Emphasis are configurabile. See the functional register description
for more details.
3. The value is informative only, and it can be achieved by using a proper board layout.
Refer to the hardw are design guidelines for more information.
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Differential Interface Electrical Characteristics
9.7.3.2
SATA II Interface Gen2 Mode Driver and Receiver Characteristics
Table 89: SATA II Interface Gen2 Mode Driver and Receiver Characteristics
Description
Sym bol
Baud Rate
Min
Max
3.0
BR
Units
Notes
Gbps
-
Baud rate tolerance
Bppm
-350.0
350.0
ppm
-
Spread spectrum modulation frequency
Fssc
30.0
33.0
kHz
-
Spread spectrum modulation deviation
SSCtol
-5000.0
0.0
ppm
-
ps
-
mV
1,2
Unit Interval
333.33
UI
Driver Parameters
Output differential voltage
Vdifftx
400.0
700.0
Differential return loss (150 MHz-300 MHz)
RLOD
14.0
-
dB
-
Differential return loss (300 MHz-600 MHz)
RLOD
8.0
-
dB
-
Differential return loss (600 MHz-2.4 GHz)
RLOD
6.0
-
dB
-
Differential return loss (2.4 GHz-3.0 GHz)
RLOD
3.0
-
dB
-
Total jitter at connector clock-data
TJ10
-
0.30
UI
4, 5
Deterministic jitter at connector clock-data
DJ10
-
0.17
UI
4, 5
Total jitter at connector clock-data
TJ500
-
0.37
UI
5, 6
Deterministic jitter at connector clock-data
DJ500
-
0.19
UI
5, 6
Receiver Parameters
Input differential voltage
Vdiffrx
240.0
750.0
mV
3
Differential return loss (150 MHz-300 MHz)
RLID
18.0
-
dB
-
Differential return loss (300 MHz-600 MHz)
RLID
14.0
-
dB
-
Differential return loss (600 MHz-1.2 GHz)
RLID
10.0
-
dB
-
Differential return loss (1.2 GHz-2.4 GHz)
RLID
8.0
-
dB
-
Differential return loss (2.4 GHz-3.0 GHz)
RLID
3.0
-
dB
-
Total jitter at connector clock-data
TJ10
-
0.46
UI
4, 5
Deterministic jitter at connector clock-data
DJ10
-
0.35
UI
4. 5
Total jitter at connector clock-data
TJ500
-
0.60
UI
5, 6
Deterministic jitter at connector clock-data
DJ500
-
0.42
UI
5, 6
Notes:
General Comment: For more information, refer to SATA II Revision 2.5 Specification, October, 2005.
General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.
General Comment: To comply w ith the values presented in this table, refer to your local
Marvell representative for register settings.
1. 0.45-0.55 UI is the range w here the signal meets the minimum level.
2. Output Differential Amplitude and Pre-Emphasis are configurabile. See the functional register description
for more details.
3. 0.5 UI is the point w here the signal meets the minimum level.
4. Defined for BR/10.
5. The value is informative only, and it can be achieved by using a proper board layout.
Refer to the hardw are design guidelines for more information.
6. Defined for BR/500.
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9.7.4
USB Electrical Characteristics
9.7.4.1
USB Driver and Receiver Characteristics
Table 90: USB Low Speed Driver and Receiver Characteristics
Low Speed
Description
Baud Rate
Baud rate tolerance
Ouput single ended high
Ouput single ended low
Output signal crossover voltage
Data fall time
Data rise time
Rise and fall time matching
Source jitter total: to next transition
Source jitter total: for paired transitions
Input single ended high
Input single ended low
Differential input sensitivity
Sym bol
BR
Bppm
Driver Parameters
VOH
VOL
VCRS
TLR
TLF
TLRFM
TUDJ1
TUDJ2
Receiver Parameters
VIH
VIL
VDI
Min
Max
1.5
-15000.0 15000.0
Units
Mbps
ppm
Notes
-
2.8
0.0
1.3
75.0
75.0
80.0
-95.0
-150.0
3.6
0.3
2.0
300.0
300.0
125.0
95.0
150.0
V
V
V
ns
ns
%
ns
ns
1
2
3
3, 4
3, 4
5
5
2.0
0.2
0.8
-
V
V
V
-
Notes:
General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000.
General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.
General Comment: To comply w ith the values presented in this table, refer to your local
Marvell representative for register settings.
1. Defined w ith 1.425 kilohm pull-up resistor to 3.6V.
2. Defined w ith 14.25 kilohm pull-dow n resistor to ground.
3. See "Data Signal Rise and Fall Time" w aveform.
4. Defined from 10% to 90% for rise time and 90% to 10% for fall time.
5. Including frequency tolerance. Timing difference betw een the differential data signals.
Defined at crossover point of differential data signals.
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Electrical Specifications (Preliminary)
Differential Interface Electrical Characteristics
Table 91: USB Full Speed Driver and Receiver Characteristics
Full Speed
Description
Sym bol
BR
Bppm
Driver Parameters
Ouput single ended high
VOH
Ouput single ended low
VOL
Output signal crossover voltage
VCRS
Output rise time
TFR
Output fall time
TFL
Source jitter total: to next transition
TDJ1
Source jitter total: for paired transitions
TDJ2
Source jitter for differential transition to SE0 transition
TFDEOP
Receiver Parameters
Input single ended high
VIH
Input single ended low
VIL
Differential input sensitivity
VDI
Receiver jitter : to next transition
tJR1
Receiver jitter: for paired transitions
tJR2
Baud Rate
Baud rate tolerance
Min
Max
12.0
-2500.0
2500.0
Units
Mbps
ppm
Notes
-
2.8
0.0
1.3
4.0
4.0
-3.5
-4.0
-2.0
3.6
0.3
2.0
20.0
20.0
3.5
4.0
5.0
V
V
V
ns
ns
ns
ns
ns
1
2
4
3, 4
3, 4
5, 6
5, 6
6
2.0
0.2
-18.5
-9.0
0.8
18.5
9.0
V
V
V
ns
ns
6
6
Notes:
General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000.
General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.
General Comment: To comply w ith the values presented in this table, refer to your local
Marvell representative for register settings.
1. Defined w ith 1.425 kilohm pull-up resistor to 3.6V.
2. Defined w ith 14.25 kilohm pull-dow n resistor to ground.
3. Defined from 10% to 90% for rise time and 90% to 10% for fall time.
4. See "Data Signal Rise and Fall Time" w aveform.
5. Including frequency tolerance. Timing difference betw een the differential data signals.
6. Defined at crossover point of differential data signals.
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Hardware Specifications
Table 92: USB High Speed Driver and Receiver Characteristics
High Speed
Description
Baud Rate
Baud rate tolerance
Data signaling high
Data signaling low
Data rise time
Data fall time
Data source jitter
Sym bol
BR
Bppm
Driver Parameters
VHSOH
VHSOL
THSR
THSF
Min
Max
480.0
-500.0
500.0
Units
Mbps
ppm
Notes
-
360.0
440.0
-10.0
10.0
500.0
500.0
See note 2
mV
mV
ps
ps
1
1
2
Receiver Parameters
Differential input signaling levels
Data signaling common mode voltage range
Receiver jitter tolerance
VHSCM
See note 3
-50.0
500.0
See note 3
3
3
mV
Notes:
General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000.
General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.
General Comment: To comply w ith the values presented in this table, refer to your local
Marvell representative for register settings.
1. Defined from 10% to 90% for rise time and 90% to 10% for fall time.
2. Source jitter specified by the "TX eye diagram pattern template" figure.
3. Receiver jitter specified by the "RX eye diagram pattern template" figure.
9.7.4.2
USB Interface Driver Waveforms
Figure 57: Low/Full Speed Data Signal Rise and Fall Time
Rise Time
Fall Time
90%
90%
VCRS
10%
Differential
Data Lines
10%
TR
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TF
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Electrical Specifications (Preliminary)
Differential Interface Electrical Characteristics
Figure 58: High Speed TX Eye Diagram Pattern Template
+525mV
+475mV
+400mV
Differential
+300mV
0 Volts
Differential
-300mV
- 400mV
Differential
-475mV
-525mV
7.5%
37.5%
92.5%
62.5%
0%
100%
Figure 59: High Speed RX Eye Diagram Pattern Template
+525mV
+475mV
+400mV
Differential
+175mV
0 Volts
Differential
-175mV
- 400mV
Differential
-475mV
-525mV
12.5%
35
65
0%
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87.5%
100%
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Hardware Specifications
10
Thermal Data
Table 93 provides the package thermal data for the 88AP510. This data is derived from simulations
that were run according to the JEDEC standard.
The thermal parameters are preliminary and subject to change.
The documents listed below provide a basic understanding of thermal management of integrated
circuits (ICs) and guidelines to ensure optimal operating conditions for Marvell products. Before
designing a system it is recommended to refer to these documents:
„
„
Application Note, AN-63 Thermal Management for Selected Marvell® Products, Document
Number MV-S300281-00
White Paper, ThetaJC, ThetaJA, and Temperature Calculations, Document Number
MV-S700019-00.
Table 93: Thermal Data for the 88AP510 in (Package Type) Package
Sy m b o l
D e fin i ti on
Ai rf lo w Va lu e ( C / W )
0[m/s]
1 [ m /s ]
2 [ m /s ]
θJA
Thermal resistance: junction to ambient.
13.2
11.7
11.1
ΨJT
Thermal characterization parameter:
junction to case center.
3.6
3.7
3.7
θJC
Thermal resistance: junction to case (not air-flow dependent)
ΨJB
Thermal characterization parameter:
junction to the bottom of the package.
θJB
Thermal resistance:
junction to the bottom of the package (not air-flow dependent)
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4.6
5.5
5.4
5.4
5.6
Copyright © 2011 Marvell
Document Classification: Proprietary Information
July 13, 2011, Preliminary
Package Mechanical Dimensions (Preliminary)
11
Package Mechanical Dimensions
(Preliminary)
The 88AP510 uses a 568-pin 27 mm x 27 mm BGA package with a 1 mm pitch.
Figure 60: 568-Pin BGA Package and Dimensions
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
Document Classification: Proprietary Information
Page 159
88AP510
Hardware Specifications
Figure 61: Package Drawing Key
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Copyright © 2011 Marvell
Document Classification: Proprietary Information
July 13, 2011, Preliminary
Part Order Numbering/Package Marking
Part Order Numbering
12
Part Order Numbering/Package Marking
12.1
Part Order Numbering
Figure 62 shows the part order numbering scheme for the 88AP510. Refer to Marvell Field
Application Engineers (FAEs) or representatives for further information when ordering parts.
Figure 62: Sample Part Number
88AP510 –xx–BJV–C000–xxxx
Custom code (optional)
Part number
Custom code
88AP510
Temperature code
C = Commercial
Custom code/
Die revision
Environmental code
2 = Green (RoHS 6/6 and
Halogen-free)
Custom code
Package code
BJV = 568-pin BGA
R.
Table 94: 88AP510 Part Order Options
P a c k a g e Ty p e
P ar t O r d e r N u m b e r
568-pin BGA
88AP510-xx-BJV2C008 (Green, RoHS 6/6 and Halogen-free package, 800 MHz CPU Frequency)
568-pin BGA
88AP510-xx-BJV2C010 (Green, RoHS 6/6 and Halogen-free package, 1 GHz CPU Frequency)
Copyright © 2011 Marvell
July 13, 2011, Preliminary
Doc. No. MV-S105141-U0 Rev. F
Document Classification: Proprietary Information
Page 161
88AP510
Hardware Specifications
12.2
Package Marking
Figure 63 shows a sample Commercial package marking and pin 1 location for the 88AP510.
Figure 63: Commercial Package Marking and Pin 1 Location
Marvell logo
Country of origin
(Contained in the mold ID or
marked as the last line on
the package.)
Part number and die revision
code
88AP510 = Part number
xx = Die revision
Pin 1 location
88AP1-BJVe
**************
YYWW ##@
Country of Origin
88AP510-xx
Part number prefix, package code, environmental code
88AP = Part number prefix
BJV = Package code
e = Environmental code: 2 = Green
Date code, die Revision, assembly plant code
YYWW = Date code (YY = year, WW = Work Week)
## = Die revision
@ = Assembly plant code
Note: The above drawing is not drawn to scale. Location of markings is approximate.
Doc. No. MV-S105141-U0 Rev. F
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Copyright © 2011 Marvell
Document Classification: Proprietary Information
July 13, 2011, Preliminary
Contact Information
Marvell Semiconductor, Inc.
5488 Marvell Lane
Santa Clara, CA 95054, USA
Tel: 1.408.222.2500
Fax: 1.408.988.8279
www.marvell.com
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