Download A Brief Introduction to Single Electron Transistors

A Brief Introduction to Single Electron Transistors
Diogo AGUIAM
OBRECZÁN Vince
December 18, 2011
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Abstract
Transistor integration has come a long way since Moore’s Law was first mentioned and current
mass fabrication methods are in the 20 nm resolution. The Single Electron Transistor makes use
of the quantum effects which occur at nanometric scales to provide discretization of its I-V spectra.
For room temperature applications, the size of the quantum dots is still lower than what is currently
feasible with existing technologies. Possible applications of the SET include memory cells, metrology
standards and new logic circuits based on its discreet currents. However, investor interest should but
gathered to allow for the proliferation of the single electron transistor outside research laboratories.
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1.1
Introduction
History of transistors
The transistor was first invented in 1947 at Bell Labs and for its deep effects on our world, it has
been considered the most important invention of the 20th century. It has allowed both scientists and
engineers to create complex systems and develop new electronic applications. The first working example
of an electronic circuit where all its components were integrated on a single semiconductor was achieved
in 1958 by Jack Kilby for Texas Instruments. The idea of building basic blocks of electronics on a single
substrate propelled the creation of a whole industry for circuit integration, semiconductor fabrication and
focused on the miniaturization of these circuits. If transistors and other electronic components could be
made smaller, more of these could be built on the same area of semiconductor. The complexity of these
circuits could be increased for the same chip area and its power reduced. Moore’s Law is a well-known
term nowadays but was first talked coined in 1970 and its current adaptation states that the number of
transistors in an integrated circuit doubles roughly every two years. This can be understood as the size
of the transistor to decrease by half every two years.
1.2
State of the Art in Nanofabrication
The current state of the art transistor fabrication methods are in the nanometer scales. Intel, for
example, introduced this year the 22 nm [1] CMOS fabrication technology for its processors with 16 nm
technology already being tested in its laboratories. Whereas in research departments there can be several
different methods which may enable building nanostructures in the 5 nm resolution and even lower [2],
the current state of the art lies in the high fidelity fabrication technologies. The technology which is used
for mass production of circuits and SoCs (Systems on Chip) must have a high success rate of functional
outputs. The maturity of a given technology allows for easier design and commercialization of products
as well as making it cheaper to fabricate. The most widely used technologies in consumer electronics are
silicon CMOS technologies but also gallium-arsenide [3] and other semiconductor technologies are used
depending on the specifications desired. The design of circuits is very specific on the technology used, be
it 0.25 µm GaAs or the 22 nm CMOS, and this technology is specific to a fabrication facility, or foundry.
Outside research departments the possibility of proliferating a new nanoscale device, such as the single
electron transistor, depends highly on its benefits in real-world applications and ease of mass fabrication.
Lithography and nano growth still remains as the preferred method for mass production. For a new
nano device to reach consumer level affordability and wide proliferation it must be fabricated using either
existing methods or without many differences, and its applications should be widespread. However, for a
very specific niche it is possible to have custom processes which highly increase the cost, but for a high
fidelity fabrication, the technology should be mature enough.
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2.1
Single Electron Transistors
Scaling problems of ordinary transistor fabrications [2]
Recent applications of transistors in the fields of computer technology and other electronics requested
a size reduction. This means not only smaller devices, it can result in low power consumption, and better
electronic properties. Unfortunately there are some problems emerging when the size of the fabricated
transistors shrink. Below about 100 nm of size some new quantum mechanical effects become significant.
In a device with very large transistor density the rising probability of electron tunneling effect causes
crosstalk between transistors built next to each other. The smaller size of n or p doped regions can lead to
tunneling electron flow form one electrode to the other resulting a reduced ability of control. Furthermore
the smaller devices require more accurate fabrication techniques. All these problems lead to the need of
newly designed devices and fabrication methods that can operate in smaller sizes.
2.2
Nanoscale devices
In a macroscopic scale the discrete value of electric charge does not show up. In an average large scale
device the smallest current means millions of moving electrons, and the manipulation of single electrons
is practically incredible. In nanoscale devices we experience the discretedness of current resulting that
we can manipulate and detect them individually. Furthermore in macroscopic devices the size of the
system is much larger than the characteristic lengths of electron propagation (such as momentum or
phase reservation length) and in nanodevices these lengths are commensurable with the system dimensions
resulting extraordinary conductive properties like quantum-Hall effect and discrete conductance quantum.
The simplest devices to manipulate single electrons may be the quantum dot (QD) devices (fig. 1).
It is composed of two barriers and a region between them where the electron can be found. It can be
described as two electron valves in a row and a valley of electron states between them. The depth (the
number of electron states) of the valley can be set with the gate voltage. If the energy level of an electron
state is higher than the first barrier, and the thermal excitation is high enough to put electrons to this
state, the electron can fall into the valley. Howerver it has a nonzero possibility for the electron to get
into the valley with tunnel effect from a lower energy level.
(a)
(b)
Figure 1: a) A theoretical figure of the quantum dot potential valley, from [4]. b) A SEM image of a
quantum dot formed of graphene, from [5]. With setting of gate voltage Vg one can control the current
flow through the QD
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2.3
Fabrication issues
It has practical reasons that we need devices operating at room temperature resulting that the device
will have to meet some certain requirements. The applications set conditions on the size of the device
components and the purity and homogeneity of its material. It is necessary to reduce the size scale of the
device. Some of the common techniques used to produce ordinary transistors are no longer acceptable.
Photolithography based fabrication methods has limitations in the size reduction. The diffraction limit
of the light highly dependent on the wavelength of the wave used. In general the resolution can be
improved by means of X-ray sources. The scattering of the photons in the photosensitive material used
to form patterns on the surface results in a lowest resolution. For preparation of smaller devices electron
lithography is used. This method can result better resolution, but is much more expensive, takes more
time and has limitations in the terms of automatization and mass production.
A SET can be fabricated using wet-chemical methods. This means devices composed of chemically
synthesized nanoparticles. The main advantage of this preparation methods are the small sizes of the
nanoparticles what can be achieved, even smaller than what a lithographically fabricated device can
achieve. These techniques have some challenges remaining such as good control over particle size and
monodisperitivity. Improvement of these fields would result in a better operation on the SETs.
2.4
Electronic properties
An example of a proven working SET is a MINIM fabricated with a wet-chemical method for an example of nanostructure. The MINIM is an abbreviation for a metal–insulator–nanocluster–insulator–metal
heterostructure which can be operate as a quantum dot if we apply a bias potential to the metal leads.
The insulators are the barriers, and the nanoclaster provide the potential valley. In a semiclassical point
of view the characteristic parameters of this nanodevice is the capacitance and resistance of the insulators.
In one approach [6] the MINIM is a chemically fabricated heterostructure (fig. 2). Measurements taken
by means of a Scanning Tunneling Microscope (STM) tip which is placed on one of the Au nanocluster.
It has been shown that this kind of device has a Coulomb-gap and one step in the conductance even at
room temperature.
Figure 2: Layers of a MINIM heteristructure [6]
In an another type of experimental arrangement [7] a SET is made using cadmium selenide nanocrystals (fig. 3a). Measurements taken at T = 4, 2K, the conductance is determined as a function of the
gate voltage. A peak is observed in the conductance at a certain gate voltage (fig. 3b). At the peak the
conductance is slightly similar to the ohmic. The reduced conductance on each side can be understood as
a result of the energy cost of adding/removing electrons to/from the nanocrystal. Thus in the I/V plots
a wide gap can be observed around zero. When the two charge states of the nanocrystal is balanced an
extra electron can propagate without energy cost resulting a higher conductance.
2.5
Single electron transistor applications
Single electron devices such as the single electron transistors have several suggested applications, both
in the analog and digital domain. Some of these suggestions definitely attract more investor interest for
their applicability in the current consumer electronics. An interesting application is the single-electron
memory [8]. The memory device industry is a very competitive area and there are several technology
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(a)
(b)
Figure 3: A SET made from a cadmium selenide nanocrystal [7]
processes dedicated to its fabrication. One of its main challenges is the miniaturization of a single memory
cell which allows for more cells to be included in the same area. Using a single electron transistor,
whose structure is similar to current CMOS memory cells, as a memory would allow for very low power
consumption, as demonstrated, and high integration due to its reduced size.
Other applications make use of the discrete I-V properties of single electron transistor. Metrology, or
the science of measurement, makes use of references to measure quantities. There are references used by
the international standards associations for every metric: weight, size, speed, charge... The ideal reference
is one based on the fundamental value of that metric. Using a single electron device allows measurements
based on the charge of a single electron, meaning that an ultra sensitive device could be achieved. This
reference could be used for DC current, temperature and resistance standards. Other analog applications
include very narrowband SET oscillators which could be used for radiofrequency systems. For digital
applications there have also been suggestions for voltage state and charge state logic circuitry [9].
2.6
Drawbacks of the SET
The sensitivity to a single electron in these nano devices demand that the device is very sensitive to
thermal noise. To operate at room temperature and above, the feature size of the quantum dots of the
single electron transistor must be very small, less than 10 nm for some materials. Circuit integration
at this resolution is still hard to accomplish feasibly and the fabrication of these devices is still based
on unconventional methods and with a low success rate. The SET is still far from replacing MOSFET
transistors and circuitry so its applications, such as a memory cell, must be integrated along with current
CMOS technologies. However, the SET is considered a charge amplifier [10] and its signals must still be
amplified to MOSFET levels, which still require very sensitive MOSFET transistors.
Summary
Single electron transistors are based on the quantum mechanic properties found at the nanometric
scale. Feasible fabrication methods have been sought after by many researchers and this is mandatory
if SETs are ever to have widespread use. Usual fabrication issues are the resolution required and the
interactions between transistors in close proximity. SET applications include memory cells, devices used
for metrology standards and logic circuits but these must be integrated along with current technologies
to reduce cost and allow for investor interest.
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References
[1] http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf.
[2] D. L. F. Christine D. Keating, “Self-assembly of single electron transistors and related devices,” Chemical
Society Reviews, vol. 27, pp. 1–12, 1998.
[3] http://www.triquint.com/prodserv/foundry/process_info.cfm.
[4] http://www.fkf.mpg.de/metzner/research/qdot/qdot.html.
[5] http://www.condmat.physics.manchester.ac.uk/pictures/.
[6] D. L. F. K. C. Grabar M. J. Natan T. E. Mallouk J. Am. Chemical Society Reviews, vol. 118, p. 7640, 1996.
[7] D. L. K. Richard Roth Andrew K. L. Lim A. Paul Alivisatos Paul L. McEuen, “A single-electron transistor
made from a cadmium selenide nanocrystal,” Nature, vol. 389, pp. 699–701, 1997.
[8] L. G. E. Leonbandung S. Y. Chou, “A silicon single-electron transistor memory operating at room temperature,” Science Magazine, vol. 275, p. 649, 1999.
[9] http://pavel.physics.sunysb.edu/ likharev/personal/PIEE99.pdf.
[10] M. H. D. R. J. Schoelkopf, “Amplifying quantum signals with the single-electron transistor,” Nature Magazine,
vol. 406, 2000.
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