Download I/O Devices, Software and Hardware Interrupts

I/O Devices, Software and Hardware
Interrupts
CISC-221 I/O, Interrupts
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Role of an Operating System
• management of system resources
• memory management
• managing I/O devices
• fault management.
• provide services to application programs
• load, start, stop programs
• simplified, consistent programming interface for access to I/O
devices
• access to system utilities (useful functions, programs, facilities)
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Traps (software or synchronous interrupts)
• a “trap”
• is a transfer of control (similar to a jump to subroutine) to a
specific memory location.
• provides a mechanism for the operating system to regain control of
the machine when an application program causes something to go
wrong. (application program causes an “exception” condition)
• provides a mechanism used by application programs to request the
services of the OS. Most architectures (but not PEP/6) have
specific SWI (SoftWare Interrupt) instructions for this purpose
• a trap causes an “interruption” of the normal sequence of
instruction execution
• it is considered a “synchronous” interrupt because it occurs
coincident with the execution of an instruction.
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Common Causes of “Exception” Conditions
• illegal instruction: an attempt to execute an unimplemented
opcode
• integer or floating point “overflow” or “underflow” (V bit
set)
• an attempt to divide by 0.
• a misaligned memory reference
• memory protection violation
• System Calls
• there are instructions that exist for the express purpose of
requesting a service from the operating system (SWI)
• normally these aren’t considered “exceptions” per se but the PEP
architecture uses an exception to obtain OS services, so I included
it here.
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TRAP (Software Interrupt) sequence on the PEP/6
•
when an application program attempts to execute an
“unimplemented” instruction ( including opcodes 11101,
11110, and 11111 which are the DECI, DECO, and
HEXO instructions),
1. The PEP hardware pushes the following CPU registers on the
stack: IR (instruction specifier part only), SP, PC, B, X, A,
Status flags NZVC)
2. SP set to new top of system stack.
3. PC set to address of interrupt service routine.
The address of the interrupt service routing is read from a fixed
address in the PEP/6 ROM (address h#0FFE). The choice of this
address is fixed by the PEP/6 hardware.
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TRAP on a PEP/6 (cont’d)
• The effect of this is to transfer instruction execution
control to the first instruction of the interrupt service
routine.
• on the PEP/6, the interrupt service routine will check to see
if the interrupt was caused by the attempt to execute a
DECI, DECO, or HEXO instruction. If so, it will perform
the appropriate utility.
• the last instruction of an interrupt service routine MUST be
a RTI (Return from Interrupt) instruction.
• The RTI instruction pops the saved “program context”
from the stack and returns instruction execution control to
the program that was interrupted.
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3
• Specifically, it pops the following off the stack and puts
the values back in the appropriate registers:
• Status flags NZVC, A, X, B, PC, SP.
• as with subroutine execution, it is vitally important that
any entries put on the stack by the interrupt service routine
are removed before the execution of the “return”
instruction so that the SP is pointing to the save register
values.
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Structure of a typical computer
Monitor
Floppy
Disk Drive
Hard
Disk
Drive
Floppy
Disk
Controller
Hard
Disk
Controller
Keyboard
asdfghjkl
CPU
Memory
Video
Controller
Keyboard
Controller
System Bus
(Address, Data, Control signals)
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System Bus Structure
• Bus: “a common electrical pathway between multiple
devices”
• Address lines (unidirectional, generated by CPU)
• Data lines (bidirectional)
• Control lines (individual lines specify size of data transfer,
direction, timing, interrupts, etc).
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I/O Controller Interface
Address Bus
Data Bus
System
Bus
Control Bus
Address
Decoder
Data, Control
and Status
Registers
Control
Circuits
I/O Controller
I/O Device
•
•
•
Address Decoder: decides if system address intended for I/O Controller
Control Circuits : control timing of data transfers and data routing to and
from specific registers within the I/O Controller
Data, Control, and Status Registers: temporary storage of information
within the I/O Controller CISC-221 I/O, Interrupts
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Addressing an I/O Controller
• I/O controller may be identified either by an unique
address or group of addresses reserved for it. This address
may be
• in the same address space as memory (Memory Mapped I/O) OR
• in a separate address space reserved for I/O devices (Port Mapped
I/O)
• Memory Mapped I/O (Motorola and most other architectures)
• advantage: any instruction which supports Memory based operands
can also be used for I/O operations
• disadvantage: total available address space shared between
memory and I/O devices – not generally a problem with 32 bit
address
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Port Mapped I/O
• Port Mapped I/O (Intel (PC) Architectures)
• advantage: separate memory and I/O address spaces
• disadvantage: separate instructions used to access I/O
devices
» IN dst, port
;dst := contents(port)
» OUT port, src
;port := contents(src)
• Must first transfer data to a CPU register before
processing
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Communication with I/O Devices
• communication between a processor and an I/O device
may require a cooperative exchange of data
• I/O controller must be ready to accept new data or command
» this may depend on the I/O device
• I/O controller must inform processor when new data is available or
previous command has been completed
• control and status registers within the I/O controller facilitate this
cooperation
• cooperative mechanism may be implemented:
» entirely by software - polled I/O
» by both software and hardware - interrupt driven I/O
•
Polling is the programmed interrogation of an I/O controller for a
specific status condition.
• is the device ready?
• does the controller have new data available?
• has the controller finished the previous operation?
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Example I/O Controller
Status
Register
new data
received
CPU
Data
Register
Pep/6
Address Decoder
address
keyboard
asdfghkjkl ;
data
System bus
Memory
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Polled I/O Example Code
kbStatus .EQUATE h#0A00
; Address of keyboard status register.
kbData: .EQUATE h#0A01 ; Address of keyboard data register.
readyBit:.EQUATE h#8000 ; Leftmost bit in status register
; indicates if keyboard has a character.
buffer: .BLOCK d#10
; Character into which to read the input.
bufLen: .EQUATE d#10
; Length of array.
;
;
initialize B and X so that we can use indexed addressing
to fill buffer
LOADB buffer,i
LOADX d#0,i
;x=0
LOADA d#0,i
; clear accumulator, including upper byte
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Polled I/O Example Code (cont’d)
poll:
LDBYTA kbStatus,d ; start of "polling" loop
ANDA readyBit,i ; mask to test ONLY the ready bit
BREQ poll
; no data ready yet, go back and check again
LDBYTA kbData,d ; buffer[x] = input char
;
;
;
;
the keyboard controller hardware detects the reading of the
keyboard data register and in response, automatically resets
the ready bit in the status register in preparation for the next
key depression.
STBYTA buffer,x
ADDX d#1,i
COMPX bufLen,i
BRLT poll
LOADA d#0,i
STOREA ,x
……
; x = x + 1 (point to next free buffer location)
; exit when x >= bufLen
; not done yet, get next character
; done. put null terminate character
; at end of buffer.
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Interrupts
• interrupt: a transfer of program control, similar to a
subroutine call, to a pre-defined location
•
interrupt types:
• synchronous (software traps) discussed earlier
• asynchronous (hardware interrupt)
» in response to an externally generated interrupt request signal (IRQ)
» response to IRQ can be usually be enable/disabled by a bit in the
CPU’s status register (but not in PEP/6)
I=0 ; handle interrupt (CLI : Clear Interrupt Flag instruction)
I=1 ; ignore interrupt ( SEI : Set Interrupt Flag instruction)
» test for IRQ automatically done by CPU hardware before fetching
each instruction.
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Hardware Interrupt Handling:
• interrupt action (taken by hardware):
• save return information: PC, CPU Register, Status flags I, NZCV
on stack
• Set I bit in Status flags register to prevent being interrupted by
another interrupt
• jump to address contained in interrupt vector table
» A fixed series of locations in memory which hold an entry for each
possible cause of interrupt or exception condition. Each entry consists
of an address of the start of the exception or “interrupt service
routine” for that specific interrupt.
» Pep/6 has only a one entry interrupt vector table at h#0FFE.
•
Last instruction of interrupt service routine MUST be a RTI instruction
which will return control to the interrupted program.
• RTI instruction pops flags PC, Registers, flags from stack
• Restored flags also restores previous state of I bit in flags register
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Interrupt Service Routine
• Moves data between a memory data buffer and the I/O
controller data register
• May be a simple transfer or a co-operative data exchange
• Should be as simple and short as possible and thus should include
minimal data processing.
• If multiple devices use common IRQ signal, ISR must include
code to identify and prioritize devices(s) causing current assertion
of IRQ signal.
» Higher speed devices should have higher priority in the sequence of
servicing interrupts from multiple devices
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Interrupt performance enough?
•
Interrupt-driven I/O spares the CPU from wasting time in polling loops
waiting for slow devices.
• Fast devices, like disk drives, present a different problem, because they
transfer large volumes of data in a short time.
• If the CPU needed to be involved in the transfer of each individual byte or
word of these transfers, it would spend a great deal of time doing I/O.
•
Think about a SCSI disk drive transferring even 10 megabytes per
second.
• If the CPU had to service an interrupt for every 4-byte word that the disk
reads, that would mean about two and a half million interrupts per second.
((10 * 1024 * 1024)/(4) = 2621440).
• If it took 100 instructions worth of computing to invoke the interrupt
handler, transfer the word between memory and the disk, and return to the
application program
• a machine capable of executing 250 million instructions a second would
be spending all its time doing disk I/O, whenever the disk was transferring
data.
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• The solution is to add a device that has the ability
transferring data between an I/O device and memory
without the CPU's intervention.
• This device is known as direct memory access (DMA) controller.
• the DMA controller may be part of an I/O Controller or may exist
as a separate system device available to multiple I/O Controllers.
• depending on the system architecture, DMA data transfers
between the I/O Controller and memory may be a one step process
(I/O ó Memory) or a two step process (I/O ó DMA Controller
ó Memory)
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DMA Operation
• Steps in a DMA operation:
1. The CPU initializes the DMA controller registers with
–
–
–
–
the address to read from or write to;
the number of bytes or words to transfer
the direction of the transfer (from the device to memory for input, or from
memory to the device for output)
and then goes on to do other computation.
2. The DMA controller manages the data transfer between the device
and the specified address in memory, becoming bus master and
"stealing" bus cycles from the CPU to transfer each byte or word.
3. When the transfer is complete, the controller raises an interrupt to
tell the CPU.
• The CPU deals with one interrupt per transfer, instead of one per byte or
word of data transferred
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Programmed I/O versus DMA I/O
CPU
I/O
Controller
Memory
Programmed I/O: 2 steps – CPU ó
ó memory; CPU ó
ó I/O
Control information
CPU
DMA
Memory
I/O
Controller
Controller
DMA I/O: single step – Memory ó
ó I/O
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Three techniques for input of a block of data.
*Only req'd by some
types of I/O controllers
Issue Command
to I/O Controller
CPU =>I/O
Issue Command
CPU =>I/O
Issue Block Read
Command to DMA
Controller
to I/O Controller
Do Something Else
Read Status of
I/O => CPU
Read Status of
I/O => CPU
I/O Module
Read Status
Interrupt
I/O Module
(See Figure 2)
Not
Check
Error
Check
Error
Status
Condition
Status
Condition
Read Byte from
Read Byte from
I/O => CPU
I/O Module
Write Byte
I/O => CPU
I/O Module
Write Byte
CPU =>Memory
into Memory
CPU =>Memory
into Memory
RTI Instruction
No
Interrupt Handler (Interrupt Service Routine)
Ready
CPU =>I/O
Do Something Else
I/O => CPU
of
Interrupt
DMA Module
(DMA Done)
Next Instruction
(c) DMA I/O
No
Done?
Done?
Yes
Next Instruction
(a) Programmed I/O
Figure 1.
Yes
Next Instruction
(b) Interrupt -Driven I/O
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Interrupt Processing
Process Interrupt:
CPU finishes
Move data between
I/O controller and
memory
execution of current
Hardware
instruction.
CPU pushes registers and
RTI instruction:
flags I, NZVC on stack
Restores CPU registers from values
saved on stack
Software (Interrupt Service Routine)
I/O controller
Asserts IRQ signal
Back to interrupted process
CPU loads PC with address of first
instruction of Interrupt Service Routine
from Interrupt Vector Table
Figure 2.
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I/O and the Operating System
User
Requesting Process
Device Driver
Operating
System
Kernel
•
Interrupt Handler
Hardware
data transfer
Generally speaking, user application programs do not have direct
access to I/O hardware. They must request access via the Operating
System. This is for reasons of:
•
•
•
•
resource sharing and scheduling
protection (security, reliability)
consistency and ease of programming
portability and platform independence
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