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Short Channel Effects
in MOSFETs
Fabio D’Agostino
Daniele Quercia
Fall, 2000
Presentation Outline
• Short-Channel Devices
• Short-Channel Effects (SCE)
• The modification of the threshold voltage due to SCE
• A numerical example
• Simulation: SCE impacts on the threshold voltage
• Simualtion: limiting effect of the saturation velocity
• Conclusion
Definition
• What is a “short-channel device”?
• A MOSFET is considered to be short when the channel
length is the same order of magnitude as the depletionlayer widths (xdD, xdS)
Short Channel Effects
• Five different physical phenonomena have to be
considered in short-channel devices:
•Drain induced barrier lowering and Punchthrough
•Surface scattering
•Velocity saturation
•Impact ionization
•Hot electrons
Drain-induced barrier lowering (DIBL)
• The electrons (carriers) in the channel face a potential
barrier that blocks their flows
• The potential barrier, in small-geometry MOSFETs, is
controlled by a two-dimensional electric field vector (in
other words by both VGS and VDS)
• If the drain voltage is increased the potential barrier
in the channel decreases, leading to
Drain-Induced Barrier Lowering (DIBL)
Drain-induced barrier lowering (DIBL) and Punchthrough
• Under DIBL condiction electrons can flow between the
source and drain even if VGS < VT
• The channel current that flows in this case is called
subthreshold current
Punchthrough
• The DIBL phenomenon can be accompanied by the socalled punchthrough, that occurs when the depletion
region surrounding the drain extends to the source
• Punchthrough minimized with thinner oxide, larger
substrate doping (and longer channel!)
Surface scattering
• For small-geometry MOSFETs, the electrons mobility in
the channel depends on a two-dimensional electric field
(x, y)
Surface scattering
• The surface scattering occurs when electrons are
accelerated toward the surface by the vertical
component of the electric field x
• The collision of the electrons causes a reduction in the
mobility
•Electrons moves with great difficult parallel to the
interface
•The average surface mobility is about half as much
as that of the bulk mobility
Velocity saturation
• For low y the electron drift velocity vde in the channel
varies linearly with the electric field intensity
• As y increases above 104 V/cm the drift velocity tends
to approach a saturation value of vde(sat)=107 cm/s
around y =105 V/cm
• The velocity saturation reduces the transconductance
of short-channel devices in the saturation condiction,
as the following formula shows:
gm = W Cox vde(sat)
Impact ionization
• The presence of high longitudinal fields can
accelerate electrons that may be able of ionizing Si
atoms by impacting against them
• Normally most of the e- are attracted by the drain, so
it is plausible a higher concentration of holes near the
source
• If the holes concentration on the source is able to
creates a voltage drop on the source-substrate n-p
junction of about 0.6V then
•e- may be injected from source to substrate
•e- travel toward the drain, increasing their energy
and create new e-h pairs
•e- may escape the drain fields and afect other
devices
Hot electrons
• The channel Hot Electrons effect is caused by
electrons flowing in the channel for large VDS
• e- arriving at the Si-SiO2 interface with enough kinetic
energy to surmount the surface potential barrier are
injected into the oxide
• This may degrade permanently the C-V characteristics
of a MOSFETs
The modification of the
threshold voltage
due to short-channel effects
Modification of VTH due to SCE
Equation giving the threshold voltage at
zero-bias
 1 
qDI
 2q   Si  N A 2 F  
VT 0  VFB  2F  
Cox
 Cox 
accurate for large MOS transistors
not accurate for short-channel MOS transistors
the amount of bulk charge is overestimated
Modification of VTH due to SCE
Large MOS transistor:
the deplition is
only due to the electric field
created by the gate voltage.
Small-geometry transistor:
in addition to
the previous contribution, the
deplition charge near n+ regions is
induced by p-n junctions.
Modification of VTH due to SCE
Modification of VTH due to SCE
The bulk depletion charge is smaller than
expected
the threshold voltage expression must be
modified to account for this reduction:
VT 0( shortchannel)  VT 0  VT 0
VT0: zero-bias
threshold
voltage
VT0: threshold
voltage shift
Modification of VTH due to SCE
We find the following relationship:
x
2


x

x
j
dD
dm  x j  LD 
2
2
Modification of VTH due to SCE
… and solving for  LD we obtain :

LD   x j  x  x  x
2
j
where
2
dm
2
dD
 2x x
j dD


2 xdD

 x j 1
 1


xj


 2 
xdD   Si VDS  0 
 qN A 
Similarly, the length  LS can also be found as
follows:


2
x
LS  x j  1  dS  1


x
j


where
 2 Si 
0 
xdS  
 qN A 
Modification of VTH due to SCE
The amount of the threshold voltage reduction
 VT0 due to short-channel effects can be found
as:
 

x j 
1
2 xdD
2
x
dS
VT 0 
 2q Si N A 2 F 
  1
 1   1 
 1
 

Cox
2 L 
xj
x
j
 


Modification of VTH due to SCE
Numerical example
We consider an n-channel MOS process with the following
parameters:
.substrate doping density NA=1016 cm-3,
.polysilicon gate doping density ND (gate) = 2 1020 cm-3,
.gate oxide tickness tox= 50 nm,
.oxide-interface fixed charge density Nox=4*1010cm-2 ,
.source and drain diffusion doping density ND= 1017 cm-3.
In addition, we assume that the channel region is implanted
with p-type impurities
(impurity concentration NI= 2 1011 cm-2 )
Moreover, the junction depth of the source and drain diffusion
regions is xj=1.0 mm.
Modification of VTH due to SCE
We obtain …
VT0= 0.855V -  VT0 ;
where
___________
VT0= ( 0.343/ L[mm] ) * (-0.724 +  ( 1 + 2 xdD)
_________________
xDd =  0.13 (0.76 + VDS)
Modification of VTH due to SCE
 … and plotting the variation of the threshold
voltage with the channel lenght
(Vth vs. L)
@ Vds=1V [-----] Vds=3V [_._._] Vds=5V [_]
0.9
Vth: Threshold voltage [V]
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0
1
2
3
4
L: Channel length [um]
5
6
Simulation: impact of SCE on the threshold voltage
• We simulate four nMOSFETs in parallel, with different
channel lengths and widths
• All the transistors have the same parameters; LEVEL 2
of Pspice is used
• For each transistor we generate the ID-VGS
characteristic at VDS = 0.1V
• The plots show how devices with smaller geometry have
higher drain currents at the same gate-to-source
voltage (i.e., smaller threshold voltages)
Simulation: impact of SCE on the threshold voltage
Simulation: the limiting effects of the saturation velocity
• We simulate two nMOSFETs in parallel, with the same
channel length and width
• One transistor has a limited saturation velocity of
vde(sat) = 2·106 cm/s; LEVEL 2 of Pspice is used
• For each transistor we generate the ID-VDS
characteristic at VGS = 5V
• The plots show the reduction of the transcoductance in
the saturation mode
Simulation: the limiting effects of the saturation velocity
Conclusion
• SCE are governed by complex physical phenomena
that can be mainly related to the
Influence of both vertical and horizontal
electric field components on the flow
of the electrons in the channel
• Usually SCE interacts the one with the other
• SCE should be carefully considered in order to
evaluate their impact on the general behaviour of
the device, both for short-term and long-term