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Digital Integrated
Circuits
A Design Perspective
The Inverter
© Digital Integrated Circuits2nd
Inverter
The CMOS Inverter: A First Glance
V DD
-Nucleus of ICs
-Analysis can be extended to study
Complex logic gates (NAND/NOR/XOR)
V in
V out
CL
Cost (complexity and area)
Robustness (static/steady state behavior)
Performance (dynamic/transient response)
Energy efficiency (power/energy consumption)
© Digital Integrated Circuits2nd
Inverter
CMOS Inverter
N Well
VDD
VDD
PMOS
2l
Contacts
PMOS
In
Out
In
Out
Metal 1
Polysilicon
NMOS
NMOS
GND
© Digital Integrated Circuits2nd
Inverter
Two Inverters
Share power and ground
Abut cells
VDD
Connect in Metal
© Digital Integrated Circuits2nd
Inverter
CMOS Inverter
First-Order DC Analysis
V DD
V DD
• Low and High o/p levels equal
VDD and GND (High Noise Margin)
Rp
V out
V out
VOL = 0
VOH = VDD
VM = f(Rn, Rp)
• Ratioless (logic levels do not
depend on device sizes)
• Vout is always connected to either
VDD or ground (Low o/p impedance)
therefore, Less sensitive to noise.
Rn
• High i/p impedance (Fanout-large)
•No static power dissipation
V in = V DD
© Digital Integrated Circuits2nd
V in = 0
Inverter
CMOS Inverter: Transient Response
V DD
Rp
V DD
tpHL = f(R on.CL)
Charging
= 0.69 RonCL
V out
V out
CL
CL
Rn
discharging
V in = 0
V in = V DD
(a) Low-to-high
(b) High-to-low
© Digital Integrated Circuits2nd
-For building fast
gates, keep either
CL small or decrease
the ON resistance
of FET
-RON is decreased by
Increasing W/L ratio
NOTE:RON is not fixed
Inverter
Voltage Transfer
Characteristic
© Digital Integrated Circuits2nd
Inverter
VDD
CMOS Inverter Load Characteristics
PMOS
In
Out
NMOS
ID n
PMOS
Vin = 0
Vin = 2.5
Vin = 0.5
Vin = 2
Vin = 1
Vin = 1.5
Vin = 1.5
Vin = 1
Vin = 1.5
Vin = 2
Vin = 2.5
NMOS
Vin = 1
Vin = 0.5
Vin = 0
Vout
© Digital Integrated Circuits2nd
Inverter
CMOS Inverter VTC
res: Resisitive/ON
NMOS off
PMOS res
2.5
Vout
1.5
2
NMOS s at
PMOS res
1
VM
NMOS sat
PMOS sat
0.5
NMOS res
PMOS sat
0.5
© Digital Integrated Circuits2nd
1
1.5
2
NMOS res
PMOS off
2.5
Vin
Inverter
Switching Threshold as a function
of Transistor Ratio
VDD
PMOS
1.8
1.7
1.6
1.5
M
V (V)
1.4
1.3
In
-VM is insensitive to
small variations in
W/L , ie., VTC
remains unaffected
-Increasing W of
PMOS or NMOS
moves VM towards
VDD or GND
VM=(rVDD)/(1+r)
Out
NMOS
1.2
1.1
1
0.9
0.8
10
0
10
W /W
© Digital Integrated
Circuits2nd
p
n
1
Inverter
VM=(rVDD)/(1+r)
considering VDD is very large
VM= VDD/2 when r =1
To move VM upwards, a larger value of r is required, which means making the
PMOS wider (stronger).
(W/L)p= (W/L)n X (VDSATn K’n)/ (VDSATp K’p)
Strengthening the NMOS on the other hand, moves VM closer to GND
© Digital Integrated Circuits2nd
Inverter
Changing the inverter threshold
can improve the circuit reliability
© Digital Integrated Circuits2nd
Inverter
Determining VIH and VIL (Noise Margin)
Vout
V OH
VM
V in
V OL
V IL
V IH
A simplified approach
© Digital Integrated Circuits2nd
Inverter
Inverter Gain
CLM consider
(1+λVout)
previous equation: equating saturation currents
of PMOS and NMOS and then differentiating to find
dVout/dVin = g ; put VM = Vin
Find dVout/dVin = g by ignoring
some second order terms
-high gain in transition
region (useful for amplifier
applications)
ID(VM) is current when Vin=VM
© Digital Integrated Circuits2nd
Inverter
#
an inverter in 0.25 um technology
PMOS to NMOS ratio of 3.4
NMOS transistor minimum size (Wn=0.375 um Ln=0.25 um)
(59 uA)
VM=1.25 V
--Find gain g
-- Find Noise Margins
(* First find ID(Vin=VM); use k’n = 115 x 10-6 , k’p = 30 x 10-6 ,VDSATn= 0.63 V,
VDSATp= 1.0 V, VTn=0.43 V, VTp=0.4 V, λn=0.06, λp= -0.1 ;
THEN find ‘g’ and then noise margins)
#
Simulate an inverter with same parameters and compare the calculated and
simulated results
© Digital Integrated Circuits2nd
Inverter
Inverter Gain
calculated values of:
VIL= 1.2 V, VIH = 1.3 V, NML=NMH = 1.2 V
simulated VTC and gain in 0.25 um process
0
2.5
-2
2
-4
-6
gain
Vout(V)
1.5
-8
-10
1
-12
-14
0.5
-16
0
0
0.5
1.5
1
V (V)
in
2
2.5
-18
0
0.5
1
1.5
2
V (V)
in
The actual values of VIL= 1.03 V, VIH = 1.45 V, NML= 1.03 V, NMH = 1.05 V
© Digital Integrated Circuits2nd
Inverter
2.5
#calculated values of:
VIL= 1.2 V, VIH = 1.3 V, NML=NMH = 1.2 V
#The actual values of VIL= 1.03 V, VIH = 1.45 V, NML= 1.03 V, NMH = 1.05 V
These values are lower than those predicted; for two reasons
1) Gain equation overestimates the gain. From gain plot, the maximum gain (at VM)
equals only 17. This reduced gain would yield values for VIL and VIH of 1.17 V
and 1.33 V. (operating conditions: velocity saturation ?)
2) The gain expression are useful as first order approximations only.
© Digital Integrated Circuits2nd
Inverter
Supply Voltage (VDD) Scaling
-subthreshold operation
-Low switching current/slow
Operation (watches)
-sensitive to noise (N don’t scale)
*trend is to reduce device dimensions and supply voltage,
however, threshold voltage is kept constant
2.5
0.2
2
0.15
Vout (V)
Vout(V)
1.5
1
0.1
0.05
0.5
Gain=-1
0
0
0.5
1.5
1
2
V (V)
in
Reducing VDD improves gain
© Digital Integrated Circuits2nd
2.5
0
0
0.05
0.1
V (V)
0.15
0.2
in
Gain deteriorates at very low supply voltages
Inverter
Why not opt for low voltage operation when the high gain
can be achieved at lower supply voltages ?
© Digital Integrated Circuits2nd
Inverter
Why not opt for low voltage operation when the high gain
can be achieved at lower supply voltages ?
--delay ?
--sensitive dc characteristics ?
--noise sensitive ?
Supply must be at least a couple times φT =kT/q
(=25 mV at room
temperature), thermal noise becomes an issue in unreliable operation.
The only way to get CMOS inverters to operate below 100 mV is to reduce the
ambient temperature, or in other words to cool the circuit.
© Digital Integrated Circuits2nd
Inverter
Impact of Process Variations
(Robustness)
2.5
2
Good PMOS
Bad NMOS
The good device has
smaller tox(-3nm),
smaller L(-25nm),
higher W(+30nm),
smaller threshold
(-60mV)
Vout(V)
1.5
Nominal
1
Good NMOS
Bad PMOS
0.5
0
0
*Operation of the
gate is insensitive to
process variations
0.5
1
1.5
2
2.5
Vin (V)
© Digital Integrated Circuits2nd
Inverter
Parasitics affecting delay
© Digital Integrated Circuits2nd
Inverter
Parasitics affecting delay
M1 and M2 are either in cut-off or in the saturation mode (up to 50%
point) of the output transient.
gate-drain capacitors: Cgd12 = 2 CGD0W (with CGD0 the overlap
capacitance per unit width as used in the SPICE model). [*Miller
effect]
(non-linear)
A multiplication factor Keq is introduced to relate the linearized
capacitor to the value of the junction capacitance under zero-bias
conditions.
© Digital Integrated Circuits2nd
Inverter
[Dally 98]
© Digital Integrated Circuits2nd
Inverter
Parasitics affecting delay
© Digital Integrated Circuits2nd
Inverter
Problem…
Find Keq and Keqsw
© Digital Integrated Circuits2nd
Inverter
© Digital Integrated Circuits2nd
Inverter
Solution…
© Digital Integrated Circuits2nd
Inverter
Solution…
© Digital Integrated Circuits2nd
Inverter
Length, width,
Fan-out distance
and number
*It assumes that all components of the gate capacitance are connected between Vout and GND (or VDD), and ignores
the Miller effect on the gate-drain capacitances.
Second approximation is that the channel capacitance of the connecting gate is constant over the interval of interest.
[10% error]
© Digital Integrated Circuits2nd
Inverter
© Digital Integrated Circuits2nd
Inverter
0.25 um CMOS technology. VDD = 2.5 V.
From the layout, derive the transistor sizes, diffusion areas, and perimeters.
As an example, we will derive the drain area and perimeter for the NMOS transistor. The drain area is formed by the metal-diffusion contact, which has an area of
and the rectangle between contact and gate, which has an area of
This results in a total area of AD=
The perimeter of the drain area is rather involved and consists of the following components
(going counterclockwise): 5 + 4 + 4 + 1 +1=
*Notice that the gate side of the drain perimeter is not included, as this is not considered a
part of the side-wall
Similarly, the drain area and perimeter of the PMOS transistor are found
© Digital Integrated Circuits2nd
Inverter
drain area and perimeter of the PMOS transistor
Wire capacitance Cw can also be calculated
This physical information can be combined with the approximations
derived above to come up with an estimation of CL using Table 3-5
© Digital Integrated Circuits2nd
Inverter
© Digital Integrated Circuits2nd
Inverter
© Digital Integrated Circuits2nd
Inverter
© Digital Integrated Circuits2nd
Inverter
Assignment-5 (Due date: 22/09/14
Multiply each dimension in the layout by 8 (eight) so that channel length is 2 um now
and other dimensions also change. Find the propagation delay at the output of first
inverter using SPICE simulation and compare it with the one obtained by finding CL,
Req, Keq, etcetra using analytical expressions (as taught in the class).
© Digital Integrated Circuits2nd
Inverter
Propagation Delay
© Digital Integrated Circuits2nd
Inverter
CMOS Inverter Propagation Delay
Approach 1
VDD
tpHL = CL Vswing/2
Iav
CL
Vout
~
Iav
CL
kn VDD
Vin = V DD
© Digital Integrated Circuits2nd
Inverter
CMOS Inverter Propagation Delay
Approach 2
VDD
tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
ln(0.5)
Vout
CL
Ron
1
VDD
0.5
0.36
Vin = V DD
RonCL
© Digital Integrated Circuits2nd
t
Inverter
Transient Response
3
?
*Cgd that couples i/p to o/p even before transistor is ON
Vin
2.5
*Overshoots result in delay
Vout(V)
2
tp = 0.69 CL (Reqn+Reqp)/2
1.5
1
tp = (tpLH+tpHL)/2
Vout
tpLH
tpHL
0.5
0
-0.5
0
0.5
1
1.5
t (sec)
© Digital Integrated Circuits2nd
2
2.5
-10
x 10
Inverter
Delay as a function of VDD
optimize/manipulate delay
5.5
5
tp(normalized)
4.5
4
*CLM ignored here
3.5
3
VDD>> VTn + VDSATn/2
Delay independent of supply
2.5
2
1.5
1
0.8
1
1.2
1.4
1.6
V
1.8
2
2.2
2.4
(V)
DD
© Digital Integrated Circuits2nd
Inverter
Design for Performance
 Keep
capacitances small
 Increase transistor sizes
 watch out for self-loading!
 Increase
VDD (????)
- (oxide breakdown, hot electron effects)
- (energy-performance tradeoff)
© Digital Integrated Circuits2nd
Inverter
Device Sizing
-11
3.8
x 10
(for fixed load)
3.6
3.4
Cint=SCref
Req=Rref /S
3.2
tp(sec)
-PMOS wider: Rn=Rp,
tpLH=tpHL,
symmetrical VTC,
Noise margin
-Delay can be smaller if
PMOS is small (else
tpHL degrades)
3
2.8
Self-loading effect:
Intrinsic capacitances
dominate
2.6
2.4
Slow further improvement
in delay
2.2
2
2
4
6
© Digital Integrated Circuits2nd
8
S
10
12
14
*Increasing transistor
size -> silicon area increases
Inverter
Optimum NMOS/PMOS ratio
-11
5
x 10
tpHL
tpLH
while widening the PMOS improves the
tpLH of the inverter by increasing the
charging current, it also degrades the
tpHL by cause of a larger parasitic
capacitance
tp(sec)
4.5
tp
4
How to derive optimum
size ?
3.5
b = Wp/Wn
3
1
1.5
2
2.5
3
3.5
4
4.5
5
b
Fig. 5.18
© Digital Integrated Circuits2nd
Inverter
Inverter Sizing
© Digital Integrated Circuits2nd
Inverter
Finding Optimal Sizing ratio β
• β=(W/L)p / (W/L)n
• Assumed that WP = 2WN
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays (symmetrical VTC)
• doesn’t imply minimum propagation delay
• If symmetry and Noise margins are not important then it is
possible to speed up inverter by reducing PMOS width.
(widening PMOS improves tPLH by increasing charging current, but it
degrades tPHL by causing larger parasitic capacitance)
•A transistor ratio is required that optimizes propagation delay
of the inverter
© Digital Integrated Circuits2nd
Inverter
Optimal Sizing ratio β …..
In
1
CL1
2
3
Out
CL
CL1 is the load capacitance of first gate
• CL1=(Cdp1 + Cdn1) + (Cgp2 + Cgn2)+ CW
•When β=(W/L)p / (W/L)n is applied (all other transistor
parameters also scale by the same factor)
•Cdp1 ≈ βCdn1 and Cgp2 ≈ βCgn2
• so that CL1= (1+β)(Cdn1 + Cgn2)+ CW
• from tp = 0.69 CL (Reqn+Reqp)/2


Reqp 

0.69
1  b  Cdn1  Cgn2  CW  Reqn 
tp 

2
b


© Digital Integrated Circuits2nd


Inverter
Optimal Sizing ratio β …..



t p  0.345 1  b  Cdn1  C gn 2  CW
where
r


r
Reqn 1  
 b
Reqp
Reqn
The optimum value of β is found by setting ∂tp/∂β=0
b opt 


C
W

r 1 


C

C
dn
1
gn
2


Eqn. 5.26
If the wiring capacitance dominates, larger values of β should be used.
Smaller device sizes yield faster designs at the expense of
Symmetry and noise margin
© Digital Integrated Circuits2nd
Inverter
Consider again our standard design example. From the values of the
equivalent resistances (Table 3.3), we find that a ratio β of 2.4 (= 31 kW /
13 kW) would yield a symmetrical transient response. Eq. (5.26) now
predicts that the device ratio for an optimal performance should equal 1.6.
These results are verified in Figure 5.18, which plots the simulated
propagation delay as a function of the transistor ratio b. The graph clearly
illustrates how a changing β trades off between tpLH and tpHL. The
optimum point occurs around β = 1.9,
© Digital Integrated Circuits2nd
Inverter
Inverter Chain
In
Out
CL
If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?
May need some additional constraints.
© Digital Integrated Circuits2nd
Inverter
Inverter Delay
• Minimum length devices, L=0.25mm
• Assume that for WP = 2WN =2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
• Analyze as an RC network
2W
W
RP  RN  Runit
Delay (D): tpHL = (ln 2) RNCL
Load for the next stage:
© Digital Integrated Circuits2nd
tpLH = (ln 2) RPCL
C gin  3Cunit
Inverter
Inverter with Load
CP = 2Cunit
Delay
2W
W
CN = Cunit
Cint
CL
Load
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)
= Delay (Internal) + Delay (Load)
© Digital Integrated Circuits2nd
Inverter
C L  Cint  Cext
t p  0.69 Req (Cint  Cext )

Cext

 0.69 Req Cint 1 
Cint

© Digital Integrated Circuits2nd


C
  t p 0 1  ext
Cint





Inverter
How transistor sizing impacts the performance of a gate ?
Req 
Rref
S
, Cint  SCiref
sizing factor S, which relates the transistor sizes of our inverter to a
reference gate—typically a minimum-sized inverter
• tp0=0.69 ReqCint is independent of sizing of gate; and is determined purely
by technology and inverter layout
•Making S infinitely large yields the maximum obtainable performance gain,
eliminating the impact of any external load, and reducing the delay to the
intrinsic one.
•S larger than Cext/Cint produce similar result at the cost of extra silicon area.
© Digital Integrated Circuits2nd
Inverter
Delay Formula


t p  0.69 Req Cint 1  Cext / C g  t p 0 1  f /  
*Inverter delay as a function of load capacitance and
input capacitance
Cint = Cg with   1 for most submicron technologies
f = Cext/Cg
- effective fanout :Cout/Cin
Req 
Rref
S
, Cint  SCiref
tp0 = 0.69ReqCint
© Digital Integrated Circuits2nd
Inverter
Apply to Inverter Chain
Cg1 and CL are given
In
Out
1
2
N
CL
tp = tp1 + tp2 + …+ tpN
 C g , j 1 
 delay expression for j-th inverter stage
t p , j  t p 0 1 
 C g , j 


N
N 
C gin , j 1 
, with C gin , N 1  CL
t p   t p, j  t p 0  1 



C
gin
,
j
j 1
i 1 

Total delay of the chain
© Digital Integrated Circuits2nd
Inverter
Optimal Tapering for Given N
--Delay equation has N - 1 unknowns, Cg2 – Cg,N
--Minimum delay can be found by finding N - 1 partial derivatives and equating them to zero ; ∂tp/∂Cg,j = 0
--Result: Cg,j+1/Cg,j = Cg,j /Cg,j-1 with j=2 to N
[Eqn. 1]
--For example: j=2 gives Cg3/Cg2 = Cg2/Cg1
--Or Optimum Size of each stage is the geometric mean of
two neighbors
C g , j  C g , j 1C g , j 1
from Eqn.1
- this means that each inverter is sized up by the same
factor ‘f ’ with respect to the preceding gate
- each stage has the same effective fanout (Cout/Cin)
- each stage has the same delay
© Digital Integrated Circuits2nd
Inverter
Optimum Delay and Number of
Stages
When each stage is sized by f and has same eff. fanout Fj=F :
f
N
 F  C L / C g ,1
Effective fanout of each stage ‘F’:
f NF
Where f is sizing factor
Minimum path delay through the chain

t p  Nt p 0 1  N F / 
© Digital Integrated Circuits2nd

Inverter
Example
In
C1
Out
CL= 8 C1
Problem: Find the optimum sizes of all the inverters in this chain
so that the delay is minimum.
© Digital Integrated Circuits2nd
Inverter
Example
In
C1
Out
1
f
f2
CL= 8 C1
CL/C1 has to be evenly distributed across N = 3 stages:
f
© Digital Integrated Circuits2nd
3
 8
2
Inverter
Buffer Design
- Size the inverters
1
64
1
64
1
64
1
64
© Digital Integrated Circuits2nd
Consider tp0=1
- Find delay
Inverter
Buffer Design
1
f
tp
1
64
65
2
8
18
64
3
4
15
64
4
2.8
15.3
64
1
8
1
4
16
2.8
8
1
N
64
© Digital Integrated Circuits2nd
22.6
Inverter
Power Dissipation
© Digital Integrated Circuits2nd
Inverter
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors
© Digital Integrated Circuits2nd
Inverter
Dynamic Power Dissipation
Vdd
Vin
Vout
CL
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Not a function of transistor sizes!
Need to reduce CL, Vdd, and f to reduce power.
© Digital Integrated Circuits2nd
Inverter
Short Circuit Currents
Vd d
Vin
Vout
CL
IVDD (mA)
0.15
0.10
0.05
0.0
© Digital Integrated Circuits2nd
1.0
2.0
3.0
Vin (V)
4.0
5.0
Inverter
Leakage
Vd d
Vout
Drain Junction
Leakage
Sub-Threshold
Current
Sub-threshold current one of most compelling issues
Sub-Threshold
in low-energy
circuitCurrent
design!Dominant Factor
© Digital Integrated Circuits2nd
Inverter
Reverse-Biased Diode Leakage
GATE
p+
p+
N
Reverse Leakage Current
+
V
- dd
© Digital Integrated Circuits2nd
Inverter
Static Power Consumption
Vd d
Istat
Vout
Vin =5V
CL
Pstat = P(In=1) .Vdd . Istat
Wasted •energy
… over dynamic consumption
Dominates
Should be avoided in almost all cases.
• Not a function of switching frequency
© Digital Integrated Circuits2nd
Inverter
Principles for Power Reduction
 Prime
choice: Reduce voltage!
 Recent years have seen an acceleration in
supply voltage reduction
 Design at very low voltages still open
question (0.6 … 0.9 V by 2010!)
 Reduce
switching activity
 Reduce physical capacitance
© Digital Integrated Circuits2nd
Inverter
Impact of
Technology
Scaling
© Digital Integrated Circuits2nd
Inverter
Goals of Technology Scaling
 Make
things cheaper:
 Want to sell more functions (transistors)
per chip for the same money
 Build same products cheaper, sell the
same part for less money
 Price of a transistor has to be reduced
 But
also want to be faster, smaller,
lower power
© Digital Integrated Circuits2nd
Inverter
Technology Scaling

Goals of scaling the dimensions by 30%:
 Reduce gate delay by 30% (increase operating
frequency by 43%)
 Double transistor density
 Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency
Die size used to increase by 14% per
generation
 Technology generation spans 2-3 years

© Digital Integrated Circuits2nd
Inverter
Technology Evolution (2000 data)
International Technology Roadmap for Semiconductors
Year of
Introduction
1999
Technology node
[nm]
180
Supply [V]
2000
2001
2004
2008
2011
2014
130
90
60
40
30
0.6-0.9
0.5-0.6
0.3-0.6
8
9
9-10
10
3.5-2
7.1-2.5
11-3
14.9
-3.6
1.5-1.8 1.5-1.8 1.2-1.5 0.9-1.2
Wiring levels
6-7
6-7
7
Max frequency
[GHz],Local-Global
1.2
Max mP power [W]
90
106
130
160
171
177
186
Bat. power [W]
1.4
1.7
2.0
2.4
2.1
2.3
2.5
1.6-1.4 2.1-1.6
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm
© Digital Integrated Circuits2nd
Inverter
Technology Evolution (1999)
© Digital Integrated Circuits2nd
Inverter
Technology Scaling (3)
tp decreases by 13%/year
50% every 5 years!
Propagation Delay
© Digital Integrated Circuits2nd
Inverter
Technology Scaling Models
• Full Scaling (Constant Electrical Field)
ideal model — dimensions and voltage scale
together by the same factor S
• Fixed Voltage Scaling
most common model until recently —
only dimensions scale, voltages remain constant
• General Scaling
most realistic for todays situation —
voltages and dimensions scale with different factors
© Digital Integrated Circuits2nd
Inverter
Scaling Relationships for Long Channel Devices
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Inverter
Transistor Scaling
(velocity-saturated devices)
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Inverter