Download LDO design solves load transient problems

ENERGY HARVESTING
LDO design solves load
transient problems
By Sergei Strik
E-mail:[email protected]
Viktor Strik
E-mail: [email protected]
National Semiconductor Estonia
The low dropout (LDO) regulator is widely used in many portable electronics systems such
as cellphones, notebooks and
PDAs. In these mobile applications, LDO design is challenging
due to the need for reduced
power consumption and accurate operation.
As the digital circuit—which
is supplied from the LDO output—switches from one mode
of operation to another, the load
demand on the LDO can change
quickly. This quick change of
load results in a temporary glitch
of the LDO output voltage. But
digital circuits do not react favorably to large voltage variations.
This makes LDO load transient
improvement very important.
Using the conventional LDO
structure, which includes an error amplifier and a pass device as
shown in Figure 1, it is possible
to define the influence of the
load variation on LDO operation.
Variation of LDO load current
changes LDO output voltage
level until the error amplifier
will be able to compensate for
the variation by driving the pass
transistor according to the variation of the load current. There is
always a delay between output
current changing and reaction
of the error amplifier. During this
time voltage spikes at the LDO
output are created. By reducing the delay time it is possible
to minimize the output voltage
error. This delay time has many
causes. One of the main causes
is the time needed for charging the parasitic capacitance of
the pass device. LDOs that are
usually used in portable applications have a maximum output
current in a range of a few hundred milliamps. This requirement
increases the pass device area.
Thus parasitic capacitances Cp1
and Cp2 of the pass device also
increase and can exceed 100pF.
This affects power consumption,
and battery life extension is very
important nowadays.
Hence, small quiescent current
of the LDO is a key parameter, but
it significantly limits parasitic capacitance charging time.
Class AB amp solutions
The most well-known approach
for reducing parasitic capacitance charging time is to use a
Class AB amplifier as error amplifier. Typically, Class AB amplifier is
a complex circuit with two gain
stages. LDO regulator power
transistor adds the third gain
stage. To provide good stability
to this three-stage amplifier, it is
common to use different compensations that reduce bandwidth and increase the reaction
time of the error amplifier.
A variety of solutions exist for
LDO circuits. The basic idea of the
circuits presented here is that the
error amplifier design focuses on
load transient improvement and
quiescent current reduction.
The pass device has a large
parasitic capacitance that creates a low frequency pole for the
output stage of the error amplifier with small quiescent current.
Figure 2 shows an LDO with
Class AB error amplifier. The very
complex structure reduces error
amplifier bandwidth for reaching
good stability. To prevent this effect, an additional buffer should
be implemented to isolate the
high output resistance of the
output stage of the error amplifier from the high load capacitance of the pass device. Such
approach, depicted in Figure 3,
Figure 1: A simplified structure of a conventional LDO is shown.
Figure 2: Using Class AB error amplifiers is a popular approach for reducing
parasitic capacitance charging time, but it reduces error amplifier bandwidth.
however, is not able to avoid the
stability problem. For small quiescent current LDO, bias current Ib
is also small. The pole of the emitter follower is placed quite close
to pole of the error amplifier A1.
In addition, this approach uses an
emitter follower as a buffer. It allows turning the pass device MP
off quickly, but the turn on time is
limited by the small current Ib.
Another disadvantage of a
structure where the main amplifier and buffer are connected in
series is that delay is determined
by the slower part of the circuit.
In the structure shown in
Figure 4, the LDO uses two
amplifiers: error amplifier A1
and current feedback amplifier
A2. The current feedback amplifier has second feedback loop,
EE Times-Asia | October 1-15, 2008 | eetasia.com
Figure 3: An emitter follower used as a buffer helps prevent reduction of the
error amplifier bandwidth, but does not solve stability problems.
which accelerates the reaction
of the LDO. But this amplifier
has a small input resistance and
it can lead to a situation where
the gain of error amplifier A1 is
reduced. Thus, the main parameters of LDO become worse.
The current feedback amplifier has Class AB output stage,
but load possibility of this
amplifier is determined by the
input current. The requirement
of low quiescent current of the
LDO supposes large values of
resistors Rf1, Rf2 and RC, but this
limits the input current of amplifier A2. It means that maximum
output current cannot exceed
a few microamps that are not
enough for fast charging of
the parasitic capacitance of the
power transistor.
Novel structure
In the previous section, different
solutions for LDO load transient
improvement were analyzed.
Using two op amps for driving
the pass device seems to be the
best principle, but it still has several disadvantages.
These disadvantages are
eliminated or reduced when an
operational transconductance
amplifier (OTA) with high gain and
low bandwidth is implemented
as the main error amplifier. This
amplifier determines the main
parameters of LDO. A second
amplifier, also based on OTA, with
relatively small gain and wide
bandwidth monitors the output
of the LDO. The outputs of both
amplifiers are connected in parallel. The proposed structure is
presented in Figure 5.
The main error amplifier A1 is
a standard two stage amplifier
and is used to guarantee good
performance of LDO. Because
A1 is not used for fast-driving
the power transistor MP, it can
have Class A output stage. The
feedback resistors Rf1 and Rf2
determine the output voltage of
the LDO.
The second amplifier has
wide bandwidth and Class AB
output stage for fast-charging
the power transistor parasitic capacitance. The output of the amplifier A2 is connected with the
output of the amplifier A1 and
the gate of power transistor MP.
LDO output is connected to the
non-inverting input of A2 and to
the low-pass filter RC. The output of the low-pass filter is connected to the input of the amplifier A2. This connection creates
zero voltage between inputs of
A2 in steady state condition and
excludes the influence of the
amplifier A2 on the parameters
eetasia.com | October 1-15, 2008 | EE Times-Asia
Figure 4: Using two amplifiers as shown can lead to a situation where the gain
of A1 is reduced, and the main parameters of the LDO become worse.
Figure 5: Using operational transconductance amplifiers with outputs connected in parallel is the novel solution proposed in this article.
of LDO. During fast variation of
the LDO output load, the inverting input of the A2 does not
change its value in case low-pass
filter time constant is larger than
transient time of the load variation. Non-inverting input of A2
follows LDO output voltage and
starts to compensate its variation. Amplifier A1 starts to react
significantly later because of its
low bandwidth. After a certain
time that exceeds the time constant of the low-pass filter, the
A2 is again in steady state condition and does not influence the
parameters of LDO. The possible
structure of OTA A2 is presented
in Figure 6. It has only one gain
stage and Class AB output stage.
The bandwidth is determined by
the bias current Ib.
Figure 7 shows the AC analysis of the proposed LDO structure. Figure 7a shows a simplified
schematic. The equivalent block
diagram of the simplified transfer
function is shown in Figure 7b.
This allows building a magnitude
response of the proposed LDO
operation as seen in Figure 7c.
At low frequencies, the LDO
operation is defined by the main
amplifier A1. At higher frequen-
Figure 6: The possible structure of OTA A2 is shown.
Figure 8: The simulated load transients for parallel amplifier operation (a) and
single amplifier operation (b) are shown.
Figure 9: The measured load transient response is shown.
Figure 7: The AC analysis of the proposed LDO regulator is shown: simplified
schematic (a), equivalent block diagram (b) and magnitude response in (c).
cies, where load transient events
take place, the LDO operation is
determined by the fast amplifier
A2. The RC filter allows separating the operation of parallel amplifiers A1 and A2 so that they do
not work simultaneously.
Figure 8 shows load transient
simulation results of the proposed
LDO structure. The LDO output
voltage behavior in case of paral-
lel amplifier connection is shown
on the left. The figure on the
right represents the case of single
amplifier operation. The output
voltage variation is twice smaller
in parallel amplifier operation.
Proving the design
The proposed LDO regulator circuit was integrated using 0.5µm
CMOS technology. The occupied
area is 0.28mm2. The measurement results are shown in the
table. The maximum current
consumption is 20µA. Greater
reduction can be achieved by
further optimization, but the
tradeoffs are larger chip area,
slower reaction for load variations and degradation of other
main parameters of the LDO
regulator.
The measured load transient
is shown in Figure 9. The LDO
regulator output voltage spikes
are 60mV for load variation from
maximum value to 1mA and
from 1mA to maximum value in
1µs. For slower speed (10µs) of
load variation the LDO regulator
output voltage change is significantly smaller at 18mV.
The measured power supply
rejection ratio at10kHz frequency
with LDO regulator output load
of 20mA is -75dB. The equivalent
output noise was measured
for the frequency range from
10Hz to 100kHz and is equal to
10µVRMS.
Experimental results show
that the proposed LDO voltage
regulator is quite competitive
EE Times-Asia | October 1-15, 2008 | eetasia.com
in the area of small current consumption LDO regulators with
improved load transient.
The frequently met problem
of LDO stability is solved in the
current design by using parallel
connection of two error amplifiers. The proposed LDO structure
has several advantages. The DC
current and low frequency parameters of LDO are determined
by a simple two gain stage Class
A amplifier which is stable and
easy to design. The robust, fast
one gain stage, Class AB amplifier is responsible for fast load
variations and also does not have
any stability problem. The parallel connection of two amplifiers
helps to avoid stability problems.
And, for low quiescent current
LDO regulators, the supply current between amplifiers can be
distributed in optimum ratio.
eetasia.com | October 1-15, 2008 | EE Times-Asia
Parameter
Conditions
Value
Output voltage
1.2…5.0V
Maximum load current
150mA
Quiescent current
20µA
Dropout voltage
IOUT=IMAX
115mV
Full load transient with 1uF
output capacitor
@1mA to IMAX in 1µs
60mV
@ IMAX to 1mA in 1µs
60mV
PSSR
@F=10kHz, IOUT=20mA
-75dB
The main parameters of the proposed LDO regulator are listed.