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7b. Passtransistor and Transmission Gate Logic Institute of Microelectronic Systems Passtransistor Logic: Basic Principle Idea: control 0=open 1=closed Vout Vin Implementation: Vout Vin Vin control Vout 1 0 x 1 1 1 0 0 x 0 1 0 control 7b: Transmission Gate Logic Institute of Microelectronic Systems 2 Passtransistor Logic: NEXOR Realisation B OUT A B A B OUT 0 0 1 0 1 0 1 0 0 1 1 1 A Institute of Microelectronic Systems 7b: Transmission Gate Logic 3 Passtransistor: Charging Characteristics NMOS Vctrl (t ) Vctrl (t < 0) = 0 Vctrl (t >= 0) = VDD VGS Vin = VDD Vout ( t ) Cout Transistor is in Saturation during Charging Process Vout ( t = 0) = 0 Vout (t ) VDD − VT ( VSB ) t 7b: Transmission Gate Logic Institute of Microelectronic Systems 4 Passtransistor Cascades VDD VDD VDD VDD Vin = VDD Vmax = VDD − VT ( Vmax ) Vmax Vmax Vmax Cout Vmax VDD Vin = VDD Vmax,1 = VDD − VT ( Vmax,1 ) Vmax,1 Vin = VDD Vmax, 2 = Vmax,1 − VT ( Vmax, 2 ) Cout Vmax, 2 ≈ VDD − 2VT Institute of Microelectronic Systems 7b: Transmission Gate Logic 5 Passtransistor: Discharging Characteristics Vctrl (t ) NMOS Vctrl (t < 0) = 0 Vctrl (t >= 0) = VDD VGS Vin = 0 Vout ( t ) Transistor is always in Nonsaturation during Discharging Process Cout Vout (t = 0) = VDD − VT ( VSB ) Vout (t ) VDD − VT ( VSB ) t 7b: Transmission Gate Logic Institute of Microelectronic Systems NMOS Passtransistor: Discharging faster than Charging, since Device Impedance is lower in NSat than in Sat 6 Passtransistor: Charging Characteristics PMOS Charging Process: Vctrl (t ) Vctrl (t < 0) = VDD Vctrl (t >= 0) = 0 VGS Vin = VDD The output is charged to VDD (Transistor is initially saturated and goes in nonsaturated mode) Vout ( t ) VDD Vout ( t = 0) = 0 Cout PMOS Discharging Process: Vctrl (t ) Vctrl (t < 0) = VDD Vctrl (t >= 0) = 0 VGS Vin = 0 The output is discharged to VT (Transistor is saturated and finally goes in cut-off mode) Vout ( t ) Cout VDD Vout ( t = 0) = VDD Institute of Microelectronic Systems 7b: Transmission Gate Logic 7 From Passtransistors to Transmission Gates Vctrl Logic Level NMOS PMOS CMOS Logic 0 0 VTP 0 Logic 1 VDD − VTN VDD VDD VDD Vctrl Vout Vin Cout Vin Vctrl I DN + I DP dV = Cout * out dt CMOS Transmission Gate Vout Vctrl Symbol: CMOS Transmission Gate • Bidirectional resistive connection between the input and output terminals • Useful in both analog (e.g. for relay contacts) and in digital design (e.g. for multiplexers) 7b: Transmission Gate Logic Institute of Microelectronic Systems 8 Transmission Gate: Operation States VTP Mp nonsaturated Mp sat. VDD − VTN Mn saturated Final Voltage : VDD Mn cut-off Operation states of the Transistors which are passed over during charging the output from 0 to VDD: Initial Voltage : 0 7b: Transmission Gate Logic Institute of Microelectronic Systems 9 CMOS Transmission Gate: On-Resistance R EQ = R onP R onN R onP + R onN On-resistance of a transmission gate, including body effect VTON = 0.75V , VTOP = − 0.75V γ = 0.5V 0.5 , 2φ F = 0.6V , K p = 20 µA / V 2 , K n = 50 µA / V 2 7b: Transmission Gate Logic Institute of Microelectronic Systems 10 CMOS Transmission Gate (III) • Charge sharing problem VF = C BIGVBIG + C SMALLVSMALL C BIG + C SMALL Example: CSMALL = 0.02 pF, VSMALL = 5 V, VBIG = 0 V CBIG = 0.2 pF (about 10 standard loads in a 0.5 CMOS process) VF = 0.45 V ⇒ The ‘big‘ capacitor has forced node A to a voltage close to a ‘0‘ Node A has to be insulated from node Z by including a buffer (e.g. Inverter) between the 2 nodes, if node A is not strong enough to overcome the ‘big‘ capacitor Institute of Microelectronic Systems 7b: Transmission Gate Logic 11 Transmission Gate Logic Multiplexer: Equivalence (NEXOR): F = AS + BS F = AB + A B Alternate equivalence logic circuit: = A⊕B S B B A A S B F B F A F A S B B 7b: Transmission Gate Logic Institute of Microelectronic Systems 12 Function Implementation with Passtransistor Logic F = bd + abd + abd + bcd Karnaugh Map of F: F 1 0 0 1 0 0 1 0 1 0 1 1 1 1 1 1 Step 1: b a c find minimum decomposition in such a way, that each selected field is depending on one variable or constant 0 or constant 1 only (in our case: decompose with combinations of the literals b and d d Institute of Microelectronic Systems 7b: Transmission Gate Logic 13 Function Implementation with Passtransistor Logic Attach decomposition variables to selection lines Step 2: VDD Determine the line input signals (implement inverted function to compensate output inverter Step 3: Sustainer transistor c a F a 0 b 7b: Transmission Gate Logic b d d Institute of Microelectronic Systems 14