Download Integrated circuits

Integrated circuits
An IC is a complete electronic circuit containing transistors and perhaps diodes,
resistors, capacitors all made from, and on a chip of silicon. They are often packaged
in different ways but the most often seen and used is the duel in line arrangement (dil)
which may have 8, 14, 16 or more pins spaced 0.1” apart.
Scales of integration
Early IC’s had only up to 100 components on the, classed as small-scale integration
(SSI). Then came large-scale integration (LSI) having 1000 to 10000 components.
Now we are using very large-scale devises (VLSI) which have up to 1 million
component parts.
Digital IC’s
A digital IC is classed as decision making devices and use combinational logic,
because their outputs are derived from a combination of inputs. There are two main
families of digital IC’s TTL and CMOS.
TTL
Transistor-Transistor Logic uses bipolar transistors and has the 74 prefix, which
defines, with the aid of further numbers and letters exactly what function it fulfils e.g.,
7400 Quad 2-input NAND
7402 Quad 2-input NOR
7410 Triple 3-input NAND
Other letters indicate manufacturer and packaging.
CMOS
Complementary metal oxide semiconductor uses P and N channel FETs, (field effect
transistors) and uses the sequence 4000 to show the function of the IC.
4001 Quad 2-input NOR
4011 Quad 2-input NAND
4023 Triple 3-input NAND
An example being shown on the next page
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The Buffer
There may be many reasons to use a buffer, a straightforward one being shown below.
Logic Buffer Stage.
Ordinary CMOS or TTL logic gates have very imprecise switching threshold
voltages. This means they cannot be guaranteed to change state at exactly the same
input levels. An improvement is to use a gate call a 'Schmitt Trigger'. These have two
precise input states, Inputs below 1.5Volts are considered logic '0' and those above
1.5Volts are logic '1'. The type of gate can be recognised by the hysteresis symbol
inside the gate diagram.
Apart from the precise timing that can be achieved, the switch over is considerably
faster. The Darlington transistor has high input impedance and so can be connected
directly to a logic gate output without drawing excessive current. This type of
transistor output has low impedance making it suitable for driving high current loads
directly. Note, the symbol shows two NPN transistors inside one package.
So, you can see that the word buffer in this case means that it ‘softens the effect’ and
makes the signal easier to cope with.
Another reasons for buffering is for logic interfacing.
CMOS to TTL Logic Interface.
Different families of logic gates may be connected together, providing the input
voltage requirements and current loading is not exceeded. There are logic packages
available specially designed to provide the correct interfacing.
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Here the use of a bipolar transistor will explain the principle. To make the transistor
conduct it only requires a base emitter voltage of slightly more than 0.6Volts, which
causes base current to flow. Our input varies between 3Volts and 15Volts where the
voltage difference is simply dropped across the series resistor R1.
Encoders
While digital equipment works in binary, humans prefer decimal code. Code
converters are therefore needed and encoders are provided at the input to convert
decimal into binary.
Decimal to BCD Encoder.
Encoding information is changing it from one number representation to another. For
example, changing a decimal value to a BCD code. The BCD value can be determined
using logic circuits called an encoder.
The output of each 'OR' gate will go to logic '1' when any input is taken 'high'.
Decimal zero is the Default State, BCD '0000'.
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In the above case decimal 6 is encoded into binary 0110. Decimal 7 would be 0111,
and so on up to binary 1001.
Decoders. The 2-4 Line Binary Decoder.
The decoder circuit is commonly used for memory addressing. From the two address
bits 'A0' and 'A1' there are four combinations. Each will select one of the four output
lines,
Adding one more address bit doubles the no of lines that can be selected. For
example, 3 address bits for eight lines and four for sixteen. Therefore 2 - 4, 3 - 8, 4 16 etc, line decoders.
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Binary to BCD decoder
The diagram below shows another type of decoder. The converts a binary count into a
format that can be outputted to a seven-segment display. The decoder chip has an
enable pin, four inputs, A, B, C, D, and eight output pins for the seven segments and a
decimal point.
Closing the input button will cause the display to count as long as both chips are
enabled.
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Multiplexers
These are devices that perform the function of a very fast rotating switch,
and connects several input channels, one at a time to a common output line. Each
input will occupy the output for an equal amount of time. The sequence can be
changed by manipulating lines A0, A1, A2 which form three-bit channel select
function.
A0
C
h
a
n
n
e
l
A1
A2
0
1
2
3
Serial output
4
5
Multiplexer
MUX. used as a parallel to
serial converter
Parallel 0
Input
I1
b3, b2,b1,b0
4-to-1
MUX
I2
I3
A1
Clock
A2
2 bit
count
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The serial to parallel converter allows a four bit word to be sent as I0 = b0, I1 = B1 etc.
by means of a 2 bit counter so that the time t1 is derived from 00, t2 from 01, t3
from10, and t4 from 11.
Another application for the MUX is with an array of 7-segment displays. As you have
seen, a display needs a decoder. So, if there are three displays we would need three
decoders, and space, cost, and number of connections becomes an issue. If we can
multiplex the displays only one will be energised at a time, and provided the
frequency is high enough the brightness of the LED's will not be affected and the eye
will not perceive the change. Another advantage is that power consumption is reduced
as only one display is energised at a time.
A fully multiplexed LED array is shown over page. The MUX unit scans D1, D2, D3
in sequence, at the same time enabling the respective input buffers. This is done by
turning on T1, T2, T3, and enabling B1, B2, B3 respectively. Each digit receives the
information related to it, by passing through the decoder, the MUX unit, and the
driver.
Demultiplexing
Multiplexed message must be converted back into parallel. The diagram below
showing the principle.
A De-multiplexer
Y0
MUX input
D
E
M
U
X
Y1
Y2
Y3
Y4
Y5
A0 A1 A2
Address select
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Read Only Memory (ROM)
This is non-volatile memory used for storing data permanently. The user can only
read the data as it is programmed by the manufacturer in accordance with the user's
requirements. A simple ROM memory is shown
MICROPROCESSOR MEMORY.
Programming a ROM (Read Only memory) permanently writes a data state (logic '1'
or '0') to each memory location. Here we are using random binary '0' and '1' for each
cell. In practice each cell is manufactured as logic '1' (diode present). A cell is then
programmed to logic '0' as required by fusing the diode connection, shown here as a
'grey' device.
Reading is a measurement of the voltage developed across the 'Data' resistor due to
the current flowing through a 'good' diode. An open circuit diode will produce logic
'0' as no current flows to generate a voltage or logic level across the resistor for that
particular data line. Note that a 'high' data output can only be derived from the logic
'1' output from the '2 - 4' line decoder when that line is selected.
2-4
Line
Decoder
The pin-outs for a 2048 bit ROM is shown below.
Pin 9
Pin16
TTL74S370 ROM
Pin 16 = VCC. Pin 8 = GND
Pins 9,10,11,12 = DATA OUT
Pin 1 to 7 and 14 & 15 ADDRESS
Setting the appropriate address will
output a 4-bit word residing therein
i.e., 2048 /4 bits = 512 nibbles and 9
address pins = 512 locations
Pin 13 Set allows address in and data
out phases
Pin 1
Pin 8
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Programmable logic devices (PLD)
This is the name for devices that can be set to give logical relationships between the
inputs and outputs. Basically they can consist of AND gates, OR gates and inverters
that can connected together in many ways.
The Programmable Logic Array
AND array
OR array
IMPLICATION
_
A
B
_
B
C
_
C
F1
A
F2 F3
These devices provide an efficient way of implementing logic functions. They are
simply an X and Y matrix of wires and are programmed to make connections between
X and Y intersections. It is in two parts AND and OR. The device is programmed and
the dots indicate the burned in connections. In the AND array the dots show
horizontal connection, and the AND function. In the OR array the dots show vertical
connection and the OR function. You can now verify that the function performed by
the above is:
F1 = ABC + BC
F2 = ABC +BC +ABC
F3 = ABC +ABC +BC
Note that this is referred to as a 3*4*3 array as it has 3 lines in, 4 implication lines
and 3 outputs
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Programmable arrays of logic (PALS)
In many ways similar to PLA’s they were introduced as are replacement to TTL
discrete circuits. The PAL has a programmable AND array but a fixed OR array. The
basic structure is shown below. The function shown is:
F1 = AB + AB
F2 = BC +BC
F1
OR gates
F2
A
A
B
B
C
C
Each PAL output is the OR of two product lines
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A 3*4*2 PAL