Download A 125 MHz Burst-Mode Flexible Read While Write 256Mbit 2b/c 1.8V

Review Of
“A 125 MHz Burst-Mode Flexible Read While
Write 256Mbit 2b/c 1.8V NOR Flash Memory”
Adopted From:
“ISSCC 2005 / SESSION 2 / NON-VOLATILE
MEMORY / 2.5
by: C. Villa et al”
Class presentation of Advanced VLSI course
by
Ashkan Jalili
Instructor: Dr. Fakhraie
1
outline
 Floating Gates
 Conventional sense amplifiers
 Proposed sense amplifier
 Programming scheme
 Chip specifications
 Summary
2
FLOATING GATE
Control Gate
Floating Gate
Drain
Tunnel Oxide
N+
Source
N+
Substrate
P-type
 Based on charges stored on
FG and changing Vth
 Desired values:
value = 1 : no charges on FG
value = 0 : specific charge on FG
 Applying a specific gate
voltage:
I>0:
I=0:
cell value = 1
cell value = 0
3
MULTILEVEL CHARGING
 Different levels of charging on the FG
 Considering the amount of cell current rather than
just sensing it’s presence or absence
 Different Vth for a 2bit/cell resulting in 4 levels of
current showing 4 states i.e 2bits:
Icell < Iref3
➱ 2bits value = 00
Icell < Iref2
➱ 2bits value = 01
Icell < Iref1
➱ 2bits value = 10
Icell > Iref1
➱ 2bits value = 11
4
Conventional Sense Amplifiers
Structure of a conventional sense amplifier[3]
5
Disadvantage of Conventional amplifiers
 A constant high voltage is applied to all cells (higher than
the largest Vth) resulting in wide range of current:
 The circuit should have the ability to work in wide range of current from
a few uA to several tens of uA
 The current in cells with lower Vth is large:
 Large current increases the effect of parasitic resistance
 Lager current increases power dissipation
6
Sense amplifier scheme
Precharger - I/V converter
Vref
+
Comparator
+
-
-
Reference sense out
Word line


Latches
Bit line
Iref
R0
MSB
LSB
Iref < 10µA
SA switched off as Icell > Iref
Proposed sense amplifier scheme[1]
7
Read scheme of proposed structure
Latch
SA
Decode
Iref
Out<1:0>
Array Wordline
SA
SA
Ref 2
Ref 3
Ramp
gen
SA
Ref 1
Iref
Ref sense out<1:3>
Reference Wordline
Structure of reading concept[1]
8
Design solution: voltage ramp read
Vgate
Iref
•SA
trigger
11
10
Word line
ramp
Reference triggers
000
00
WL reset by
ref3 trigger
array
cell
Icell
Vtref1
01
Vtref2 Vtref3
001
011
time
111
Array cell trigger
Sense output
01
Read ramp, reference and array sense output[1]
9
Conventional programming Scheme
Conventional programming:
Applied constant Vg [4]
 Constant Vg is applied to all
cell gates
 Amount of desired charge is
tuned by the pulse width
 Disadvantage:
 The threshold voltage distribution
of programmed cells can be
several volts (not suitable for low
voltage operations)
10
Programming scheme
A sample threshold voltage distribution diagram [2]
11
Improved programming scheme
Introduced in 1995
 Easier to control Vth distribution
width
 Higher programming speed
can be obtained
 Easier to generate on chip
a) Trapezoidal, b) and staircase,
programming pulses [4]
 Vth will increase with every step
 Changes depend on the amount of
step
12
Programming scheme
Threshold voltage changes for different voltage steps [2]
13
Programming scheme



Staircase voltage is applied to achieve narrow
distribution width
The gate voltage in programming phase is varied from
1V to 9v with a step size of 75mV
3 phase is used for programming:
1.
2.
3.
Content of memory is read and compared to the content of write
buffer
Programs “10” and “01” cells executing a program/verify loop
Programs “00” cells applying a voltage ramp starting from the last
used voltage level in phase 2, no verify is done
14
256 Mbit flash - Die photo [1]
16Mbit
Bank
Sense
amps
 16 banks of
64Mb
 16 sectors / bank
 64Kw / sector
Ctrl logic
Charge Pumps
Output
Input
Ctrl logic
 Independent
64+3 sense
amplifiers per
bank
 Die size 55mm2
in 130nm
Die photo [1]
15
Access time measurement [1]
Address
input
65 ns
Data output
Fastest slope conf
(~250mV / ns)
Ref 3
sense out
Word line
ramp
Access time measurement [1]
10 ns/div
16
Key feature table [1]
Specifications of the chip [1]
17
Summary
 A new structure for sense amplifiers was proposed in
order to remove the undesired effects of high currents
due to high constant voltage applied to transistors in
conventional sense amplifiers
18
References
1.
2.
3.
4.
C. Villa et al., “A 125 MHz Burst-mode Flexible Read-While-Write
256 Mbit 2b/c 1.8V NOR flash memory,” ISSCC 2005
Tae-Sung Jung et al., “A 117-mm2 3.3-V Only 128-Mb Multilevel
NAND Flash Memory for Mass Storage Applications,” JSSCC 1996
G. Campardo et al., “40-mm2 3V Only 50-MHz 64-Mb 2b/c NOR
Flash Memory’” JSSCC 2000
G.J. Hemink et al., “Fast Accurate Programming Method for MultiLevel NAND EEPROMs,” Symposium on VLSI Technology Digest of
Technical papers 1995
19
Thank you
Any question?