Download TLV8x3 3-Pin Voltage Supervisors with Active

TLV803
SBVS157 – APRIL 2011
www.ti.com
3-Pin Voltage Supervisors
with Active-Low, Open-Drain Reset
FEATURES
DESCRIPTION
•
•
•
The TLV803 family of supervisory circuits provides
circuit initialization and timing supervision, primarily
for DSPs and processor-based systems.
1
2
•
•
•
•
3-Pin SOT23 Package
Supply Current: 9 µA (Typical)
Precision Supply Voltage Monitor:
2.5 V, 3 V, 3.3 V, 5 V
Power-On Reset Generator with
Fixed Delay Time of 200 ms
Pin-for-Pin Compatible with MAX803
Temperature Range: –40°C to +125°C
Open-Drain, RESET Output
APPLICATIONS
•
•
•
•
•
•
•
•
DSPs, Microcontrollers, and Microprocessors
Wireless Communication Systems
Portable/Battery-Powered Equipment
Programmable Controls
Intelligent Instruments
Industrial Equipment
Notebook and Desktop Computers
Automotive Systems
During power-on, RESET is asserted when the
supply voltage (VDD) becomes higher than 1.1 V.
Thereafter, the supervisory circuit monitors VDD and
keeps RESET active as long as VDD remains below
the threshold voltage VIT. An internal timer delays the
return of the output to the inactive state (high) to
ensure proper system reset. The delay time (td(typ) =
200 ms) starts after VDD has risen above the
threshold voltage, VIT. When the supply voltage drops
below the VIT threshold voltage, the output becomes
active (low) again. No external components are
required. All the devices in this family have a fixed
sense-threshold voltage (VIT) set by an internal
voltage divider.
The product spectrum is designed for supply voltages
of 2.5 V, 3 V, 3.3 V, and 5 V. The circuits are
available in a 3-pin SOT-23 package. The TLV803
devices are characterized for operation over a
temperature range of –40°C to +125°C.
DEVICE COMPARISON TABLE
DEVICE
FUNCTION
TLV803
Open-Drain, RESET Output
TLV809
Push-Pull, RESET Output
TLV810
Push-Pull, RESET Output
TYPICAL APPLICATION
3.3-V LDO
3.3 V
5V
OUT
IN
GND
VDD
TLV803
VDD
DBZ Package
(Top View)
GND
DSP/FPGA/ASIC
TLV803S
1
RESET
RESET
GND
3
RESET
VDD
GND
2
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2011, Texas Instruments Incorporated
PRODUCT PREVIEW
Check for Samples: TLV803
TLV803
SBVS157 – APRIL 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
THRESHOLD
VOLTAGE
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
OPERATING
TEMPERATURE
PACKAGE
MARKING
TLV803Z
2.25 V
SOT23-3
DBZ
–40°C TO +125°C
VORQ
TLV803R
TLV803S
TLV803M
(1)
2.64 V
2.93 V
4.38 V
SOT23-3
SOT23-3
SOT23-3
–40°C TO +125°C
DBZ
–40°C TO +125°C
DBZ
–40°C TO +125°C
DBZ
VOSQ
VOTQ
VOUQ
ORDERING
INFORMATION
TRANSPORT MEDIA,
QUANTITY
TLV803ZDBZR
Tape and Reel, 3000
TLV803ZDBZT
Tape and Reel, 250
TLV803RDBZR
Tape and Reel, 3000
TLV803RDBZT
Tape and Reel, 250
TLV803SDBZR
Tape and Reel, 3000
TLV803SDBZT
Tape and Reel, 250
TLV803MDBZR
Tape and Reel, 3000
TLV803MDBZT
Tape and Reel, 250
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or visit the
device product folder at www.ti.com.
PRODUCT PREVIEW
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted) .
VALUE
MIN
Voltage
VDD
MAX
(2)
7
All other pins (2)
–0.3
Maximum low output current, IOL
Temperature
(2)
V
5
mA
–5
mA
±20
mA
Output clamp current, IOK (VO < 0 or VO > VDD)
±20
mA
Operating free-air temperature range, TA
–40
+125
°C
Storage temperature range, Tstg
–65
+150
°C
+260
°C
Soldering temperature
(1)
V
7
Input clamp current, IIK (VI < 0 or VI > VDD)
Maximum high output current, IOH
Current
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND. For reliable operation the device should not be operated at 7 V for more than t = 1000h
continuously
THERMAL INFORMATION
TLV803
THERMAL METRIC
(1)
DBZ
UNITS
3 PINS
θJA
Junction-to-ambient thermal resistance
286.9
θJCtop
Junction-to-case (top) thermal resistance
105.6
θJB
Junction-to-board thermal resistance
124.4
ψJT
Junction-to-top characterization parameter
25.8
ψJB
Junction-to-board characterization parameter
107.9
θJCbot
Junction-to-case (bottom) thermal resistance
—
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TLV803
TLV803
SBVS157 – APRIL 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
At specified temperature range (unless otherwise noted).
MIN
MAX
UNIT
VDD
Supply voltage
1.1
6
V
TA
Operating free-air temperature range
–40
+125
°C
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted).
VOL
TEST CONDITIONS
Low-level output voltage
Power-up reset voltage (1)
MIN
Negative-going input
threshold voltage (2)
0.2
VDD = 3.3 V, IOH = 2 mA
0.4
VDD = 6 V, IOH = 4 mA
0.4
IOL = 50 µA, VOL < 0.2 V
TLV803R
TLV803M
Vhys
Hysteresis
Supply current
IOH
Output leakage current
(1)
(2)
V
V
2.20
2.25
2.30
2.58
2.64
2.70
2.87
2.93
2.99
4.28
4.38
4.48
TLV803Z
30
TLV803R
35
TLV803S
40
TLV803M
IDD
UNIT
1.1
TA = – 40°C to 125°C
TLV803S
MAX
VDD = 2 V to 6 V, IOH = 500 µA
TLV803Z
VIT–
TYP
V
PRODUCT PREVIEW
PARAMETER
mV
60
VDD = 2 V, output unconnected
9
12
VDD = 6 V, output unconnected
20
25
VDD = 6 V
µA
100
nA
The lowest supply voltage at which RESET becomes active. tr, VDD ≤ 66.7 V/ms.
To ensure best stability of the threshold voltage, a bypass capacitor ( 0.1-µF ceramic) should be placed near the supply terminals.
SWITCHING CHARACTERISTICS
At RL = 1 MΩ, CL = 50 pF, TA = +25°C.
PARAMETER
TEST CONDITIONS
tw
Pulse width at VDD
VDD = VIT– + 0.2 V, VDD = VIT– – 0.2 V
td
Delay time
VDD ≥ VIT– + 0.2 V; see Timing Diagram
MIN
TYP
MAX
120
200
UNIT
µs
1
280
ms
TIMING DIAGRAM
VDD
V(NOM)
VIT
1.1 V
t
RESET
1
0
t
td
td
For VDD < 1.1 V Undefined
Behavior of RESET Output
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TLV803
3
TLV803
SBVS157 – APRIL 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
TLV803
R1
_
VDD
+
R2
Reset
Logic
+
Timer
RESET
GND
Oscillator
Reference
Voltage
of 1.137 V
PRODUCT PREVIEW
4
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Product Folder Link(s): TLV803
TLV803
SBVS157 – APRIL 2011
www.ti.com
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
2.75
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
20
VDD = 2.5 V
2.50
2.00
ICC - Supply Current - mA
VOL − Low-Level Output Voltage − V
+85°C
2.25
TA = 25°C
1.75
1.50
TA = 85°C
1.25
TA = 0°C
1.00
0.75
TA =−40°C
0.50
15
+25°C
10
0°C
5
+40°C
0.25
0
2.5
5.0
7.5
10.0
0
12.5
1
2
3
4
VCC - Supply Voltage - V
5
Figure 1.
Figure 2.
NORMALIZED INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE AT VDD
MINIMUM PULSE DURATION AT VDD
vs
VDD THRESHOLD OVERDRIVE VOLTAGE
VDD = 2.3 V
1.000
0.999
0.998
0.997
0.996
0.995
−40
6
3.5
1.001
t w − Minimum Pulse Duration at V DD − µ s
Normalized Threshold Voltage
V IT (T A ), V IT (25 ° C)
IOL − Low-Level Output Current − mA
PRODUCT PREVIEW
0.00
0.0
−20
0
20
40
60
85
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
TA − Free-Air Temperature − °C
Figure 3.
0.2
0.4
0.6
0.8
1.0
VDD − Threshold Overdrive Voltage − V
Figure 4.
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5
TLV803
SBVS157 – APRIL 2011
www.ti.com
APPLICATION INFORMATION
VDD TRANSIENT REJECTION
The TLV803 has built-in rejection of fast transients on the VDD pin. The rejection of transients depends on both
the duration and the amplitude of the transient. The amplitude of the transient is measured from the bottom of the
transient to the negative threshold voltage of the TLV803, as shown in Figure 5.
VDD
VITTransient
Amplitude
Duration
Figure 5. Voltage Transient Measurement
The TLV803 does not respond to transients that are fast duration/low amplitude or long duration/small amplitude.
Figure 4 shows the relationship between the transient amplitude and duration needed to trigger a reset. Any
combination of duration and amplitude above the curve generates a reset signal.
PRODUCT PREVIEW
RESET DURING POWER UP/DOWN
The TLV803 output is valid when VDD is greater than 1.1 V. When VDD is less than 1.1 V, the output transistor
turns off and becomes high impedance. The voltage on the RESET pin rises to the voltage level connected to the
pull-up resistor. Figure 6 shows a typical waveform for power-up, assuming the RESET pin has a pull-up resistor
connected to the VDD pin.
VIT- + VHYS
VDD
1.1V
tD
RESET
Valid Output
Figure 6. Power-Up Response
6
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Product Folder Link(s): TLV803
TLV803
SBVS157 – APRIL 2011
www.ti.com
If a valid output is needed below 1.1 V, then a pull-down resistor can be added to the output in addition to a
pull-up resistor. Figure 7 shows the addition of a pull-down resistor to provide a valid output down to 0 V. The
pull-up and pull-down resistors must be selected to provide valid logic-high levels to the load.
3.3V
0.1mF
VDD
10kW
Microprocessor
TLV803
RST
RESET
GND
100kW
Figure 7. Resistor Added For Valid Low-Voltage Output
Because the TLV803 has an open-drain output, multiple TLV803 outputs can be directly tied together to form a
logical OR-ing function for the RESET line. Only one pull-up resistor is required for this configuration. Figure 8
shows two TLV803s connected together to provide monitoring of a 3.3 V power rail and a 5.0 V power rail. A
reset is generated if either power rail falls below the threshold voltage of its corresponding TLV803.
5.0V
3.3V
0.1mF
VDD
TLV803M
RESET
VIO
100kW
VCORE
Microprocessor
RST
GND
3.3V
0.1mF
VDD
TLV803S
RESET
GND
Figure 8. Multiple Voltage Rail Monitoring
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Product Folder Link(s): TLV803
7
PRODUCT PREVIEW
MONITORING MULTIPLE SUPPLIES
TLV803
SBVS157 – APRIL 2011
www.ti.com
BIDIRECTIONAL RESET PINS
Some microcontrollers have bidirectional reset pins that act as both inputs and outputs. In a situation where the
TLV803 is pulling the RESET line low while the microcontroller is trying the force the RESET line high, a series
resistor should be placed between the output of the TLV803 and the RESET pin of the microcontroller to protect
against excessive current flow. Figure 9 shows the connection of the TLV803 to a microcontroller using a series
resistor to drive a bidirectional RESET line.
3.3V
VCC
VDD
TLV803S
Microprocessor
100kW
RESET
47kW
RST
GND
Figure 9. Connection to Bidirectional Reset Pin
PRODUCT PREVIEW
OUTPUT LEVEL SHIFTING
The RESET output of the TLV803 can be pulled to a maximum voltage of 6 V and can be pulled higher in voltage
than VDD. It is useful to provide level shifting of the output for cases where the monitored voltage is less than the
useful logic levels of the load. Figure 10 shows the TLV803Z used to monitor a 2.5 V power rail, with a logic
RESET input to a microprocessor that is connected to 5.0V and has 5.0 V logic levels.
2.5V
5.0V
0.1mF
VDD
TLV803Z
RESET
10kW
Microprocessor
RST
GND
Figure 10. Output Voltage Level Shifting
8
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Product Folder Link(s): TLV803
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TLV803MDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VOUQ
TLV803MDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VOUQ
TLV803RDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VOSQ
TLV803RDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VOSQ
TLV803SDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VOTQ
TLV803SDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VOTQ
TLV803ZDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VORQ
TLV803ZDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VORQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jul-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TLV803MDBZR
SOT-23
DBZ
3
3000
179.0
8.4
TLV803MDBZT
SOT-23
DBZ
3
250
179.0
TLV803RDBZR
SOT-23
DBZ
3
3000
179.0
TLV803RDBZT
SOT-23
DBZ
3
250
TLV803SDBZR
SOT-23
DBZ
3
W
Pin1
(mm) Quadrant
3.15
2.95
1.22
4.0
8.0
Q3
8.4
3.15
2.95
1.22
4.0
8.0
Q3
8.4
3.15
2.95
1.22
4.0
8.0
Q3
179.0
8.4
3.15
2.95
1.22
4.0
8.0
Q3
3000
179.0
8.4
3.15
2.95
1.22
4.0
8.0
Q3
TLV803SDBZT
SOT-23
DBZ
3
250
179.0
8.4
3.15
2.95
1.22
4.0
8.0
Q3
TLV803ZDBZR
SOT-23
DBZ
3
3000
179.0
8.4
3.15
2.95
1.22
4.0
8.0
Q3
TLV803ZDBZT
SOT-23
DBZ
3
250
179.0
8.4
3.15
2.95
1.22
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jul-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV803MDBZR
SOT-23
DBZ
3
3000
203.0
203.0
35.0
TLV803MDBZT
SOT-23
DBZ
3
250
203.0
203.0
35.0
TLV803RDBZR
SOT-23
DBZ
3
3000
203.0
203.0
35.0
TLV803RDBZT
SOT-23
DBZ
3
250
203.0
203.0
35.0
TLV803SDBZR
SOT-23
DBZ
3
3000
203.0
203.0
35.0
TLV803SDBZT
SOT-23
DBZ
3
250
203.0
203.0
35.0
TLV803ZDBZR
SOT-23
DBZ
3
3000
203.0
203.0
35.0
TLV803ZDBZT
SOT-23
DBZ
3
250
203.0
203.0
35.0
Pack Materials-Page 2
4203227/C
PACKAGE OUTLINE
DBZ0003A
SOT-23 - 1.12 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
2.64
2.10
1.4
1.2
PIN 1
INDEX AREA
1.12 MAX
B
A
0.1 C
1
0.95
3.04
2.80
1.9
3X
3
0.5
0.3
0.2
2
(0.95)
C A B
0.25
GAGE PLANE
0 -8 TYP
0.10
TYP
0.01
0.20
TYP
0.08
0.6
TYP
0.2
SEATING PLANE
4214838/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
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EXAMPLE BOARD LAYOUT
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
2
(R0.05) TYP
(2.1)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214838/C 04/2017
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
2
(R0.05) TYP
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214838/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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