Download Serial Interconnect Bus

Serial Interconnect Bus
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low cost serial communication between IC devices
used to connect controllers, peripherals, sensors,
EEPROMS over short distances (< 10 feet)
2 or 3 wire “inter IC” or “inside the box” serial bus
few pins, low complexity, low cost, low speed (few Mbps
at fastest)
Many serial bus “standards”
… I2C
… SMB
… SPI
… Microwire
… Maxim 3-wire
… Maxim/Dallas
1-wire
MSSP
= Master Synchronous Serial Port
→ module in PIC processor
→ not an interface
→ operation modes: I2C and SPI
I2C and SMBus
I2C or I2C = Inter Integrated Circuit (Inter IC)
„ 2 wire serial interface (plus ground)
„ Philips Semiconductor, 1980’s for TVs
„ used as a control interface to signal processing devices that have separate
data interfaces, e.g. RF tuners, video decoders/encoders, audio processors
„ speeds:
1.
2.
3.
slow, < 100Kbps, “standard mode”
fast, < 400Kbps, “fast mode”
high speed, 3.4Mbps, I2C v2.0
SMBus = System Management Bus
„ extension of I2C bus
„ from Smart Battery System Implementer’s Forum to link intelligent battery,
charger, and microcontrollers
„ speed: 10kHz to 100 100kHz
PIC can use I2C bus to connect to I2C or SMBus peripherals
I2C Bus Configuration
SDA
+5V
Rp
SCL
Rp
SDA = serial data line
SCL = serial clock line
„ lines pulled high via pull-up resistors;
lines pulled low via open-drain drivers
„ master controls clock frequency and signal
„ master can control signal transfers between two slaves
or can transmit/receive signals to/from slave
I2C Protocol
1.
2.
3.
Master sends start condition (S) and controls the clock signal
Master sends a unique 7 bit (10 bit) slave device address
Master sends read/write bit (R/W)
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4.
5.
6.
7.
8.
0 - slave receive
1 - slave transmit
Receiver sends acknowledge bit (ACK)
Transmitter (slave or master) transmits 1 byte of data
Receiver issues an ACK bit for the byte received
Repeat 5 and 6 if more bytes need to be transmitted.
If master transmitting,
master issues stop condition (P) after last byte of data
else master receiving,
last byte is not acknowledged
master issues stop condition (P)
I2C Signals
SDA
SCL
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Start =
Stop =
Data =
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ACK =
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SDA
+ SCL
SDA
+ SCL
value when SCL high;
transition when SCL low
receiver pulls SDA low;
transmitter lets it float
I2C Transmit and Receive
I2C: ACK, NACK, No ACK
Get ACK from slave:
1.
master pulls SCL low
to complete the transmission of the bit
2.
slave pulls SDA low
3.
master issues a clock pulse on the SCL line
4.
slave releases the SDA line
when clock pulse complete
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In case of data being written to a slave, the ACK must be
completed before a stop condition can be generated. The slave
will be blocking the bus (SDA kept low by slave) until the master
has generated a clock pulse on the SCL line.
I2C: ACK, NACK, No ACK
Give ACK to slave:
1.
Master transmits last bit
2.
Slave will release the SDA line:
line will go high (exaggerated)
3.
Master will pull the SDA line low
4.
Master will put a clock pulse on the SCL line
5.
Master will release the SDA line (exaggerated)
6.
Slave will now regain control of the SDA line
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An Acknowledge of a byte received from a slave is
always necessary, except on the last byte received.
I2C: ACK, NACK, No ACK
No acknowledge - after a master has written a byte to a slave
„ If, after transmission of the 8th bit from the master to the slave, the slave
does not pull the SDA line low, then this is considered a No ACK condition.
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The slave is not there (in case of an address)
The slave missed a pulse and got out of sync with the SCL line of the master.
The bus is "stuck". One of the lines could be held low permanently.
Master should abort by attempting to send a stop condition on the bus.
Not acknowledge (NACK) - after a master has read a byte from a slave
„ If the master wants to stop receiving data from the slave, it must be able to
send a stop condition.
„ Since the slave regains control of the SDA line after the ACK cycle issued
by the master, this could lead to problems.
„ Let's assume the next bit ready to be sent to the master is a 0. The SDA line
would be pulled low by the slave immediately after the master takes the
SCL line low. The master now attempts to generate a Stop condition on the
bus. It releases the SCL line first and then tries to release the SDA line which is held low by the slave. Conclusion: No Stop condition has been
generated on the bus.
I2C on PIC
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SSPADD
if slave = device address;
if master, SSPADD<6:0> = baud
rate generator reload value
Fosc/4 = SSPADD +1
FI2C
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SSPSR – shift register
SSPBUF – buffer register
SSPCON1 – control register
SSPCON2– control register
SSPSTAT – status register
SSPIF, PIR1 =
1 – operation complete
1 – operation not complete,
clear before operation initiated
I2C on PIC
to initialize:
„ must initialize SSPADD
„ must initialize SSPSTAT <7:6>
„ must initialize SSPCON1 <5,3:0>
NOTES:
„ selecting master mode on SSPCON1 with SPEN=ON forces SCL
and SDA to open drain IFF TRIS=INPUT for these pins
„ SPEN must be issued after the TRIS is configured
„ if the pins are open drain, you do not have to keep changing the
TRIS direction and reenabling the pins (a good thing)
„ system must have pull up resistors on SCL and SDA for the open
drain to work correctly
I2C …typical read/write sequences
typical write sequence:
→ Start [S]
→ slave address
→ write
Ack ←
→ internal slave address n
Ack ←
→ data to be written to n
Ack ←
→ data to be written to n+1
Ack ←
→ Stop [P]
typical read sequence:
→ Start [S]
→ slave address
→ write
Ack
←
→ internal slave addr i
Ack
←
→ Start [S]
→ slave address
→ read
Ack
←
data@ i ←
→ Ack
data@ i+1 ←
→ NoAck
→ Stop [P]
I2C on PIC … a typical transmit sequence
1.
2.
The user generates a START condition by setting the START enable bit,
SEN (SSPCON2<0>). Wait until complete, i.e. SEN is clear.
SSPIF is set. The MSSP module will wait the required start time before any
other operation takes place.
I2C Master mode does not allow queuing of events.
e.g. the user is not allowed to initiate a START condition and immediately write
the SSPBUF register to initiate transmission before the START condition is
complete.
„ In this case, the SSPBUF will not be written to and the WCOL bit will be set,
indicating that a write to the SSPBUF did not occur.
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3.
4.
5.
6.
The user loads the SSPBUF with the slave address to transmit.
Address is shifted out the SDA pin until all 8 bits are transmitted.
BF on SSPBUF is set when operation complete.
The MSSP module shifts in the ACK bit from the slave device and writes its
value into the SSPCON2 register (SSPCON2<6>).
The MSSP module generates an interrupt at the end of the ninth clock cycle
by setting the SSPIF bit. Check for ACK; if no ACK then timeout.
I2C on PIC … a typical transmit sequence
7.
8.
9.
10.
The user loads the SSPBUF with eight bits of data.
Data is shifted out the SDA pin until all 8 bits are transmitted.
BF on SSPBUF is set when operation complete.
The MSSP module shifts in the ACK bit from the slave device and
writes its value into the SSPCON2 register (SSPCON2<6>).
The MSSP module generates an interrupt at the end of the ninth
clock cycle by setting the SSPIF bit. Check for ACK; if no ACK then
timeout
12.
The user generates a STOP condition by setting the STOP enable
bit PEN (SSPCON2<2>). Wait until complete, i.e. PEN is clear.
Interrupt is generated once the STOP condition is complete.
13.
If appropriate, go into master mode idle.
11.
I2C on PIC
Once Master mode is enabled, the user has six options.
[from data sheet]
1.
2.
3.
4.
5.
6.
Assert a START condition on SDA and SCL.
Assert a Repeated START condition on SDA and SCL.
Write to the SSPBUF register initiating transmission of
data/address.
Configure the I2C port to receive data.
Generate an Acknowledge condition at the end of a
received byte of data.
Generate a STOP condition on SDA and SCL.
Reading:
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Text: Chapter 11 - Interintegrated Circuit Interface
PIC18FXX2 Data Sheet [pdf, 332pp; ©2006 Microchip Technology Inc.]
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Section 15.4 I2C Mode
Philips Semiconductors I²C-bus Information [©2004-2005 Koninklijke Philips
Electronics N.V.]
I2C (Inter-Integrated Circuit) Bus Technical Overview and Frequently Asked
Questions (FAQ) [ESAcademy, 2000]
The I2C-bus specification, Version 2.1, January 2000 [Philips
Semiconductor]
Application Notes [Microchip Technology Inc.] :
„ AN989 Using the MSSP Module to Interface I2C™ Serial EEPROMs with
PIC18 Devices [source code]
„ AN554 Software Implementation of I2C Bus Master [source code]
„ AN735 Using the PICmicro MSSP Module for I2C Communications [source
code]