Download An inductorless wideband LNA with a new noise cancelling technique

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An inductorless wideband LNA with a new noise cancelling
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technique
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Pouria Pazhouhesh MOGHADAM1 and Adib ABRISHAMIFAR2
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Department of Electrical Engineering
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Iran University of Science and Technology
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Narmak, Tehran, 16844, Iran
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[email protected]
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[email protected]
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Abstract
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An inductorless wideband low-noise amplifier (LNA) employing a new noise
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cancelling technique for multi-standard applications is presented. The main
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amplifier has a cascode common gate structure which provides good input
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impedance matching and isolation. The proposed noise cancelling technique not
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only improves the noise figure and power gain but also embeds gm-boosting
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technique in itself which reduces the power consumption of the main amplifier.
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Using current-steering and current-reuse techniques in the noise cancelling branch
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makes the design realizable and low power. The proposed LNA is simulated and
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optimized in 0.13 μm CMOS technology. The LNA achieves the noise figure of
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2.8-3.4 dB, power gain of 19.2 dB and input impedance matching better than -10.5
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dB over bandwidth of 0.04-4.6 GHz. It consumes only 8.5 mW from 1.2 V supply
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voltage which makes it a low power LNA.
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Keywords: Current reuse technique; Gm-boosting technique; Low power LNA;
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Noise cancelling technique.
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1.
Introduction
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Fast growth of wireless technology has led to appearance of various new communication
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standards which accommodate different applications at distinctive frequency bands such as
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terrestrial digital (450-850 MHz) video broadcasting, satellite communications (950-2150
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MHz), global positioning systems (GPS) at 1.2 GHz and 1.575 GHz, and cellular radios
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(850-1900 MHz) [1-2]. Accordingly, Software Defined Radio (SDR) and multi-band/multi-
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standard radio receivers are considered as future radios. One of the main blocks of these
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receivers is LNA at the front-end which has to provide high gain while introducing the least
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noise. One approach to implement multiband receivers is to utilize multiple narrowband
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front-ends which is in contrast to single wideband front-end, the alternative approach, in
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terms of area, power and cost. Besides this, single ended input LNAs are preferred to save
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I/O pins and because antennas and RF filters usually produce single ended signals [3].
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Among different topologies for realization of wideband LNAs, the ones with noise
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cancelling technique are very popular as the trade-off between noise figure and input
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impedance matching is alleviated [4-6]. The main structures proposed for this, are shunt
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resistive feedback and common gate LNAs. In the former, the resistive feedback reduces
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the input impedance providing input matching while in the latter, the wideband
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transconductance of the common gate amplifier is used for input matching.
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The main idea of the noise cancelling technique is to use two nodes with in-phase signal
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voltages and out of phase noise voltages or vice versa and add them at the output by the use
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of auxiliary amplifier(s) in a way that noise is cancelled but signal amplified. Whereas the
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shunt resistive feedback and CG LNAs are not the only implementations of the noise
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cancelling technique, a new noise cancelling technique based on the cascode common gate
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structure is proposed. The proposed LNA achieves a low noise figure, high gain and low
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power consumption while other parameters are kept within acceptable range.
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The paper is organized as follows: in section 2, the proposed wideband LNA is
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presented. Explaining the new noise cancelling technique, the detailed analysis of gain,
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input impedance and noise figure is addressed. In section 3, the designed LNA and
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simulation results are presented. Finally, conclusions are drawn in section 4.
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2.
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2.1. The proposed noise cancelling technique
The Proposed LNA
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Figure 1(a) shows a conventional cascode common gate LNA. The gain transistor, M1,
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develops the LNA’s gain while the cascode transistor, M2, improves its output impedance,
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bandwidth, and particularly its isolation. M1’s dominant noise contributor, its channel
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thermal noise, is modeled by a noise current source connected between its drain and source
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nodes. Investigating the signal and noise voltage polarities on the source and drain nodes of
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M1, it is observed that the signal voltages are in-phase while the noise ones shows 180º
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phase shift. So, if the amplified source voltage of M1 is turned back to the M2’s gate with
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180º phase shift, M2’s gate-source experiences a cancelled noise voltage but amplified
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signal one which is the main idea of the proposed LNA shown in Figure 1(b).
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Consequently, the M1’s noise is cancelled at the output.
Considering the LNA shown in Figure 1(b), the noise cancelling condition is found to
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be:
v s 1,n . Av  v d 1,n
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(1)
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where vs1,n and vd1,n are M1’s source and drain voltages, respectively. Because of the
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negative feedback loop, increasing gain Av causes vs1,n to decrease but vd1,n to increase.
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Then, for complete noise cancelling, the gain Av have to be chosen very high that is not
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practical. However, a moderate value of Av still leads to significant noise cancellation.
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2.2. Gain
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Implementing the gain stage -Av by a common source structure, as shown in Figure 2(a),
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the voltage gain of the LNA, Gv, at frequencies well below fT is obtained by considering its
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small signal equivalent circuit shown in Figure 2(b):
Gv 
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
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g m 3 . 1  g m 1.ro 1  g m 2 .R1 
v out

 RL
vs
1  g m 3 .  ro 1  R s . 1  g m 1.ro 1  g m 2 .R1  
(2)
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 RL
ro 1 1  g m 1.ro 1  g m 2 .R1   R s
It is observed that increasing gm2.R1 improves Gv.
Replacing the input source with Norton equivalent, the input impedance is calculated as
follows:
Z in 
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
g m1  g m 2 .  R 1 ro1   1 ro1 g m1  g m2 .  R 1 ro1 
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(3)
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Where it is assumed that ro1 >> 1. Appearance of gm2 in the denominator of Zin, denotes that
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the proposed LNA embeds gm-boosting technique in itself contributing to its low power
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design.
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2.3. Noise analysis
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The noise equivalent circuit of the LNA is shown in Figure 3. Considering the channel
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thermal noise of the M1 as its dominant noise contributor and using finger digitized gate
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structure, the noise figure of the LNA is found to be approximately:
F  1  FM 1  FM 2  FR 2  FR L  1  (
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(
R1

)2 .

1  g m 1.ro 1  g m 2 .R1 R s .R L
ro 1
 .g m 1
R1
 .g m 2
)2 .
(
)2 .
1  g m 1.ro 1  g m 2 .R1
Rs
1  g m 1.ro 1  g m 2 .R1
Rs

1  g m 3 .  ro 1  R s .1  g m 1.ro 1  g m 2 .R1 
g
2
m3
.R L .R s . 1  g m 1.ro 1  g m 2 .R1 

2
(4)
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It is observed that the appearance of gm2.R1 term in the denominator of FM1 reduces M1’s
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noise contribution at the output. Although further increase of gm2.R1 reduces FM1 more but
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M2’s noise contribution increases as FM2 term shows. Then, there is a tradeoff between FM1
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and FM2 which can be removed by proper selection of R1 and increasing gm2 but this leads
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to more power consumption of the LNA. In addition, increasing gm1 can also contribute to
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further reduction of FM1 and FM2. Even though increasing gm1 and gm2 improves the circuit
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noise performance, according to (3), the input impedance is degraded and, consequently,
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gm1 and gm2 cannot be increased arbitrarily.
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In order to gain insight into circuit design and proper selection of different parameters, it
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is helpful to draw the contour curves of S11 and NF (NF = 10log (F)) in respect with gm2
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and R1 and address the effect of gm1 variation on them. Furthermore, these plots help to
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better understand the interaction between S11 and NF.
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In Figure 4 the contour curves of S11 and NF for two values of gm1 (gm1 = 5 mA/V and
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gm1 = 25 mA/V) were plotted. The goal is to address the effect of gm1 increase. As it is
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inferred, the turn-around point of contours move roughly on the line R1 = gm2 towards the
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origin of the coordinate system as gm1 increases. The contour curves of S11 move faster than
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the ones of NF which means gm1 variations affects S11 more than NF. Then, this causes that
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good input impedance matching is obtained for larger value of NF. On the other hand, large
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gm1 is provided by high bias current of transistor M1 which restricts the design to the
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selection of a low value for the load resistor and then, the gain of the circuit degrades.
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Moreover, choosing gm1 very low causes the desired input impedance matching and low NF
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to be obtained for high values of gm2 and R1 that the former increases the power
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consumption and the latter makes the circuit design challenging from the bias point of
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view. Thus, selecting a mean value for gm1 (10 mA/V < gm1 < 15 mA/V) not only facilitates
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the circuit design but also leads to proper circuit performance.
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2.4. Gain Stage (-Av) Design
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Low noise design of the LNA demands large R1 and gm2. High gm2 corresponds to high
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current consumption. Choosing large values for I2 and R1 leads to a large voltage drop on
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R1 and, consequently, the LNA needs a high supply voltage for proper performance.
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Besides this, high current degrades the output resistance of the noise cancelling branch
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transistor and makes it difficult to use a large R1. Using cascode structure along with
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current steering technique can alleviate these problems and makes the use of large R1 and
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lower supply voltage possible. Furthermore, adding current reuse technique to current
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steering one reduces the power consumption of the LNA significantly.
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3.
LNA Design and Simulation
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Figure 5 shows the complete schematic of the proposed LNA. A single Vdd = 1.2 V
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supply voltage and MIM capacitors for ac-coupling were used. A buffer stage was used at
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the output of the LNA for impedance matching.
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The circuit was simulated in TSMC RF CMOS 0.13 μm with ADS. Using RF transistors in
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the circuit implementation, the minimum length of channel (lr = 0.13 μm) and finger width
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of 2 μm is chosen for gate resistance thermal noise reduction and bandwidth enhancement.
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Using genetic algorithm optimization tools in ADS, the LNA was optimized simultaneously
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for the least NF and S11 over the -3 dB bandwidth while keeping other parameters value in
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an acceptable range. As Figure 6 shows, the highest gain of LNA is 19.2 dB in the
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bandwidth of 0.04 – 4.6 GHz and the input impedance matching, S11, is lower than -10 dB
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(Figure 7). If the noise performance of the proposed LNA is compared with the one without
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noise cancelling (Figure 8), the effectiveness of the new noise cancelling technique is
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proved and the noise figure reaches to the minimum of 2.8 dB. Due to the cascode
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structure, the isolation of lower than -50 dB (Figure 7) is observed which will be about 5 to
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10 dB worse but still very high in practice. The simulated value of IIP3 at 1.9 GHz is -13
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dBm as shown in Figure 9 and -8 dBm and -14 dBm at 0.5 GHz and 4.5 GHz, respectively.
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In the table shown, the simulated results are compared with previously reported ones. The
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proposed LNA achieves high gain, very low noise figure over a wide bandwidth while the
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power consumption is just 8.5 mW.
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4.
Conclusion
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Based on the cascode common gate structure, a new noise cancelling technique for
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multi-standard wideband LNA design was presented in this paper. The proposed LNA was
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analyzed in detail which shows significant improvement of noise figure and gain.
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Simulated in 0.13 μm CMOS technology, the LNA achieves the noise figure of 2.8-3.4 dB,
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power gain of 19.2 dB and input impedance matching better than -10.5 dB over bandwidth
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of 0.04-4.6 GHz. The IIP3 at 1.9 GHz is -13 dBm and the LNA consumes only 8.5 mW
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which makes it a low power LNA.
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References
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[1]
exploiting thermal noise canceling. IEEE J Solid-St Circ 2004; 39: 275-282.
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Bruccoleri F, Klumperink EAM, Nauta B. Wide-band CMOS low-noise amplifier
[2]
El-Nozahi M, A. Helmy A, Sánchez-Sinencio E, Entesari K. An inductor-less noise-
13
cancelling broadband low noise amplifier with composite transistor pair in 90 nm
14
CMOS technology. IEEE J Solid-St Circ 2011; 46: 1111-1122.
15
[3]
gain flatness enhancement. IEEE J Solid-St Circ 2010; 45: 502-509.
16
17
Yu YH, Yang YS, Chen YJE. A compact wideband CMOS low noise amplifier with
[4]
Chen WH, Liu G, Zdravko B, Niknejad AM. A highly linear broadband CMOS
18
LNA employing noise and distortion cancellation. IEEE J Solid-St Circ 2008; 43:
19
1164-1176.
20
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[5]
Liao CF, Liu SI. A broadband noise-canceling CMOS LNA for 3.1–10.6-GHz
UWB receivers. IEEE J Solid-St Circ 2007; 42: 329–339.
8
1
[6]
Wang H, Zhang L, Yu Z. A wideband inductorless LNA with local feedback and
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noise cancelling for low-power low-voltage applications. IEEE T Circuits S-I 2010;
3
57: 1993-2005.
4
[7]
Blaakmeer SC, Klumperink EAM, Leenaerts DMW, Nauta B. Wideband balun-
5
LNA with simultaneous output balancing, noise-canceling and distortion-canceling.
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IEEE J Solid-St Circ 2008; 43:1341–1350.
7
[8]
Bruccoleri F, Klumperink EAM, Nauta B. Noise cancelling in wideband CMOS
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LNAs. IEEE 2002 International Solid-State Circuits Conference; 3-7 February
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2002; San Francisco, CA, USA: IEEE. pp. 406-407.
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Figure 1. (a) Conventional cascode common gate LNA (b) The proposed LNA with noise
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cancelling technique
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1
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Figure 2. (a) The proposed LNA (b) Its small signal equivalent circuit
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Figure 3. The proposed LNA’s noise equivalent circuit
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(a)
2
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(b)
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Figure 4. (a) The Contour curves of NF for gm1 = 5 mA/V (b) The Contour
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curves of NF for gm1 = 25 mA/V (ro1 = 1500 Ω, gm3 = 10 mA/V, RS = 50 Ω,
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RL = 550 Ω, γ = 2/3)
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1
(c)
2
3
(d)
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Figure 4. (Continued) (c) The Contour curves of S11 for gm1 = 5 mA/V (d) The
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Contour curves of S11 for gm1 = 25 mA/V (ro1 = 1500 Ω, gm3 = 10 mA/V,
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RS = 50 Ω, RL = 550 Ω, γ = 2/3)
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1
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Figure 5. The complete schematic of the proposed LNA
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Figure 6. Simulated S21 of the proposed LNA with and without applying noise cancelling
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technique.
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Figure 7. Simulated S11, S22 and S12of the proposed LNA with applying noise cancelling
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technique.
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Figure 8. Simulated NF of the proposed LNA with and without applying noise cancelling
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technique.
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Figure 9. Simulated IIP3 at 1.9 GHz.
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Table . Performance Summary
Supply
Technology
-3dB-BW
Gain
NF
S11
IIP3
(CMOS)
(GHz)
(dB)
(dB)
(dB)
(dBm)
Reference
Power
voltage
(mW)
(V)
[2]
90 nm
0.002-2.3
21
1.4
<-10
-1.5
1.8
18
[3]
0.18 μm
0.004-1.2
16.4
2.1-3.4
<-10
0
1.8
14.4
[4]
0.13 μm
0.8-2
14.5
2.6
<-8.5
+16
1.5
17.4
[5]
0.18 μm
1.2-11.9
9.7
4.5-5.1
<-11
-6.2
1.8
20
[6]
0.13 μm
0.2-3.8
19 VG
2.8-3.4
<-9
-4.2
1
5.7
[7]
65 nm
0.2-5.2
13-15.6
<3.5
<-10
>0
1.2
21
15
[8]
0.25 μm
0.002-1.6
13.7 VG
2.4
<-8
0
2.5
35
This work
0.13 μm
0.04-4.6
19.2
2.8-3.4
<-10.5
-13
1.2
8.5
1
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