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Transcript
EE141 Fall 1999 Homework Set #5 Solutions Due 10/13/99 Problem 1) Since NMOS form weak pull-up transistors, we occasionally employ a PMOS transistor to restore the level in a pass transistor logic: Vdd = 2.4V .750/.625 B X In .750/.375 50fF Out Assume that the inverter switches abruptly at V M = 1.2V. Vtn = 0.43V; Vtp = -0.4V; VDSAT,n = 0.63; VDSAT, p = -1V; kn’ = 115x10-6 A/V2; kp’ = -30x10-6 A/V2; = 0; = 0; a) Vin = 0V; and the capacitor is fully charged. B switches from 0V to VDD instantly. Explain what happens at Node X? What is the propagation delay, tp , as seen at X? B turns on NMOS pass transistor. Node X is pulled down. Can assume VOL < 1.2V PMOS is off VOL = 0V Propagation Delay defined as tphl = Delay from Vx = 2.4V to Vx = 1.2V Ids,p (Vx = 2.4V) = 0 Req,p(Vx = 2.4V) = 2.4/0 = undefined !! Need for better aproximation, use Req,p (Vx = 2.4V) = Vx/Ids Since PMOS will operate near cut-off/triode mode threshold, Ids,p (Vx = 2.4V) = -kp’ (.75/.625)((2.4-0.4)(Vdd-Vx) - (Vdd-Vx)2) Ids /Vx = kp’ (.75/.625)((2.4-0.4) - 2(Vdd-Vx)) = kp’ (.75/.625)(2.4-0.4) @ Vx = Vdd Req,p(Vx = 2.4V) = [kp’ (.75/.625)(2.4-0.4)]-1 =13.9k Ids,p (Vx = 1.2V) = -kp’ (.75/.625) ((2.4-0.4) - ½) = 51.8A Req,p,Av = 0.5*( 13k + 1.2/51.8 ) = 18.5k Ids,n (Vx = 2.4V) = kn’ (.75/.375) ((2.4-0.43)0.63 - 0.5*0.632) = 33.7A Ids,n (Vx = 1.2V) = kn’ (.75/.375) ((2.4-0.43)0.63 - 0.5*0.632) = 33.7A Req,n =0.5*(2.4/33.7 + 1.2/33.7 ) = 53k tphl = 0.69 (Req,p // Req,n) 50fF = 0.47ns b) VB = Vdd. A clock of 10MHz is applied at In. What is the power consumption of the above circuit? When In=Vdd Vx is driven up. As it passes beyond 1.2V, PMOS is turned on. As Vx continues to increase beyond Vdd-Vtn , NMOS turns off. Vx is pulled to Vdd. VOH = Vdd . So, 50fF is repeatedly charged to Vdd and discharged to 0. Power consumption = CVdd2f = 50fF x 2.42 x 10M = 2.88W Problem 2) The figure on the following page is an implementation of a Look-Up-Table. A,B,C,and D are non-volatile bit values obtained from a ROM output. a) By making use of a truth table, explain what the above circuit does. The Look-up-table uses S0 and S1 as input index to select between A to D. S0 1 0 0 1 S1 1 1 0 0 Out A B C D b) What is a possible disadvantage of the above circuit? VOH = Vdd - 2Vtn c) All transistors above are minimum size. Write down the ratio for W/L for minimum sized transistors. (W/L)min = 3/2 S0 A S1 B 30mm M1 wire, 3.6m wide Out S0 C S1 D Cdiff, p = Cdiff,n = 2fF / m2 Cmetal = 0.02fF / m2 Ron,n = 22k Ron,p = 60k Rmetal = 0.08 S0 = S1 = 0, and a voltage step S0 d) Find the delay of the circuit for the case when is applied to the active input, using = 0.125m. a distributed RC for the transistor network, and Gate area of transistors = 3*2*0.1252 = 0.937m2 Gate capacitance = 0.937 * 2fF = 0.199fF Transistor network: 22k 22k C 0.199fF 0.199fF Rtotal, metal = 30,000/3.6 * 0.08 = 666 Ctotal,metal = 30,000*3.6*0.02 = 2.16pF I. Lumped RC circuit for the metal wire. 22k 22k 666 C 0.199fF 0.199fF 2.16pF tp = 0.69*{ 22k*0.199f + (22k+22k)*0.199f + (666+22k+22k)*2.16p} = 67s II. model for the metal wire. 22k Rtotal 22k C 0.199fF 0.199fF Ctotal/2 Ctotal/2 tp= 0.69* {22k*0.199f + (22k+22k)*(0.199f + 0.5*2.16p) + (666+22k+22k)*0.5*2.16p} = 66ns III. T model for the metal wire. 22k Rtotal/2 22k Rtotal/2 C 0.199fF 0.199fF Ctotal tp= 0.69* {22k*0.199f + (22k+22k)*0.199f + (22k+22k+0.5*666)*2.16p} = 66ns e) Verify the validity of the above 3 approximations using Spice. SPICE results: (See hw5.cir for SPICE deck, especially for wire model) Lumped 70s 69ns T 69ns HSPICE’s wire model 60ns f) Is there a charge sharing problem? Explain. No charge sharing problem. Output is always connected to one of A,B,C or D. Problem 3) a) What is the logic function implemented by the CMOS transistor network in Figure 1? Label the sizes of NMOS and PMOS devices such that the gate has the same drive as the inverter with Wn = 1m and Wp=2m F = [(A+B)CD]’ = A’B’ + C’ + D’ = (A+B)’ + C’ + D’ b) VDD 4m B D C 2m 2m A 4m Y 3m 3m 3m 3m Figure 1 c) What is the logic function implemented by the pass-transistor network in Figure 2? Signals A, A’, B, B’, C and C’ are the inputs and Y and Y’ are the outputs. Y = A(B’C’+BC) + A’(B’C+BC’) You might notice that this could be part of an adder. Set Cin = A, B = X[0], C = W[0], and you have the sum output Y = X[0] + W[0]. A A B B C C Y Y Figure 2 Problem 4) List all the possible logic functions of inputs A, A’, B and B’ that could be implemented using the pass-transistor function generator from Figure 3, with P1, P2, P3, P4 being the control variables. All 16 possible functions. The Xinlinx FPGA uses this circuit (or its derivative) predominantly to achieve its logic functionality. A B F(A,B) 0 0 P1 0 1 P2 1 0 P3 0 0 P4 By setting P1,P2,P3,P4 (0,1), you can basically obtain all possible functions of A and B, i.e. all 24 possible functions. P3 P1 P2 P4 A A B B F ( A, B ) Figure 3