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Breakdown in the metal/high-k gate stack: Identifying the “weak link”
in the multilayer dielectric
G. Bersuker, D. Heh, C. Young, H. Park, P. Khanal, L. Larcher1, A. Padovani2,
P. Lenahan3, J. Ryan3, B. H. Lee, H. Tseng, R. Jammy
SEMATECH, 2706 Montopolis Dr., Austin, TX 78741, USA; [email protected]
1
DISMI Università di Modena e Reggio Emilia and IU.NET, 42100 Reggio Emilia, Italy
2
Dipartimento di Ingegneria, Università di Ferrara and IU.NET, 44100 Ferrara, Italy
3
Penn State University, University Park, PA 16802
Abstract
We apply a systematic approach to identify a highk/metal gate stack degradation mechanism. Our results
demonstrate that the SiO2 interfacial layer controls the overall
degradation and breakdown of the high-k gate stacks stressed
in inversion. Defects contributing to the gate stack
degradation are associated with the high-k/metal-induced
oxygen vacancies in the interfacial layer.
Introduction
In spite of significant efforts [1-5], major factors
controlling time-dependent dielectric breakdown (TDDB) in
the metal/high-k gate stacks still remain unclear. An
essentially complicating feature of the MIS high-k gate stacks
is that they are multilayer (at least two films: a high-k HK
and interfacial SiO2 layer [IL]) structures, both layers being
modified by the inter-material interaction with each other and
the metal electrode. When one of the layers fails, the applied
voltage drops primarily across the remaining layer,
accelerating its degradation [5]. Therefore, to understand the
mechanism of high-k stack degradation and breakdown (BD),
one need to identify the “weak link”—the layer that degrades
and fails first—in the multilayer stack. In this study, we first
establish which of the electrical characteristics correlates to
gate stack degradation and BD, then identify the dielectric
layer providing the major contribution to stress-dependent
changes of this characteristic, and finally identify the nature
of the defects and mechanism governing stress-induced
degradation of the “weaker” layer.
Devices and measurements
n- and pFETs for this study were fabricated using a
standard gate-first CMOS process including a 1000°C/10sec
source/drain (S/D) activation anneal. The gate stacks were
formed using 3 nm and 4 nm atomic layer deposition (ALD)
HfO2 films and a TiN electrode. For MIM capacitors, which
do not contain IL and therefore serve as a reference for the
MIS stacks, crystallized HfSiO (10% SiO2) or ZrO2 and TiN
were used as the dielectrics and electrode, respectively.
The devices were subjected to constant voltage stress
(CVS) in inversion, as well as substrate hot carrier (SHC)
stress [6], interspersed with pulsed Id-Vg, frequency
dependent charge pumping (CP) and stress-induced leakage
current (SILC) to monitor dielectric degradation.
SILC as the gate stack degradation monitor
In all cases of CVS in inversion, SILC data exhibit a
strong correlation to the evolution of the gate current
degradation features, e.g., soft BD, progressive BD, and hard
BD. See examples in Fig.1 (a detailed discussion on the SILC
correlation to BD is given in [7]). This indicates that the
dielectric layer controlling SILC growth is the major
contributor to the dielectric stack degradation, thus
representing the “weak link” in the high-k gate stack.
SILC origin
Interface trap density (ΔNit) by low frequency CP
(Fig.2a) and SILC growth (Fig.2b) measured during the same
stress sequence demonstrate excellent correlation at all stress
voltages (Fig.3), indicating that both characteristics are
controlled by the same defects. To obtain such a correlation,
only one layer, either the high-k or IL, can contribute to SILC
since they exhibit very different voltage acceleration factors
for defect generation. According to the CP simulation results
[8], under the conditions used, CP performed within the
1MHz-1KHz frequency range probes traps distributed
primarily within IL and IL/high-k interface, Fig.4. Indeed, the
trap density exhibits a monotonous growth within the total
frequency range, as should be expected when the probed traps
are located within the single material. Since the high
frequency CP measurements are known to probe IL, we may
conclude that the low frequency data reflect on the traps
within the IL as well, consistent with simulation results. The
observed increase of the trap density in the IL with closer
proximity to the high-k layer is caused by the high-k-induced
trap and trap-precursor generation in the IL [9].
Therefore, data in Fig.3 suggest that SILC is controlled
by the trap generation in the IL, primarily near its interface
with the high-k. Alternatively, MIM caps (no IL) do not
exhibit an appreciable SILC up to the BD moment at any
stress voltage, Fig.5. In addition, MIS stacks show a
reduction in the activation energy (Ea) extracted from the
SILC temperature dependency during the post-soft BD
stressing (Fig.6), while in MIM, Ea does not change.
Verification of SILC factors
The stress time-dependent trap distributions in Fig.4
were used to simulate SILC (measured during the same
stress/sense sequence as CP) using the model, which
considers a multi-phonon trap-assisted tunneling conduction
mechanism, including random defect generation and barrier
deformation induced by the charged traps [10,11]. The
excellent agreement between the experimental and simulated
Ig-Vg curves in the whole range of stress times, Fig.7,
confirms the above conclusion that SILC is controlled by
defect generation in the IL. The trap energies are determined
to be uniformly distributed within the 2.2-2.6eV range from
the bottom of the SiO2 conduction band in both n- and pFETs (Fig.8), which correctly reproduces the maximum SILC
increase, Fig.9, indicating that defect energy is aligned with
the electron quantized levels in the Si channel. The trap
density in high-k remains constant at ~2·1019 cm3.
Mechanism of IL trap generation
Substrate hot carrier (SHC) stress performed under
different carrier energy conditions results in trap generation
exclusively at the IL/Si interface, Fig.10, with no SILC,
Fig.11, which is consistent with the above conclusion that
SILC is controlled by the bulk IL traps. These data indicate
that bulk IL trap generation due to the possible release of H
from the anode does not occur in the metal gate stacks as
opposed to poly-Si gates [6]. CVS and SHC results suggest
that the IL bulk traps apparently are activated by electron
trapping, which is much less effective with the SHC stress
due to the significant mismatch between the precursor defect
energy and that of the injected high energy electrons in the
SiO2 conduction band. In summary, trap generation is driven
by the capture of electrons by precursor defects in the IL,
most likely oxygen vacancies. Electron energy-loss
spectroscopy (EELS), electron spin resonance (ESR), and Xray photoelectron spectroscopy (XPS) data [9,12] showed
these to be induced by the IL interaction with high-k/metal
films. Ab initio calculations show [13] that the electron
captured by the Si-Si vacancy forms a specific E’ center (a
negative O-vacancy), located within the 2.2-3.5eV range
below the SiO2 conduction band (depending on the specifics
of the local amorphous SiO2 matrix around the defect), that
matches the trap energy range obtained by the simulations in
Fig.8. The calculated g-matrix components of this negative
O-vacancy, g=2.0023 and 2.0027 [13], match well with the
zero crossing g= 2.0026 +/- .0002 observed by ESR in the
signal from IL, Fig.12a. These E’ defects are clearly present
in the as-processed stack, and their density is increased in the
result of the substrate injection stress, which was performed
by applying a corona charge on a blanket film stack used for
the ESR measurements, Fig.12a. The results indicate that
these E’ centers were stress-activated from the precursor Ovacancy defects. One needs to consider that the ESR
measurements could underestimate the total number of
these defects but not overestimate them. This is so because
the measurements are not sensitive to those centers which are
not in a paramagnetic charge state.
No such E’ centers were generated in the SiO2 samples
(Fig.12b) confirming the high-k-induced nature of these IL
traps.
Effect of stress on high-k
The value of the gate current (Ig) activation energy of
0.40eV for the high-k MIM caps, Fig.13, points to the Ovacancies in the high-k [14] as the defects supporting Ig. The
fact that no appreciable SILC was observed and that the Ig
activation energy remains constant during the stress indicates
that no new O-vacancies were generated. This is consistent
with the pulsed Id-Vg data, Fig.14, which do not show any
electron trap generation associated with O-vacancies [15].
From the MIM TDDB data, Fig.15a, the activation energy for
the BD path formation = 0.7eV. The TDDB characteristics of
MIS, Fig.15b, do not match those of MIM as expected for the
IL-controlled BD.
Conclusion
Our results demonstrate that the IL is the major factor
controlling the overall degradation and breakdown of the
metal/high-k gate stacks in inversion. Defects contributing to
gate stack degradation are associated with the metal/high-kinduced oxygen vacancies in the IL. Control over the IL
stoichiometry is critical if dielectric scaling requirements are
to be met.
References
[1] K. Okada et al., Symp.VLSI Tech., p.34, 2007
[2] J. McPherson et al., Appl. Phys. Lett., 82, 2121, 2003.
[3] T. Kauerauf et al., Electron Dev. Lett. 26, 2005
[4] A.Paskaleva et al.,Appl.Phys.Lett., 90, 042105, 2007
[5] N. A.Chowdhury et al., Microel. Eng., 85, 27, 2008
[6] D.J.DiMaria, J. Appl. Phys., 86, 2100, 1999
[7] G. Bersuker et al., Proc. IRPS, p.49, 2007
[8] D. Heh et al., IEEE TED, 54, 1338, 2007
[9] G. Bersuker et al., J. Appl. Phys, 100, 094108, 2006
[10] L. Larcher, IEEE TED, 50, 1246, 2003
[11] A. Padovani et al.,Proc. IRPS, 616, 2008
[12] P. Lysaght et al., J. Appl. Phys., 101, 024105, 2007
[13] P.V.Sushko et al., Microel. Eng., 80, 292, 2005
[14] D. Muñoz Ramo et al., Phys.Rev.B 75, 205336, 2007
[15] G. Bersuker et al., IEEE TDMR, 7, 138, 2007
3
50
Ig [μA]
ΔIg/Ig
Stress
Time
40
10
6
4
ΔIg/Ig
0.0
0.5
1.0
Gate Voltage [V]
Ig [ μA]
8
2
1
2
10
0
10
Ig
2
10
ΔSILC
1
30
10
20
10
10
10
0
3
10
Time [sec]
10
ΔIg/Ig
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
0
-1
-2
1
2
10
10
3
10
10
Time [sec]
Fig. 1 (a) Variation of the gate leakage current and SILC in 3nm HfO2 (a) NMOS and (b) PMOS under constant voltage stress.
2
3
10
1
0
1
Vg = 2.5 V
0
10
-1
0
10
Vg = 2.0 V
Vg = 2.8 V
Vg = 2.3 V
Vg = 3.0 V
1
10
2
10
3
10
Stress time (sec)
ΔIg/Ig
10
10
-1
-2
-3
10
4
0
10
10
10
Vg = 2.0 V
Vg = 2.8 V
Vg = 2.3 V
Vg = 3.0 V
10
1
10
2
10
3
10
Stress time (sec)
-3
-3
19
2.0
1.5
1.0
3.0
t=0s
t = 10 s
t = 100 s
t = 1000 s
pFET
2.5
2.0
1.5
1.0
0.5
0.5
0.0
0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3
X (nm)
0.0
0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3
X (nm)
Vg = 3.0 V
0
1
10
10
ΔNit/Nit0 (%)
10
70
60
50
40
30
20
10
0
14
12
10
8
6
4
2
0
2nm MIS
3nm MIS
8nm MIM
2
10
3
Time [sec]
10
Fig. 5 (a) Examples of the typical SILC in 2 nm
(CVS at Vg=2.7V) and 3 nm (Vg=3.7V) MIS gate
stacks and 8 nm MIM (Vg=3.4V and 3.3V).
1
EA ~ 0.30 eV
3
EA ~ 0.20 eV
2
1
EA ~ 0.09 eV
EA ~ 0.01 eV
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VBIAS (Volt)
Fig. 5 (b) Example of the typical SILC in 8 nm
MIM.
0
26
10
Init
SBD
PBD
HBD
-1
10
2
4
Jg (A/cm )
Vg = 2.5 V
ln(ISILC)
ΔIg/Ig0
Vg = 2.8 V
Vg = 2.3 V
Fig. 3 Correlation of low voltage SILC and lowfrequency Nit stress time dependencies at
various stress voltages (data from Fig. 2).
Fig. 4 Variation of the trap density through the thickness of the interfacial SiO2 layer during
stress at (a) Vg=3V in nFET (data from Fig.2) and (b) Vg=-3V in pFET.
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
Vg = 2.0 V
-1
10
ΔIg/Ig
2.5
3.5
a)
-2
4
10
[2 nm HfO2]
4.0
nFET
Vg = 2.5 V
-2
Vg = 2.5 V
10
NIT (x10 cm )
NIT (x1019 cm-3)
3.0
t=0s
t = 10 s
t = 100 s
t = 1000 s
-1
ΔIg/Ig [3 nm HfO2 and MIM]
3.5
10
10
10
Fig. 2 (a) Stress time dependence of Nit at different stress voltages and (b) Stress time dependence
of low voltage SILC at different stress voltages in 1.1nmSiO2/3nmHfO2/TiN nFET.
4.0
ΔNit: [email protected]
10 SILC: Vg = 0.5 V
0
ΔIg/Ig
ΔNit/Nit0 (%)
2
10
10
2
10 SILC @ V = 0.5 V
g
1
10
10 [email protected] f = 1kHz
-3
10
30
32
34
1/Thermal Voltage [q/kT]
36
Fig. 6. Activation energies from
1.1nmSiO2/3nmHfO2 nFET SILC temperature
dependence before stress, after SBD, progressive
BD, and HBD.
E T = 2.4-2.8eV
σT = 2x10
-5
10
10-7
-9
28
Symbols: experiment
fresh
Lines: simulation
t = 10s
t = 100s
t = 1000s
SiO 2 trap:
10
EOT = 1.245nm
WG AT E = 4.4 eV
ΨO FF SET = 1.6 eV
-14
2
cm
High-k trap:
ET = 1.1-1.6eV
-15
σT = 4x10
2
cm
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Vg (Volt)
Fig. 7(a). Measured (symbols) and simulated
(lines) Ig-Vg curves during
1.1nmSiO2/3nmHfO2/TiN nFET stress
Vg=3V.
1
10
-1
10
1.6eV
50
-3
10
SiO2 trap:
ET = 2.3-2.55eV
-5
10
-14
σT = 1.8x10
-7
10
-9
10
EOT = 1.43nm
WGATE = 4.4 eV
high-k trap:
ET = 1.1-1.55eV
ΨOFFSET = 1.6 eV
σT = 5x10
-15
VG = 0.5V
2
cm
H fO
2
SiO
2
30
10
2
0
cm
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Vg (Volt)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Vg (Volt)
12
10
2
g=2.0025
11
-2
4.8X10 cm
Stressed
1nm SiO2 /3nm HfO2
3464
3466
3468
3470
3472
-4
-1
10
2
5
10
10
2
Qinj,tot [C/cm ]
8
10
10
3474
3466
3468
3470
1.5
2.0
Vg (V)
2.5
3.0
10
-1
3472
0.32
0.28
3474
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VBIAS (Volt)
Fig. 13 Activation energy Ea=0.42 eV extracted
from the Ig–Vg temperature dependency in the
total Vg range in high-k MIM caps.
Ea = 0.702 (eV)
0
)
1
2
10
10
tBD (sec)
10
3
Fig. 14 Pulse Id-Vg curves of
1.1nmSiO2/3nmHfO2/TiN devices measured after Fig. 15 (a) TDDB distributions of the high-k
every 1000s intervals during 3V/104s CVS before MIM caps stressed at different temperatures.
Inset: extracted activation energy Ea=0.7 eV.
and after discharge at Vg =-1V for 30s.
Ea'
Ea = 0.41 (eV)
0.30
1
10
1.5
β = 5.55 (e-A)
0.34
Ln(-Ln(1-F))
Ln (tDB @66% )
Ln(1-Ln(1-F))
Id (mA)
1.0
1.0
Ea' = Ea - βEox
0.36
3
(
0.5
0.38
Fig. 12 ESR signal from the (a) IL of the 1.1nmSiO2/3nmHfO2 stack before and after corona
stress and (b) 1.1nm thermal SiO2 before and after corona stress (only the Pb centers generation
is observed).
1.6
o
125 C 100 75
50
1.4 10
0.6 After discharge
1.2
0.5
10
1.0
0.4
10
0.8
2.5 2.6 2.7 2.8 2.9 3.0 3.1
Stress time
0.3 Stress time
1/T 10-3/K
0.6
0.2
0.4
0.1
0.2
Before discharge
0.0
0.0
β = 0.86 0.86 1.05
1.46
2
0.0
Vg [V]
Fig.11. SILC during HSC stress at high and
low gate biases (B -substrate, I –injector, G
–gate).
Magnetic Field [Gauss]
Magnetic Field [Gauss]
-0.5
0.40
1nm SiO2
3464
-1.0
0.42
g=2.0036
12
-2
1.0X10 cm
Stressed
0.0
-1.0
g=2.0036
11
-2
3.9X10 cm
Unstressed
0.5
-0.5
Fig.10. Trap generation in IL (by CP at different
frequencies) vs. injected charge during HSC stress
under various electron energies and gate bias
conditions (B -substrate, I –injector, G –gate).
Signal Intensity [Arb. Unit]
Unstressed
1.0 G=1V,B=-6V, I=-7V
1MHz
100KHz
10KHz
G=1V,B=-6V,I=-7V
G=1V,B=-4V,I=-5V
G=1V,B=-3V,I=-4V
10
g=2.0025
11
-2
3.9X10 cm
-1.0
10
10
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Vg (Volt)
0.0
-0.5
Vg increase
11
0.5
ΔIG/IG0
pFET
G=2V,B=-6V,I=-7V
Ea (eV)
t = 10 s
t = 100 s
t = 1000 s
G=2V,B=-6V, I=-7V
1.0
ΔIG/IG0
Symbols: experiment
Lines: simulation
Fig. 9 (b) Experimental (symbols) and
simulated (lines) relative change of pFET Ig-Vg
curves (wrt the pre-stress one) during stress.
Signal Intensity [Arb. Unit]
Fig. 9 (a) Experimental (symbols) and
simulated (lines) relative change of nFET IgVg curves (wrt the pre-stress one) during
stress.
1.5
Carrier energy
increase
ΔNit [/cm ]
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
t = 10 s
t = 100 s
t = 1000 s
nFET
40
20
Fig. 8.Band diagram for 1.1nmSiO2/3nmHfO2/TiN
nFET gate stack. Energy distribution of the stressFig. 7(b) Measured (symbols) and simulated
generated defects exhibiting a non-uniformed depth
(lines) Ig-Vg curves during
1.1nmSiO2/4nmHfO2/TiN pFET stress Vg=-3V. profile is shown by a shaded rectangular area.
ΔIg/Ig0
Symbols: experiment
Lines: simulation
60
∼ 2.8eV
2.6eV
ΔIg/Ig0
2
Jg (A/cm )
70
Symbols: experiment
fresh
Lines: simulation
t = 10s
t = 100s
t = 1000s
4
10
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
o
75 C
o
100 C
o
125 C
1
10
β=0.5
2
10
β=0.7
3
tBD (sec)
10
β=0.3
4
10
Fig. 15b. Example of TDDB distributions of
1.1nmSiO2/3nmHfO2/TiN transistors stressed
at different temperatures.