Download Examples of SoC and SiP System-on-Chip

Overview
System-on-Chip
• Ericsson’s Bluetooth radio (2001)
• TI’s quad-band GSM (2007)
Examples of SoC and SiP
• Infineon’s quad-band GSM (2007)
• Intel processors (2007)
Pietro Andreani
Dept. of Electrical and Information Technology
Lund University, Sweden
P. Andreani – System-on-Chip
Ericsson’s CMOS Bluetooth radio (2001)
Examples of SoC and SiP
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Floorplan and photo
Low-IF receiver
Analog part = 4mm2
excluding pads
Direct-conversion transmitter
(with double-freq. LO)
P. Andreani – System-on-Chip
Examples of SoC and SiP
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P. Andreani – System-on-Chip
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Issues
Issues –II
• Cross-coupling at 1) PCB level, 2) bond wires and
package, 3) ground and supply lines, 3) silicon substrate
• Buried N-layer for isolating nMOS from substrate
• Trench contacted to ball grid array (BGA) through 13
bumps Æ 25dB of improved isolation at 2.5GH (product is
flip-chip mounted on a BGA, unlike the one shown here,
which was bonded for testing purposes)
• The large digital cells were simulated via equivalent huge
inverters. Example: the CPU (75k gates, 10MHz, 5mA
from 1.5V) was emulated by an inverter with width 70,000x
the minimum width
• All sensitive analog circuits are differential with low
common-mode to differential-mode conversion
• Foorplan available from start Æ substrate RC network
extracted with dedicated software, impact simulated
• 5 supply domains in the digital section, plus 5 more in the
analog section
• A specially designed P-type trench separates analog from
digital Æ trench width = 300μm (!), area = 1.4mm2 (!!!),
“which will be lowered significantly in future versions”
P. Andreani – System-on-Chip
Examples of SoC and SiP
• Voltage regulators for most analog blocks (LNA, VCO, etc)
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P. Andreani – System-on-Chip
TI’s single-chip quad-band GSM radio (90nm CMOS)
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TI’s single-chip – II
• The cell phone growth is fantastic
– 1.2 billion phones sold in 2007
– unprecedented in the history of electronics
• Digital baseband (DBB) and application processor need to
be in the most advanced CMOS
– e.g. low-voltage nanoscale digital CMOS
• Mature markets are saturated
– Over 100% cell phone saturation in some countries
• e.g., Finland, Taiwan, Hong Kong
– US is 75%
• True “phone-on-a-chip” has not been yet realized
– 2-watt PA
– Battery power management with 20-volt chargers
– RX bandpass SAW filters
• Continued growth from the emerging market
– i.e., India and China
• Single-chip radio that integrates RF with digital baseband is
the most cost-effective solution
– Digitized RF functions can scale with Moore’s Law
• Population in those countries desire cell phones but most
cannot afford $100 phones
– “$20 phones” will gain billions of new subscribers
This and following 6 slides courtesy of B. Staszewski, TI, Dallas
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P. Andreani – System-on-Chip
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Digital RF processor (DRP)
• ARM7 MPU
– Protocol layer stack
– Light application
processor
– MP3/AAC player
– VGA camera I/F
• 2.5Mb SRAM
– Externally extensible
• RF ADPLL can
generate DBB clocks
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Front-end
Module
2-watt PA
T/R
switch
RX SAW
filters
DPA
Digital
logic
Processor clock
DCO
TDC
LO
clock
TX
Dividers
RX
Digital
logic
A/D
Power Management (PM)
Discrete
time CH
iRF
Current
sampler
LNA
+TA
RF in
RF Built-in Self Test (RF-BIST)
Battery Management
P. Andreani – System-on-Chip
Coexistence of RF and Digital
Amplitude modulation
DCXO
FREF
– Modem functions
Dither
Internal D
DRP Processor
• C54x DSP
Xtal
Digital Base
eband Processor
• Transforms RF
functionality into:
– All-digital PLL
– All-digital polar
TX
– Digitallyintensive RX
• 26MHz digitallycontrolled crystal
oscillator (DCXO)
– FREF dither
• DBB clocks
synchronous
with RF clock
SRAM
S
Digital base-band (DBB)
VBAT
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Digital clock coupling to RF
• Digital clock activity is a strong aggressor
• DCO LC tank is the most sensitive victim
• Core RF circuits still experience conventional RF system
issues
– Device parameter spread and mismatch
– Performance variability due to environmental conditions
– Parasitic coupling
• DBB clocks
synchronous
with the RF
clock create
less injection
pulling
• On-die digital processors brings tremendous benefits
– Digital logic and memory are powerful yet inexpensive
– Digital assistance with calibration, compensation,
predistortion , linearization, built-in self-test
Package
IC
LDO
DCO
Clock
MUX
Variable caps
Pre
PA
RF
out
• However, clocking creates noise injection issues
– Millions of digital gates on the same die
EM coupling
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Chip photo
Infineon’s quad-band GSM radio SiP (130nm CMOS)
• Single-chip GSM radio
• 90m digital CMOS with
no analog extensions
• Package: 10x10mm2
BGA w/ 0.5mm ball
pitch
• ITX: 47mA @ 1.4V
• IRX: 56mA @ 1.4V
• NF = 1.9dB (!)
• No TX bandpass SAW
filter
• SoC: 24mm2
• DRP: 3.8mm2
• DRP consumes only
16% of SoC area
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• System solution including BB+RF and powermanagement unit (PMU)
– reduction of PCB size
– due to RF integration, only RX and TX interconnections
to SAW filters and PA are required
– bill-of-material (BOM) reduction
Æ faster development and less effort for mobile phone
manufacturers
This and following 6 slides courtesy of G. Li Puma, Infineon Technologies
P. Andreani – System-on-Chip
System overview
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SiP details and photograph
• BB+RF SoC
– 0.13μm CMOS
– 6 Metal layers
– MIM-capacitors
– 20Ωcm substrate
– bumps over active area
– no deep trench
– Triple well
• PMU
– 0.25 μm CMOS
– thick top metal layer
– 5V capability
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Details of RF subsystem
SiP challenges
• RX
– Quad-band zero-IF
– 3rd order channel filter
– 90dB DR CT-ΣΔ ADC
– NF=2.4dB
– AM suppression of 88dB
• Crosstalk
– PMU to RF coupling
– BB to RF coupling
• Technology trends
– # digital gates ↑
– Clock frequency ↑
– I/O interface speed ↑
• TX
– linear polar modulator
– closed loop power
control
– +6dBm output power
Æ digital noise increases
• Two 26MHz output
buffers
• Thermal effects
• Digital interface to BB
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Temperature distribution
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Measured TX spectrum, GSM 914.8MHz
• PMU is the major contributor of heat Æ temperature
gradient
• Reduced thermal stress on RF part due to separation
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P. Andreani – System-on-Chip
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Measured sensitivity
SiP - conclusions
• SiP with integrated highly efficient power managementunit
• Measured sensitivity
with BB and PMU
running
• Fabricated in standard CMOS technologies
• RF performance is comparable to stand-alone CMOS
transceivers
• No degradation due
to integration
• Careful floorplanning, package routing, supply and
ground partitioning is mandatory
• Performance
comparable to
stand-alone
transceivers
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65nm CMOS 2-billion transistor quad-core Itanium
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Penryn family – 45nm CMOS
• ISSCC 2008-2009
• Maiden PLL Æ cleans ref.
clock (133MHz) jitter for core
PLLs
• Dynamic clock frequency
• Final max. clock = 2.0GHz
• 21.5x32.5mm2
• 170W @ 110 oC
• transistors:
•
•
•
•
•
P. Andreani – System-on-Chip
• 410 million transistors for
dual core, 820 million for
quad core
• World’s first working CPU
in a 45nm CMOS process
1.42B cache
430M core logic
157M system interface
39M I/O logic
2.046B total
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P. Andreani – System-on-Chip
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Nehalem – 45nm CMOS
Xeon – 45nm CMOS
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•
•
•
•
ISSCC 2009 (no photo)
8 Nehalem cores, 130W
2.3B transistor
16PLLs, 8DLLs
Same clock cleaning as
Itanium
• 4 power domains: 1) cores;
2) cache; 3) I/O; 4) PLLs +
thermal sensors
• ISSCC 2009
• Successor of Penryn
• 4 cores (each core with
own PLL and clock tree)
• 731M transistor
• Power from <10W to 130W
•
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Level shifter between domains
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