Download high efficiency linear power amplifiers

HIGH EFFICIENCY LINEAR POWER AMPLIFIERS:
ANALYSIS, LINEARIZATION AND
IMPLEMENTATION
A DISSERTATION
SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING
AND THE COMMITTEE ON GRADUATE STUDIES
OF STANFORD UNIVERSITY
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
Mehdi F. Soltan
June 2004
© Copyright by Mehdi F. Soltan 2004
All Rights Reserved
ii
I certify that I have read this dissertation and that, in my opinion, it is fully adequate in
scope and quality, as a dissertation for the degree of Doctor of Philosophy.
Donald C. Cox (Principal Adviser)
I certify that I have read this dissertation and that, in my opinion, it is fully adequate in
scope and quality, as a dissertation for the degree of Doctor of Philosophy.
Bruce A. Wooley
I certify that I have read this dissertation and that, in my opinion, it is fully adequate in
scope and quality, as a dissertation for the degree of Doctor of Philosophy.
Thomas H. Lee
Approved for the University Committee on Graduate Studies.
iii
Abstract
Power amplifiers are key components in wireless transceivers. Their function is to
amplify the signal and generate the required RF power that allows transmission of the
signal over the appropriate range. Linear power amplifiers are needed in many modern
wireless systems that deploy non-constant envelope modulations. Examples of such
modulations are seen in CDMA and OFDM systems.
A common disadvantage of linear power amplifiers compared to their nonlinear
counterparts is their substantially lower power efficiency. Since the power amplifier is
the component that consumes most of the power in a transmitter, this lower power
efficiency directly translates into lower talk time in portable systems. Therefore,
improving efficiency of linear power amplifiers is a major objective. Finding fast and
systematic nonlinearity analysis methods and tools as well as linearization techniques that
promise higher efficiency are among the major challenges along this way. An additional
challenging requirement in portable systems is the need for smaller and lower cost power
amplifier devices. This work addresses these challenges and provides improved methods,
techniques and devices.
iv
Acknowledgments
I am indebted to so many people who have helped me in various stages of my life and
throughout my education. Completion of this work at Stanford would not have been
possible without all that support. It is beyond my capabilities to really articulate an
acknowledgment that can covey my most sincere and deepest gratitude to all those
people, whether explicitly mentioned here or not.
First I thank Professor Donald C. Cox, my primary academic advisor. Over the past
several years he has not only provided me with the best of the vision, advice and
encouragement that a graduate student might ever receive from his Ph.D. advisor, but
also has most kindly supported and advised me in almost every aspect of my life. I will
remain deeply indebted to him.
It is my pleasure to particularly thank Professors Bruce Wooley and Thomas Lee for all
their help during my stay at Stanford and for carefully reading a draft of this entire
dissertation. I also thank Professor David Leeson for kindly joining my orals committee
and Professor Abbas El Gamal who served as the chair of my orals committee.
I like to thank all my former teachers and professors as well as all my friends from whom
I have learned in the past.
I am most grateful to my family that has never let me feel that I am alone in my
endeavors. Without persistent support and encouragements from my parents and my wife
this work would never have finished. I also extend my thanks to my dear daughter,
Nazanin, who I hope can soon read this.
v
Contents
Abstract ..............................................................................................................................iv
Acknowledgments............................................................................................................... v
List of Tables....................................................................................................................viii
List of Figures ....................................................................................................................ix
Chapter 1: Introduction ....................................................................................................... 1
1.1 Basics of power amplifiers and classes ..................................................................... 3
1.2 Basics of nonlinearity................................................................................................ 9
1.3 Basics of linearization ............................................................................................. 12
1.4 Basics of signal and modulation dynamic range and effects on efficiency ............ 17
Chapter 2: More on PA nonlinearity and its effects on modulated signals....................... 19
2.1 Quasistatic versus dynamic nonlinearity................................................................. 21
2.2 A very fast method for simulating quasistatic nonlinearity effects......................... 26
2.3 Effects of the shape of the gain compression on ACPR ......................................... 38
2.4 A search for optimum gain compression shapes..................................................... 47
Chapter 3: PA linearization from an efficiency and complexity point of view ................ 49
3.1 More on EER and newer ER techniques................................................................. 50
3.1.1 Pulse deletion modulation ................................................................................ 53
3.1.1.1 In band vs. out of band linearity trade off ................................................. 56
3.1.1.2 Signal and modulation dynamic range effects .......................................... 60
3.1.1.3 Jitter in the signal constellations ............................................................... 65
3.1.1.4 Implementation methods for classes C and D amplifiers.......................... 73
3.1.1.4.1 Feedback methods .............................................................................. 79
3.1.1.4.2 Other methods .................................................................................... 82
3.1.1.4.3 Synchronous vs. asynchronous PDM................................................. 85
3.1.2 Pulse width modulation.................................................................................... 88
3.1.3 Pulse width and amplitude modulation (PW&AM)......................................... 92
3.1.3.1 EER with envelope feedback through bias control ................................. 100
3.1.3.2 Bias controlled envelope feedback without envelope elimination.......... 102
3.1.3.3 Envelope detector dynamic range and integrator offset effects .............. 108
3.1.3.4 Bandwidth effects and dynamic nonlinearity.......................................... 116
3.1.3.5 Potential for bias-controlled ER with envelope pre-distortion................ 123
3.2 Linearization by design of shape of gain compression curve ............................... 124
3.2.1 A note on self-biasing .................................................................................... 125
3.2.2 Cascade of self-biased nonlinear stages ......................................................... 128
Chapter 4: PA module constructions and matching methods ......................................... 139
4.1 Traditional output matching network topologies and implementations................ 141
4.2 A new approach to eliminate off chip discrete passives ....................................... 144
4.2.1 HP matching networks ................................................................................... 146
4.2.2 LPHP and LPLP networks ............................................................................. 150
vi
Chapter 5: Conclusion..................................................................................................... 159
5.1 Summary ............................................................................................................... 159
5.2 Future research directions ..................................................................................... 161
5.2.1 Integrated dynamic load adjustment .............................................................. 161
5.2.2 Sharing output devices for multiple bands..................................................... 163
5.2.3 CMOS PAs & breakdown .............................................................................. 164
5.2.4 Device layout.................................................................................................. 165
5.2.5 Dynamic interaction of thermal and electrical behaviors............................... 167
Bibliography.................................................................................................................... 169
vii
List of Tables
Table 1-1: Published articles indexed under “Power Amplifiers” ...................................... 1
Table 1-2 Class A PA.......................................................................................................... 4
Table 1-3: Class B and Class C PAs ................................................................................... 5
Table 1-4: Class D and Class E PAs ................................................................................... 6
Table 1-5: Class F PA ......................................................................................................... 7
Table 1-6: Summary of a few basic PA measures for classes A-F ..................................... 7
Table 1-7: Linearization by back-off ................................................................................ 12
Table 1-8: Predistortion and feedforward linearization .................................................... 13
Table 1-9: Feedback (polar and cartesian) linearization ................................................... 14
Table 1-10: LINC method ................................................................................................. 15
Table 1-11: Envelope elimination and restoration ............................................................ 16
viii
List of Figures
Figure 1-1: Sample output versus input power curve ......................................................... 3
Figure 1-2: Sample power added efficiency for different input powers ............................. 4
Figure 1-3: P1dB and IP3.................................................................................................... 9
Figure 1-4: AM to PM conversion .................................................................................... 10
Figure 1-5: Nonlinear capacitors are a source of AM-PM................................................ 10
Figure 1-6: Spectral regrowth ........................................................................................... 11
Figure 1-7: Probability distribution of signal average power in CDMA systems [1] ....... 18
Figure 2-1: Contributions of m and m& to spectrum of s& ............................................... 22
Figure 2-2: Compression curve, magnitude ...................................................................... 28
Figure 2-3: Compression curve, phase.............................................................................. 28
Figure 2-4: Power gain...................................................................................................... 29
Figure 2-5: Sample CDMA signal magnitude................................................................... 29
Figure 2-6: Undistorted input signal trajectory ................................................................. 30
Figure 2-7: Distorted output signal trajectory ................................................................... 30
Figure 2-8: Spectral regrowth ........................................................................................... 31
Figure 2-9: Amplitude probability distribution, CCDF .................................................... 31
Figure 2-10: ACPR for various power outputs ................................................................. 32
Figure 2-11: Comparison of measured and simulated ACPRs ......................................... 34
Figure 2-12: Transfer characteristic with 5% fluctuation ................................................. 36
Figure 2-13: Effect of magnitude error on ACPR............................................................. 36
Figure 2-14: Linear amplifier with sharp saturation ......................................................... 38
Figure 2-15: Gain and ACPR in a sharply saturated amplifier ......................................... 39
Figure 2-16: Effect of gain compression on ACPR .......................................................... 40
Figure 2-17: Effect of gain expansion on ACPR .............................................................. 41
Figure 2-18: ACPR of an expansive/compressive gain profile......................................... 41
Figure 2-19: ACPR of a compressive/expansive gain profile........................................... 42
Figure 2-20: Effect of gain magnitude profile on ACPR .................................................. 43
Figure 2-21: Effect of gain magnitude profile on ACPR .................................................. 43
Figure 2-22: Effect of gain magnitude profile on ACPR .................................................. 44
Figure 2-23: Effect of AM-PM on ACPR......................................................................... 45
Figure 2-24: ACPR of different phase profiles ................................................................. 46
Figure 2-25: ACPR in presence of large AM-PM............................................................. 46
Figure 3-1: Envelope elimination and restoration............................................................. 50
Figure 3-2: EER using a delta modulated Class-D switching power supply [32]............. 51
Figure 3-3: Envelope and phase modulated signals generated separately by DSP [1]. .... 51
Figure 3-4: Full power with no pulses dropped ................................................................ 53
Figure 3-5: 2 out of 8 pulses dropped ............................................................................... 53
Figure 3-6: 3 out of 8 pulses dropped ............................................................................... 53
Figure 3-7: Sample output filter frequency response ........................................................ 56
Figure 3-8: Case a ............................................................................................................. 57
Figure 3-9: Case b ............................................................................................................. 57
Figure 3-10: Spectrum of the signals for cases a and b..................................................... 57
ix
Figure 3-11: PDM output spectrum .................................................................................. 58
Figure 3-12: Output spectrum with better filtering ........................................................... 59
Figure 3-13: Impact pulse dropping ratio on spectrum ..................................................... 60
Figure 3-14: Impact pulse dropping ratio on spectrum ..................................................... 61
Figure 3-15: Spur levels with PDM based power level adjustment.................................. 62
Figure 3-16: AM modulation with PDM........................................................................... 63
Figure 3-17: AM modulation with PDM........................................................................... 63
Figure 3-18: AM modulation with PDM........................................................................... 63
Figure 3-19: AM modulation with PDM........................................................................... 63
Figure 3-20: AM modulation with PDM........................................................................... 63
Figure 3-21: AM modulation with PDM........................................................................... 63
Figure 3-22: Digital modulation with PDM...................................................................... 65
Figure 3-23: Digital modulation with PDM...................................................................... 65
Figure 3-24: Filtered output tracks input........................................................................... 65
Figure 3-25: Digital modulation with PDM...................................................................... 65
Figure 3-26: I-Q trajectory ................................................................................................ 66
Figure 3-27: I-Q trajectory ................................................................................................ 66
Figure 3-28: Signal constellation ...................................................................................... 66
Figure 3-29: Signal constellation ...................................................................................... 66
Figure 3-30: PDM induced jitter ....................................................................................... 67
Figure 3-31: Time/phase jitter for the modulation ............................................................ 68
Figure 3-32: Output constellation for OSR=64................................................................. 69
Figure 3-33: Output constellation for OSR=16................................................................. 69
Figure 3-34: PDM jitter for OSR=64 ................................................................................ 70
Figure 3-35: PDM jitter for OSR=16 ................................................................................ 70
Figure 3-36: Phase jitter for various carrier/modulation frequencies ............................... 71
Figure 3-37: Modulation timing curve .............................................................................. 71
Figure 3-38: Modulation timing curve .............................................................................. 71
Figure 3-39: Simulation vs. fast estimates on phase jitter................................................. 72
Figure 3-40: PDM on Class C amplifier ........................................................................... 73
Figure 3-41: PDM on Class D amplifier ........................................................................... 75
Figure 3-42: Waveforms at full power.............................................................................. 75
Figure 3-43: Waveforms at 6dB back off.......................................................................... 75
Figure 3-44: Normalized efficiency for PDM and Class A .............................................. 77
Figure 3-45: Asynchronous envelope delta modulation ................................................... 79
Figure 3-46: Synchronous envelope delta modulation...................................................... 80
Figure 3-47: Lookup table based synchronous PDM........................................................ 82
Figure 3-48: Synchronous PDM using envelope sigma-delta........................................... 83
Figure 3-49: Magnitude of spurious in asynchronous PDM ............................................. 86
Figure 3-50: Frequency of spurious in asynchronous PDM ............................................. 86
Figure 3-51: Constellation jitter in asynchronous PDM ................................................... 87
Figure 3-52: Modulating Class F amplifier with PWM .................................................... 88
Figure 3-53: Magnitude vs. duty cycle in PWM ............................................................... 89
Figure 3-54: Waveforms in a PWM Class F amplifier ..................................................... 89
Figure 3-55: PWM only creates narrow band harmonics ................................................. 90
Figure 3-56: PW&AM on a Class C amplifier.................................................................. 92
x
Figure 3-57: PW&AM efficiency for various maximum conduction angles.................... 94
Figure 3-58: 30% conduction angle profile....................................................................... 96
Figure 3-59: Efficiency for the 30% conduction angle profile ......................................... 96
Figure 3-60: 50% conduction angle profile....................................................................... 97
Figure 3-61: Efficiency for the 50% conduction angle profile ......................................... 97
Figure 3-62: 100% conduction angle profile..................................................................... 98
Figure 3-63: Efficiency for the 100% conduction angle profile ....................................... 98
Figure 3-64: Output magnitude as a nonlinear function of base bias................................ 99
Figure 3-65: EER with envelope feedback through bias control .................................... 100
Figure 3-66: Output power controlled by supply voltage ............................................... 102
Figure 3-67: Output power controlled by base bias voltage ........................................... 103
Figure 3-68 AM-PM in supply and base bias controlled amplifiers ............................... 103
Figure 3-69: Effect of limiter on the drain efficiency of the output stage ...................... 106
Figure 3-70: Envelope feedback PW&AM without limiter ............................................ 107
Figure 3-71: Waveform for an envelope detector with dead-zone.................................. 108
Figure 3-72: Effect of dead-zone on the spectrum of detected envelope........................ 109
Figure 3-73: Mismatch in envelope detectors ................................................................. 110
Figure 3-74: Error from envelope detector mismatch..................................................... 111
Figure 3-75: Spectrum of error form mismatch .............................................................. 111
Figure 3-76: Dead-zone effect in a closed loop system .................................................. 112
Figure 3-77: Dead-zone effect in a closed loop system .................................................. 113
Figure 3-78: Dynamic range of a PW&AM system with envelope feedback................. 114
Figure 3-79: Closed loop system tracks slower modulations.......................................... 116
Figure 3-80: Closed loop system fails to track fast modulations .................................... 117
Figure 3-81: Frequency response of a closed loop PW&AM system ............................. 118
Figure 3-82: Loop gain effect on envelope stability ....................................................... 119
Figure 3-83: In-channel linearity and stability................................................................ 120
Figure 3-84: Out-of-channel linearity and stability......................................................... 121
Figure 3-85: Biasing an amplifier stage .......................................................................... 125
Figure 3-86: Effect of load impedance on self-biased DC current ................................. 126
Figure 3-87: Effect of load impedance on gain and power output.................................. 127
Figure 3-88: Self-biasing for various quiescent currents ................................................ 128
Figure 3-89: Shape of gain .............................................................................................. 129
Figure 3-90: Phase variation ........................................................................................... 130
Figure 3-91: Impact of the second stage on current of the driver stage .......................... 130
Figure 3-92: Power added efficiency of the two stage amplifier .................................... 131
Figure 3-93: Power added efficiency of the two stage amplifier .................................... 132
Figure 3-94: Power added efficiency of the two stage amplifier .................................... 132
Figure 3-95: Linearity of the two stage amplifier ........................................................... 133
Figure 3-96: Measured gain ............................................................................................ 135
Figure 3-97: Measured ACPR......................................................................................... 135
Figure 3-98: Measured power added efficiency.............................................................. 136
Figure 4-1: A two stage low pass matching network ...................................................... 141
Figure 4-2: A traditional PA module............................................................................... 142
Figure 4-3: Low pass matching....................................................................................... 147
Figure 4-4: High pass matching ...................................................................................... 147
xi
Figure 4-5: PA module in a lead frame package with no discrete passives .................... 148
Figure 4-6: Measure power added efficiency.................................................................. 149
Figure 4-7: Measured linearity........................................................................................ 149
Figure 4-8: Low pass-low pass matching........................................................................ 150
Figure 4-9: Low pass-low pass matching with one discrete capacitor............................ 151
Figure 4-10: Low pass-high pass matching..................................................................... 152
Figure 4-11: Implementation of LPHP matching............................................................ 152
Figure 4-12: High pass-high pass matching.................................................................... 153
Figure 4-13: Implementation of HPHP matching ........................................................... 153
Figure 4-14: A grossly power imbalanced PA ................................................................ 155
Figure 4-15: A PA with some power imbalance ............................................................. 155
Figure 5-1: Power added efficiency with load adjustment.............................................. 162
Figure 5-2: A compact layout for a power transistor [86]............................................... 166
xii
Chapter 1: Introduction
Power amplifiers are used in many different applications including the majority of
wireless and radio communications equipment, wireless and cable TV broadcast systems,
cable and other wired transmission systems, optical driver amplifiers, audio systems and
Radars. Depending on the application, frequencies range from audio frequencies to
millimeter wave frequencies. Amplifier power ranges from a few milliwatts to several
megawatts are used for different applications. Over many years the knowledge of related
technologies and the design of these amplifiers has been developed. Table 1-1 represents
interesting sample statistics on the most directly related publications indexed by IEEE
alone.
Publication Year
Before 1980
1980 to 1990
1990 to 1998
1998 to 2/2004
Number of
195
397
1682
1854
Articles
Table 1-1: Published articles indexed under “Power Amplifiers”
in IEEE and affiliated publications
While some knowledge has been developed that is common to a wide variety of
applications, increasing specialization has led to the creation of a large number of
techniques and technologies that are useful only in very specific power amplifiers.
In this dissertation our main focus is on applications for cellular phone handsets and
portable wireless devices, with an emphasis on linear power amplification. CDMA,
TDMA and OFDM based handsets (or other portable systems) are among these related
applications. The carrier frequencies in these applications range from several hundred
megahertz to a few gigahertz, while peak powers of 100 milliwatts to a few watts are
most common. The most well known common objectives in amplifier designs for these
applications are: cost and size reduction; efficiency and talk time improvement; and
1
meeting linearity, gain, stability, robustness, reliability and other related requirements.
Many of the specific techniques, technologies and tradeoffs discussed in this dissertation
are directly useful in other applications as well. Therefore, while our main focus is linear
amplifiers, we briefly stretch further into some nonlinear applications such as GSM
handsets to highlight the more general applicability of the techniques.
Based on this focus, this dissertation is organized in five chapters. In the remainder of
this chapter, we will very briefly review some related background material. The objective
is to allow those new to the field to quickly gain a good overview of power amplifiers
and related technologies. One of the primary needs of researchers and designers working
on linear amplifiers is to quickly assess, analyze, design and optimize amplifier
nonlinearities based on their specific objectives. Chapter 2 focuses on a methodology and
a tool developed to address this need. In Chapter 3 we will present four non-traditional
categories of linearization methods. The common objective among those schemes is to
enhance the talk time of the portable wireless equipment using such amplifier systems.
Each of these is analyzed from the efficiency behavior and complexity viewpoints. In
cases where nontraditional effects or artifacts come to play analysis is provided to
enhance our understanding. Chapter 4 covers implementation issues related to power
amplifier modules. That chapter covers some newer topologies for output impedance
transformation networks that enable manufacturing of smaller and lower cost modules
followed by a brief discussion on some of the most important, but infrequently cited,
additional concerns in power amplifier design. We conclude in Chapter 5 by
summarizing the main points discussed in the first four chapters, followed by an
identification of main areas for future research on power amplifiers for handsets and
portable wireless systems.
2
1.1 Basics of power amplifiers and classes
RF and microwave power amplifiers, PA’s, are devices that amplify the input RF or
microwave signals and deliver much higher power at the output. Power gain, defined as
the ratio of the output RF power to input RF power, is therefore a primary performance
measure. The power amplifier can also be considered a device that converts DC power
provided from the supply into RF power at the output. One of the most critical
performance measures of a PA is the efficiency of this conversion process. Drain or
collector efficiency is defined as the ratio of RF output power to the DC power provided
from the supply. Power added efficiency is another measure that is the ratio of the output
RF power, less input RF power, to the total power into the device (DC+RF).
Pout − Pin
Eq. 1.1-1
Ptotal
PAE = η =
The power amplifier dissipates a major portion of the total power in many portable
systems such as phone handsets. Therefore, the efficiency of that amplifier is the most
important factor affecting the talk or operation time. Figure 1-1 and Figure 1-2 show
sample behaviors of a typical power amplifier. A rather good general review of these
basic concepts on RF power amplifiers can be found in [1].
Pout
Output
Compression
Curve
Output
Compression curve
Pin
Figure 1-1: Sample output versus input power curve
3
PAE
Power Added Efficiency
Pin
Figure 1-2: Sample power added efficiency for different input powers
In order to allow better analysis and understanding of their behaviors, power amplifiers
are grouped into different classes of operation. The classification is primarily based on
voltage and current waveforms, and hence based on operating conditions and topologies
[1, 2]. Tables 1-2 to 1-5 list the best known classes of PAs with some basic pictures of
waveforms and topologies.
Class Information:
Class A
Conduction angle is 360deg (100%)
Circuit Topology
Waveforms
Vd
VDD
VDD
Vd
Vin
RL
id
t
Ploss
t
IDC
t
Ploss is the power dissipated in the device
Table 1-2 Class A PA
4
Class Information:
Class B
Conduction angle is 180deg (50%)
Circuit Topology
Waveforms
Vd
VDD
VDD
id
Vd
RL
Vin
IDC
Ploss
2ϕ
Class Information:
Class C
Conduction angle is less than 180deg (less than 50%)
Efficiency and Power Capability
Circuit Topology
as functions of Conduction angle
η
100%
Power Capability
0.134
0.125
VDD
78.5%
Vd
Vin
RL
50%
C
0
B AB A
50% 100%
Conduction angle
C
0
0
B AB A
50% 100%
68.1%
Conduction angle
Waveforms are similar to those shown for Class B
Table 1-3: Class B and Class C PAs
5
Class Information:
Class D
No time overlap between transistor’s drain source voltage and drain current
Circuit Topology
Waveforms
Vd1
2VDD
Vd1
id1
Vin
VDD
RL
-Vin
id1
id2
id2
Class Information:
Class E
No time overlap between transistor’s drain source voltage and drain current
First derivative of VDS is zero at the moment device turns on
Circuit Topology
Waveforms
VDD
C2
Vd
Vin
C1
L
RL
Table 1-4: Class D and Class E PAs
6
Class Information:
Class F
No time overlap between transistor’s drain source voltage and drain current
Circuit Topology
Waveforms
Vd
VDD
2VDD
vd
λ/4 @ ω0
Vin
RL
8VDD
πRL
id1
Table 1-5: Class F PA
Class
Efficiency
η%
Normalized
RF Power
Po ,max
Vdd 2 /( 2 R )
D
50
78.5
86
(θ=71°)
100
E
100
F
100
A
B
C
Normalized
Normalized
vd max
id max
Vd max
Vdd
id max
I DC
Power
capability
Po ,max
Vd ,max id ,max
1
1
1
2
2
2
2
3.14 (=π)
3.9
0.125
0.125
0.11
1.624
(=16/π2)
1.154
(=4/(1+π2/4))
1.624
(=16/π2)
2
3.6
1.57
(=π/2)
2.86
0.318
(=1/π)
0.098
2
3.14 (=π)
0.159
(=1/2π)
Table 1-6: Summary of a few basic PA measures for classes A-F
7
Aside from efficiency, there are other measures that can be used to benchmark power
amplifiers. Normalized RF power is a measure that can provide a rough estimate of the
load impedance required for delivering certain power in an ideal case. Normalized
maximum theoretical voltage and currents for different classes can help to determine the
required device voltage breakdown and current handling capabilities. Power capability is
another measure that can provide a basis to compare different classes from the required
device size point of view.
Table 1-6 summarizes definitions and optimum theoretical
values for these measures for Classes A to F.
More on PA classes can be found in [3, 4, 5 and 6]. One has to keep in mind though that,
due to many known and unknown practical factors, optimum theoretical values can not be
achieved in reality. Indeed, even determining the class of operation in many practical
amplifiers is not easy and sometimes becomes impossible. In many cases amplifiers can
be modeled as one class at certain power output levels, and as another class in a different
power output range. However, this classification approach is very useful in providing
insights and starting points for design tradeoffs in power amplifiers. In addition to the
theoretical class-based design, some of the best known measurement based device
modeling and design approaches are based on load-pull and source-pull measurements
[2, 7].
8
1.2 Basics of nonlinearity
Power amplifiers are nonlinear systems because the large signal behavior of the
semiconductor devices is nonlinear. Power output saturation, as shown in Figures 1-1 and
1-3, is one nonlinear behavior that occurs in every amplifier.
Among the measures for nonlinearity are P1dB and IP3. Figure 1-3 illustrates those
measures on a typical amplifier power out versus power in curve. IP3 is the extrapolated
intercept of the desired linear output with the 3rd order intermodulation with two-tone
excitation. P1dB is where the output drops 1dB below the desired linear output. These
measures are independent of input signal modulation schemes.
Desired linear
output
1dB
3rd order intermod term
IP1dB IIP3
Figure 1-3: P1dB and IP3
In addition to the amplitude (AM) nonlinearity, power amplifiers usually also exhibit
some amplitude to phase conversion behavior (AM-PM) as shown in Figure 1-4 for a
sinusoidal input. AM-(to)-PM refers to the creation of phase modulation (PM) observed
at the output of a nonlinear amplifier when amplifying amplitude modulated (AM)
9
signals. AM-PM is often the result of voltage dependent capacitors (e.g. junction
capacitors). Figure 1-5 illustrates this mechanism.
Phase (Deg)
AM-PM curve
Pin (dBm)
Figure 1-4: AM to PM conversion
Vout(t)
Iin=Asin(ωt)
R
C
Vout (t ) = B(t )Cos (ωt + ϕ (t ))
C = C[Vout (t )] ⇒ C ≈ C[ B(t )]
ϕ (t ) = tan −1 ( RC[ B(t )]ω )
ϕ ≈ tan −1 ( RC ω )
C = Average capacitor value at the fist harmonic
ϕ
=Average phase at the fist harmonic
Figure 1-5: Nonlinear capacitors are a source of AM-PM
Amplitude dependent amplifier nonlinearity interacting with modulated carriers with
variable envelopes causes an effect called spectral regrowth. A modulated carrier can be
considered as a large set of tones squeezed into a particular frequency band around the
carrier. Amplifier nonlinearity creates intermodulation products among these tones. The
10
net effect is that additional unwanted spectral components are created. The creation of
these additional components is called spectral regrowth. Figure 1-6 shows a typical
spectrum of a nonlinear amplifier output that has suffered spectral regrowth.
PLo
PHi
Po
Figure 1-6: Spectral regrowth
ACPR HI =
PHI
Po
ACPR LO =
PLO
Po
Eq. 1.2-1
Several measures of system nonlinearity are defined based on the amount of regrowth
related artifacts that are created for particular modulations. Adjacent channel power ratio
(ACPR) is the most often used parameter for characterizing CDMA amplifiers. ACPR is
defined as the ratio of unwanted power created in a specific channel within a specified
bandwidth at a specified frequency offset from the main carrier, divided by the power in
the desired modulation bandwidth. ACPR is illustrated in Figure 1-6. For example, in
PCS CDMA (IS-95) [34], ACPR is defined as the ratio of the power in a 30kHz
bandwidth at 1.25MHz offset from the center frequency, divided by the power in the
main modulation bandwidth. Unlike P1dB and IP3, ACPR and other spectral regrowth
based nonlinearity measures are heavily dependent on the modulating signal. As a result,
using specific signal characteristics and statistics is very important in simulating or
measuring ACPR in nonlinear systems.
11
1.3 Basics of linearization
In order to improve the linearity of amplifiers, many linearization schemes have been
developed for different applications over many years. Tables 1-7 to 1-11 provide a listing
of the most well known linearization methods. There is extensive literature available on
most of these traditional linearization schemes and their more modern variations. Some
additional general information can be found in [8 and 9].
Back-off
Transmit less power to achieve higher linearity by avoiding the saturation nonlinearity.
Highlights:
1. Back-off is the simplest linearization
technique.
2. The required back off depends on
modulation type, AM-to-AM and AMto-PM distortion levels.
3. Efficiency is sacrificed to achieve
desired linearity
4. Low cost and no added complexity
Table 1-7: Linearization by back-off
12
Predistortion
Compensate for amplifier gain and phase variation over power range by applying an
inverse nonlinearity to the input signal prior to entering the amplifier.
Baseband
IN
RF out
Correction
Gain
Modulator
phase
Gain
Gain
phase
phase
Overall Response
Highlights:
1. Look up table is perfectly suited for open loop predistortion.
2. Process and temperature variations as well as long term drifts usually mandate the
need for adaptation.
3. Adaptive predistortion systems can be complex.
References: [9,10, 11 and 12]
Feedforward
Correct the nonlinearity by subtracting an estimate of nonlinearity induced artifacts from
the output.
RFin
+
Delay
PA
Σ
-
Attenuator
Auxiliary
Amp
Delay
+
Σ
PA
Error
Highlights:
1. Requires a linear auxiliary PA to amplify the error signal.
2. Requires matching of the delays and attenuation/gain behaviors in order to function
correctly.
3. Efficiency is low due to losses in the output delay line, output power combiner and
the auxiliary amplifier.
4. Sensitivity to parameter variations over temperature and time usually mandates the
need for complex adaptive schemes.
References: [9,13,14 and 15]
Table 1-8: Predistortion and feedforward linearization
13
Polar Feedback
Using feedback from the output, detect magnitude and phase information and use it to
correct the signal fed into the amplifier by comparing it with that of the desired input
signal.
PD
θ
VCO
Filter
PA
VGA
Filter
r
+
Σ -
Envelope
Detector
Highlights:
1. Two feedback loops: One for phase and one for magnitude. Stability is a concern.
2. Bandwidth of the envelope loop should be reasonably larger than the envelope
maximum frequency.
3. When AM-to-PM is manageable, phase feedback may be eliminated.
4. High performance envelope detection is required.
Reference: [16]
Cartesian Feedback
Feedback a sample of the output, demodulate and detect in-phase and quadrature
components and use them to correct the signals fed into the amplifier by comparing them
with those of the desired signal.
I
Q
+
Σ
-
LPF
+
Quadrature
Modulator
Σ
PA
LPF
-
Phase
Adjustment
LO
Quadrature
Demodulator
Highlights:
1. Two feedback loops on I&Q. Stability is a concern.
2. I& Q phases have to be aligned
3. Loop bandwidth has to be reasonably higher than I & Q channel bandwidths.
References: [17-21]
Table 1-9: Feedback (polar and cartesian) linearization
14
LINC
(Linear amplification using nonlinear components.)
Modulate the amplitude by combining two out-phased constant envelope amplified
signals whose phase difference contains the amplitude information.
S1(t)
PA
S(t)
Signal
Separator
Σ
PA
S2(t)
+
K*S(t)
+
s (t ) = b(t ) cos( wt + ϕ (t ))
s1 (t ) = A cos( wt + ϕ (t ) + α (t ))
s2 (t ) = A cos( wt + ϕ (t ) − α (t ))
α (t ) = cos −1 (b(t ) / 2 A)
S1(t)
α(t)
S(t)
-α(t)
S2(t)
Highlights:
1. When fully matched hybrid combiners used, efficiency is proportional to the average
output power due to the loss in the hybrid.
2. Lossless combining on the other hand stresses the individual amplifiers reducing their
efficiency, and degrades the overall linearity.
3. Not efficient for modulations with large peak to average ratio
4. Difficult to implement the signal separator with analog components.
References: [22-28]
Table 1-10: LINC method
15
Envelope Elimination and Restoration (EER)
(Also known as Kahn technique)
Amplify a constant envelope signal containing the phase information using an efficient
nonlinear amplifier and superimpose the envelope variation by modulating the supply
voltage of the amplifier.
RFin
Envelope
Detector
Supply
modulator
RFout
Limiter
PA
Highlights:
1. Requires a very low loss, power efficient and fast supply modulator, such as class S
supply modulators or sigma delta DC-DC converters
2. Supply variations result in AM-to-PM distortion.
3. Delay mismatch between the envelope and RF phase paths can result in distortion.
4. Envelope feedback can be used to improve the linearity
5. A variation of this technique that uses amplifiers with additional back-off to
guarantee linearity is called envelope tracking
References: [29-33]
Table 1-11: Envelope elimination and restoration
16
1.4 Basics of signal and modulation dynamic range and effects on efficiency
As briefly noted in the previous section, linearity measures such as ACPR are dependent
on modulation characteristics such as dynamic range, statistical distribution and
modulation bandwidth and therefore vary for different modulation schemes. Measures
such as modulation peak to average and peak to minimum are used to convey further
insight into modulation dynamic range and how the signal amplitude fluctuates.
However, as will be seen in the next chapter, for precise measurement or estimation of
ACPR, signals with the exact modulation and having the correct cumulative distribution
function (CDF) of the amplitudes must be used. As a result, acquiring precise knowledge
of signal characteristics is a prerequisite to any amplifier optimization. Among the
systems requiring linear amplifiers are CDMA and OFDM based systems. A good review
of the signal characteristics in these kinds of systems can be found in [34 and 35]. In the
following chapters the effects of amplifier nonlinearity on modulated signals in general
and CDMA signals in particular will be discussed in further detail. Some related
information specific to OFDM systems can be found in [36].
In most modern wireless systems, power control schemes are used to reduce transmit
power when full power is not necessary in order to minimize unnecessary interference
and thus maximize the system capacity. For example, in CDMA systems, the average
power of the transmitted signals is varied over a range as large as 70dB [1 and 34].
The statistical distribution of the average power output varies as a function of where the
handset is functioning. This is illustrated in Figure 1-7 for urban and suburban areas. One
has to distinguish between modulation dynamic range, which can be defined as the peak
to average or peak to minimum signal power for a particular average power output, and
the dynamic range of the average power output such as the ones shown in Figure 1-7.
17
Figure 1-7: Probability distribution of signal average power in CDMA systems [1]
One practical implication of such large dynamic ranges is the need to characterize and
improve the efficiency of power amplifiers over wide power output ranges. This renders
single power efficiency data useless and therefore requires efficiency roll-off curves to
objectively compare various amplifiers and linearization schemes. This is done in
Chapter 3. More information on signal dynamic range can be found in [37]. Among the
main techniques developed to improve efficiency roll-off behavior in nonlinear amplifiers
are Doherty amplifiers [38] and stage bypassing [39]. In Doherty amplifiers an auxiliary
amplifier is used next to the main amplifier. At high power outputs the auxiliary amplifier
functions and causes a reduction in the load impedance seen by the main amplifier. This
allows the main amplifier to see higher load impedance at lower power outputs while
experiencing the correct impedance at higher power outputs. As a result Doherty
amplifiers show higher efficiencies at lower powers. Stage bypassing is based on the
concept that low power outputs can be delivered by driver stages. Therefore the output
stage devices in a PA can be turned off and bypassed to save power at lower power
outputs.
18
Chapter 2: More on PA nonlinearity and its effects on modulated
signals
So far we have discussed the general effects caused by amplifier nonlinearity such as
spectral regrowth, harmonics, spurs, oscillatory behaviors, etc. We have also
discussed briefly the measures and metrics used for quantifying nonlinearity effects.
We have noted measures like IP3 and P1dB as general measures for the amplifiers.
We have also looked at modulation dependent measures such as ACPR, that are used
to assure compliance with standards with respect to unwanted signal emission that
occurs because of spectral regrowth.
One of the issues that designers face in the design of linear amplifiers for specific
digital modulation standards is how to simulate and predict the behavior of their
designs when amplifying modulated signals. We usually have to make sure that the
design robustly maintains linearity, e.g. the ACPR margin holds over a range of
frequencies, power outputs and temperatures. Also, in order to estimate ACPR
measures with acceptable variance, they have to be averaged over a few hundred
transmitted symbols, e.g. for CDMA this means an averaging time between 100µs to
1ms. The cell phone carrier frequencies are in the GHz range, e.g. 850 MHz for cell
band CDMA or 1.7- 1.9GHz for PCS CDMA. This means that if we want to estimate
ACPR using an FFT and running a regular transient simulation on our amplifier, it
would require us to obtain 4 to 40 million data points, depending on the desired
precision, for just one specific combination of frequency, temperature, power output,
circuit topology and bias level. With current computers and transient simulation
technologies, obtaining even one ACPR point for a specific case takes a prohibitively
long time. One feasible approach to avoid the problem is to use theoretical estimates
[40 and 41]. Unfortunately these theoretical methods can’t be easily adapted to
address various amplifier characteristics and hence do not provide a reliable and easy
to use tool for designers and researchers. One alternative solution is to use simulation
engines that support algorithms based on envelope transient simulation in conjunction
with harmonic balance simulation [42]. Those algorithms take advantage of the fact
19
that in most RF systems, the envelope frequency, or the modulation frequency, is
much smaller than the carrier frequency. Based on this assumption they have
combined harmonic balance and transient simulation algorithms to provide a solution
for these cases. While the approach provides useful results, the simulation time per
point ranges from several minutes to a few hours depending on the computer used,
circuit complexity, and how close to saturation the amplifier is driven. This limits the
usefulness of the approach only to providing reassurance for a few specific
conditions. It is almost impossible to use those tools for heavy exploration of the
trade offs or optimization in the design. In order to serve the unaddressed need for an
easy to use tool that could effectively predict nonlinearity effects of the linear power
amplifiers, an approach and a program were developed that allow very fast estimation
of effects such as ACPR and constellation jitter generated by amplifier nonlinearity.
The tool has enabled the development of an extremely interesting new linearization
technique that is discussed in chapter 3. This chapter will discuss the basics of the
approach, results from the program and results of a search to find optimum power
amplifier compression curve characteristics for specific modulations.
20
2.1 Quasistatic versus dynamic nonlinearity
A modulated carrier can be represented as
s(t ) = a(t ) ⋅ cos(2πf c t + ϕ (t ))
Eq. 2.1-1
or
s(t ) = Re{m(t ) ⋅ e j 2πfct }
Eq. 2.1-2
where
m(t ) = a (t ) ⋅ e jϕ (t )
Eq. 2.1-3
is the complex modulation of a band limited signal with frequency content only at much
lower frequencies than the carrier frequency f c .
In a general case a power amplifier, in response to a signal s (t ) , will generate an output
signal u (t ) , that can be a nonlinear dynamic function of s (t ) with the dynamics
represented by derivatives of s (t ) .
u = f ( s, s&, &s&, &s&&, L)
Eq. 2.1-4
where
s& = Re{(m& + j 2πf c m).e j 2πfct } Eq. 2.1-5,
&s& = Re{(m
&& + j 4πf c m& + ( j 2πf c ) 2 m).e j 2πfct } Eq. 2.1-6
etc.
The functional relationship, f (.) , depends on the amplifier circuit and operating
conditions.
21
Let us first consider a simple case where the modulation, m(t ) , is a single tone signal at
the frequency of f env much smaller than f c .
m(t ) = cos(2πf envt )
Eq. 2.1-7
m& (t ) = 2πf env sin(2πf envt )
Eq. 2.1-8
s& = Re{(m& + j 2πf c m) ⋅ e j 2πfct }
= Re{(2πf env sin(2πf envt ) + j 2πf c cos(2πf envt )) ⋅ e j 2πfct }
π
2
π
2
Eq. 2.1-9
Magnitude of Spectrum
fc
m
f env
m& component
f c − f env
component
f c + f env
Frequency
& to spectrum of s&
Figure 2-1: Contributions of m and m
As observed in the spectrum of s& in Figure 2-1, the m& related component is suppressed
by a factor of f c / f env compared to the component due to m . When m(t ) is well behaved
and band limited, which is the case for practical modulation signals having maximum
frequency of f env , the same kind of suppression occurs on all spectral components of
m& compared to their equivalent in m . Since all the spectral content in the modulation
signal is at frequencies lower than f env , f c / f env serves as a lower bound for the
suppression factors of the spectral components in m& .
22
For example, this minimum suppression is more than 67dB in a PCS CDMA system. The
same suppression mechanism is in effect with the higher order time based derivatives of
the signal. Therefore with good precision the output can be estimated as
u ≅ f (Re{m ⋅ e j 2πfct }, Re{j 2πf c ⋅ m ⋅ e j 2πfct }, Re{( j 2πf c ) 2 ⋅ m ⋅ e j 2πfct },L) = g ( fc, m)
Eq. 2.1-10
This conveys an approximate or quasistatic relationship between u and m .
Usually when the amplified signal is a narrowband modulated carrier as in the current
cellular phones and most other wireless systems, the output signal can also be represented
as
u = Re{∑ α n (t ) ⋅ e jθ n (t ) ⋅ e j 2πnfct } + Ω( fc, m, t ) Eq. 2.1-11
where
α n (t ) ⋅ e jθ
n (t )
⋅ e j 2πnf ct represents
the
signal
around
the
n th harmonic
and
Ω( fc, m, t ) represents other unwanted signal contributions including potential out of band
spurs, oscillations, subharmonics and noise. All of the in band components are included
in the α 1 (t ) ⋅ e jθ1 ( t ) ⋅ e j 2πf ct term. Here in band refers to the spectral components whose
frequencies are close enough to the carrier that they fall in the same or immediately
adjacent application frequency band as that of the carrier, e.g. in CDMA systems spectral
components that are less than 50MHz away from the carrier for this purpose can be
considered in band. The remainder of the terms represent out of band contributions. The
phrase “in band nonlinearity” can be used to describe nonlinear behavior, specifications,
measures and signals that cause, contribute to, or otherwise refer to the
α 1 (t ) ⋅ e jθ (t ) ⋅ e j 2πf t term. We can refer to all the other effects caused by nonlinearity as
1
c
“out of band nonlinearity.”
Thus, all the in band effects are governed by a relationship expressed as:
u1 = α 1 (t ) ⋅ e jθ1 ( t ) ≈ g1 ( f c , m) Eq. 2.1-12
23
The important message is that the dynamic effects of the circuit that shape the carrier
waveform or its harmonic content do not affect the modulation in a dynamic manner but
contribute to the shaping of a static relationship between input and output complex
modulation waveforms. The other important message is that the dynamic effects that
govern the behavior of the envelope or modulation do not affect the harmonic content
except through the magnitude and phase of the modulation. In summary the dynamics of
the envelope and carrier may be treated as decoupled.
In the above, which we will refer to as “quasistatic nonlinearity”, we have made two
basic assumptions:
1. The carrier frequency, fc , is much higher than maximum frequency of the
modulation, fenv.
2. The nonlinear signal path in the system is approximately the same for all the
spectral components. That means there is not a major decoupling or re-coupling
between the modulation and carrier signals when they travel through the
amplifier; they travel together.
The above two conditions together are sufficient but not always necessary to validate the
quasistatic nonlinear relationship between input and output of an amplifier.
An envelope detector with an envelope bandwidth much higher than the signal’s
maximum envelope frequency is a good example where we might still see a quasistatic
relationship between input and output even when the second condition is not met.
However when the second condition is not met, it can be a warning that we must be
careful about making the quasistatic assumption unless we can rule out the importance of
the modulation’s dynamics. We will revisit this matter later when discussing the EER
techniques. In EER systems the modulation and carrier signals are separated and
recombined and therefore they do not travel together. There we will provide examples of
systems in which the quasistatic assumption is not valid even though the condition 1 is
24
met. In general if the system’s bandwidth is narrow compared to the modulation, fenv, the
time dispersive behavior will violate condition 2.
A slightly different but essentially equivalent view of bandpass nonlinearities can be
found in [43]. There have been attempts in system level modeling of amplifiers with
dynamic nonlinearities, where the quasistatic assumption is not valid. The majority of
work has been focused on modeling of memory effects [44] or modeling and simulation
of weak wideband nonlinearities based on Volterra series [45]. Usefulness of such
approaches is usually limited to very specific cases. Fortunately, in most traditional single
carrier power amplifier circuits, where no elegant linearization techniques are used that
may involve narrow band feedback or dynamic adjustment based on narrow band
sampling of the signal or its envelope, the quasistatic assumption is valid. That covers all
of the handset PAs, even the ones with dynamic biasing schemes like the ones discussed
in section 3.2.
25
2.2 A very fast method for simulating quasistatic nonlinearity effects
As we discussed in the last section, when the quasistatic nonlinearity assumption holds
true
u1 = α 1 (t ).e jθ1 ( t ) ≈ g1 ( f c , m(t )) = g1 ( f c , a(t ).e jϕ ( t ) ) Eq. 2.2-1
governs all the in band nonlinearity effects. Therefore, in band modulation dependent
measures like ACPR, signal constellation and jitter can be derived from an output signal
estimated using Eq.2.2-1. An amplifier’s quasistatic characteristic has been successfully
used for estimating nonlinearity effects on analog linear modulations such as SSB [46].
The function g1 is in fact the complex nonlinear compression curve of the amplifier
circuit at one specific carrier frequency and operating condition. In simulation it can be
estimated easily by running a single sweep analysis over input amplitude in a harmonic
balance simulation. Using transient simulation it can be calculated by estimating the
magnitude and phase of the FFT of the output signal at the carrier frequency, swept over
input power. These analyses are very simple and for typical power amplifier circuits they
take between several seconds to a few minutes depending on the computer used and the
amplitude sweep range.
Based on the above simulation approaches we can easily estimate and record the behavior
of g1 as a table of magnitudes and phases of the output versus magnitudes and phases of
the input. Since in most practical situations the gain magnitude is independent of the
input signal’s phase, and only the phase shift between input and output is a function of
the magnitude, the table simply becomes a table of output signal magnitudes and the
phase shift versus the input signal magnitude.
With such data, the most natural approach for estimating the output signal attributes is
first to estimate the output signal itself using a finely interpolated version of the lookup
table and the complex modulation signal m(t ) , and then subsequently calculate all the
26
imperfection measures such as ACPR. For example, for PCS CDMA the right side
adjacent ACPR, defined as the ratio of signal power in an adjacent channel with an offset
of 1.25MHz from the carrier and bandwidth of 30kHz to the signal power in the main
channel, can be calculated from:
f c +1.25 MHz +15 kHz
∫ F (u )
acprh1 =
2
.df
f c +1.25 MHz −15 kHz
f c +885 kHz
∫ F (u)
2
Eq. 2.2-2
.df
f c −885 kHz
2
where F (u ) is the estimated power spectrum of the amplifier output.
Based on the principle described above, a MATLAB program called ACP was developed
to perform the following:
1. Generate complex modulation signals for various types of modulations, with
further emphasis on various CDMA standards.
2. Read in the lookup table for the complex gain compression curve and interpolate
it to a very finely quantized lookup table to minimize errors.
3. Estimate a time based index number for each time sample of the input signal
4. Estimate the output signal u1 (t ) = α 1 (t ) ⋅ e jθ1 ( t ) time samples by reading the
magnitude and adding the phase shift for the right index number from the table.
5. Perform FFTs and calculate discrete time equivalents of equations such as Eq.
2.2-2 for estimating parameters such as adjacent ACPR.
6. Perform steps 3,4 and 5 for each output power to derive the characteristic curves
The following figures are sample results from the program. Figures 2-2 and 2-3 are the
magnitude and phase of the complex compression curve of the amplifier, i.e., the function
g1 of the Eq. 2.2-1, for a particular carrier frequency.
27
Figure 2-2: Compression curve, magnitude
Figure 2-3: Compression curve, phase
28
Figure 2-4: Power gain
Figure 2-5: Sample CDMA signal magnitude
29
Figure 2-6: Undistorted input signal trajectory
Figure 2-7: Distorted output signal trajectory
30
Spectrum around carrier frequency
Figure 2-8: Spectral regrowth
Figure 2-9: Amplitude probability distribution, CCDF
31
Figure 2-10: ACPR for various power outputs
Figure 2-4 shows the calculated gain compression curve. Figure 2-5 shows a sample of
the envelope of a CDMA modulated signal. Figure 2-6 and Figure 2-7 show the signal
I&Q trajectories at the input and the output of the amplifier, respectively. The skew and
jitter introduced by the nonlinear amplifier are readily seen. Figure 2-8 shows the spectral
regrowth caused by the nonlinearity in the amplifier. Figure 2-9 demonstrates the impact
of the amplifier’s gain compression by comparing the cumulative probability distribution
function, CCDF, of the power of the output with that of the input for a CDMA modulated
signal.
Figure 2-10 contains the estimates of the left and right side ACPR for adjacent and
alternate channels of the amplifier, for various power outputs. Alternate channel ACPR is
defined the same way as the adjacent ACPR, but with a larger channel offset from the
carrier, e.g. 1.98MHz in PCS systems. There is a slight difference between right side and
left side ACPRs. This is why in Figure 2-10 we see a set of two close curves for adjacent
channels and another set of two curves for alternate channels. The primary cause for this
32
asymmetry in the spectrum is the simultaneous interaction of amplitude and phase
nonlinearities with the signal. If only amplitude or phase nonlinearities were present, the
spectrum would have been symmetric and the right and left side ACPRs should have
been the same. More on distortion sideband asymmetries can be found in [47].
Deriving the curves in Figure 2-11 using the more traditional envelope transient
simulation approach on a fast machine can easily take several hours to a few days. Using
the approach described above takes several seconds to a few minutes to derive the
compression curve of the PA using simple harmonic balance simulation and less than 10
seconds subsequently to derive all the above information including the ACPR curves.
This approach enables comprehensive exploration when designing and optimizing linear
amplifiers which wouldn’t have been possible otherwise. For example the unexpected dip
around 27dBm on the adjacent channel power ratio in Figure 2-10, was first seen using
this simulation method, and following it up permitted power amplifiers to be developed
that use this feature to enhance the efficiency. We will discuss this further in the next
section and in section 3.2.
In order to apply a simulation technique like the one above with confidence, one of the
first concerns is to seek conformance of the simulation results with measurements or
other simulation techniques. In order to compare simulation results from our ACP
program and a traditional envelope transient simulator, a reference amplifier model on
HP ADS was used to estimate ACPR at one power output. The ACPR estimates from this
program and ADS were less than 1dB apart from each other. For the reference circuit it
took ADS 12 hours to calculate that single reference data point on ACPR. Using our
approach described here it took a minute to generate the compression curves with ADS
and a few seconds for ACP to estimate ACPR versus power output, including the
reference data point.
The conformance can also be checked by comparing results from measurements on an
amplifier and the estimated ACPR curve derived from a simulation using an estimate of
the compression curve in the ACP program. That has been done many times and the
33
results usually match very well. The inherent problem with this type of verification is that
all the simulation errors and artifacts from passive and active device modeling all the way
to the modeling of the couplings in the bond wires, etc., add up and there are also errors
from measurements. These errors can mask potential inherent errors in the simulation
technique. Therefore, although the results match well, it is not a firm verification of the
program because it may very well be the effect of many errors canceling each other.
For additional verification the compression curve of an amplifier was measured in the
lab. The result was fed to the program and the estimated ACPR curves were compared
with the ones measured for the high side and low side on the same amplifier. This way all
other modeling and simulation errors are excluded and the only sources of error are in the
measurement techniques and the simulation program itself.
.
Figure 2-11: Comparison of measured and simulated ACPRs
Given the inherent high sensitivity of ACPR measurement and estimation, as noted in
Figure 2-11 the results from simulation and measurements match very well. Particularly
34
the shape of the curves is predicted very closely. Some of the known contributing sources
of error in the above experiment are:
1. Phase information is not available from simple measurements and all the phase
nonlinearity effects are neglected.
2. Power meter nonlinearity.
3. Power error in the output of the signal source.
4. Absolute error in power measurement, e.g. in the above curve due to the high
slope of the curve at powers above 27dBm just 0.2dB error in power measurement
could lead to an error of more than 1.2dB in the ACPR reading.
5. In measurement of ACPR a fluctuation of +/- 1dB is normal.
6. Different results can be obtained due to windowing effects and filter length.
7. The lookup table is usually generated by interpolating data and creating a table of
several thousand entries from a typical 30 to 60 point measurement set. This can
introduce offset caused by quantization error.
In order to get a sense of the magnitude of the errors that can be caused as noted in items
2, 3 and 7 above, a simulation was run on a linear compression curve that had a
sinusoidal fluctuation error:
y = (1 + m ⋅ sin( k ⋅ x )) ⋅ x
Eq. 2.2-3
with 100 times m being the percentage error introduced for each power.
35
Figure 2-12: Transfer characteristic with 5% fluctuation
Figure 2-13: Effect of magnitude error on ACPR
36
Figure 2-12 shows a sample compression curve for 10 percent fluctuation or +0.8dB/ 0.9dB. Figure 2-13 shows the effect on ACPR estimate for different error percentages
ranging from 0.1% to 10%. In summary this result suggests that a 5% magnitude or
equivalently 0.4dB power measurement error can in turn introduce substantial error in the
estimate of the ACPRs below -50dB. On the other hand it indicates that we should not
worry much about power measurement errors less than 0.1dB. Therefore in using the
simulation, attention should be paid to creating the compression curve and the input to
the program, with fine enough steps to avoid excessive quantization error. About 50 or
more points per curve is usually adequate.
In summary, confidence is obtained that this method for estimating the ACPR can
provide very useful results when combined with an adequate simulation of the
compression curve. This is confirmed in actual use and is predicted by the theory for
quasistatic nonlinear amplifiers.
37
2.3 Effects of the shape of the gain compression on ACPR
In this section we explore various potential scenarios for nonlinear gain compression and
discuss the resultant trends observed in the ACPR behavior. Throughout this section we
use the same CDMA modulated input signal that was used in section 2.2.
The first case, which can be considered the most intuitive one, is the case of a sharply
clipped or saturated otherwise perfectly linear amplifier with no phase or gain distortion.
Output phase (degrees)
Pout (dBm)
40
20
0
-20
-40
-60
-40
-20
0
20
200
100
0
-100
-200
20
Pin (dBm)
25
30
Pout (dBm)
27
-30
ACPR (dBc)
Gain (dB)
26
25
24
23
22
21
0
10
20
Pout (dBm)
30
40
-40
-50
Adjacent
Channels
-60
-70
Alternate
Channels
20
25
30
Pout (dBm)
Figure 2-14: Linear amplifier with sharp saturation
Figure 2-14 shows the characteristics and calculated ACPR for such a sharply clipped
amplifier. In all the following we maintain the saturation or clipping level the same at
31.6dBm output or 12volts on a 50 ohm load. Whenever the phase characteristic is not
38
shown explicitly, the phase is constant as shown in Figure 2-14.
Whenever the
magnitude or gain magnitude is not shown, it is the same as shown in Figure 2-14.
Figure 2-15: Gain and ACPR in a sharply saturated amplifier
Figure 2-15 shows the same case as Figure 2-14, but with further detail. There is a knee
in the adjacent and alternate ACPR curves at 27dBm output or equivalently at a back-off
of 4.6dB with respect to full saturated power. It is only after that point that the nonlinear
effect of clipping becomes significant. We also observe that -50dBc adjacent channel
power ratio can be obtained at a back-off of 3.2dB. A second and much sharper knee is
observed in the alternate channel power ratio at about 0.3-0.4 dB back-off. The highest
slope of the adjacent channel power ratio curve occurs at back-off levels between -3.2dB
and -1.6dB and is as high as 7dB per a 1dB change in output power.
39
In a second case, the effect of gain compression prior to saturation is explored. As shown
in Figure 2-16 for the three cases of a, d and e we observe that with increasing
compression the knee moves further down to lower power outputs, i.e. to higher back-off,
and overall the ACPR increases further in the region of compression.
Figure 2-16: Effect of gain compression on ACPR
The scenario of ACPR for an expansive gain behavior is similar to that for compressive
gain behavior as seen in Figure 2-17 for the cases of a, b and c. Figure 2-18 shows what
is expected when an expansive gain behavior is followed by a gain decrease and then
saturation thereafter.
40
Figure 2-17: Effect of gain expansion on ACPR
Figure 2-18: ACPR of an expansive/compressive gain profile
41
Figure 2-19: ACPR of a compressive/expansive gain profile
Figure 2-19 shows an alternative case with a compressive gain behavior that is followed
by a gain increase and then saturation thereafter.
The interesting observations are:
1. A local maximum of the adjacent ACPR occurs at a power level where the gain
vs. power slope is highest.
2. There is a local minimum of ACPR at around 27.5dBm where the gain behavior
switches from expansive to compressive, and the second derivative of gain vs.
Pout is therefore zero.
3. When the power output is close to saturation, clipping is the dominant nonlinear
effect that determines the ACPR.
42
Figure 2-20: Effect of gain magnitude profile on ACPR
Figure 2-21: Effect of gain magnitude profile on ACPR
43
Figure 2-22: Effect of gain magnitude profile on ACPR
Figures 2-20, 2-21 and 2-22 show three other examples. Though atypical for actual
amplifiers, they further help to provide a better sense of how the shape of the gain versus
power output can change the ACPR behavior.
Among the above scenarios, the case shown in Figure 2-18 has the most important
practical impact. We observe the local minima in ACPR curve for the first time in such
an exploratory simulation. That inspires the thought that it may be possible to have an
amplifier as a cascade of two nonlinear stages that creates the expansive/compressive
behavior by tuning the conduction angle or bias of the two stages to achieve much better
ACPR at lower currents and higher efficiencies. In chapter 3, we will discuss results of
further research along this direction. In summary this approach has led to the design of
cellular and PCS handset CDMA power amplifiers with measured efficiencies of over
40% for the first time.
So far all the cases discussed have been constant phase cases. The following cases
explore the effect of AM-PM conversion on the ACPR for a constant gain magnitude
44
sharply saturated amplifier with peak power of 31.6dBm (see Figure 2-14 gain versus
Pout curve).
As intuitively expected and shown in Figure 2-23, increased AM-PM conversion also
degrades ACPR performance. Figures 2-24 and 2-25 present additional cases that show
how AM-PM conversion can also affect the ACPR, in addition to its effect on
constellation jitter.
Figure 2-23: Effect of AM-PM on ACPR
45
Figure 2-24: ACPR of different phase profiles
Figure 2-25: ACPR in presence of large AM-PM
46
2.4 A search for optimum gain compression shapes
For all the cases discussed in the previous section, the ACPR curve shown in Figures 214 and 2-15 is a lower bound on what can be achieved for all power outputs. This
suggests that among saturated amplifiers with a fixed maximum output power level, the
best ACPR is achieved at all power outputs by a perfectly linear amplifier with abrupt
saturation at the maximum power. Although intuitively appealing, this hypothesis is not a
trivial one. For example, can ACPR resulting from the clipping of the high side of the
signal be reduced, for example, by means of some additional nonlinear distortion on the
low side of the signal? What prevents the low side distortion from creating some adjacent
channel signal components in opposite phase to the components created by the high side
so that they cancel out and lead to lower ACPR?
In order to address the above questions a random search was performed for gain
characteristics with a saturation level of 31.6dBm with the target to find a curve that
could deliver an ACPR better than that shown in Figure 2-14 for at least one power level.
No such gain characteristic was found.
Using a different approach, a MATLAB optimization code was used to search for a
compression curve vector with the constraint of saturation at 31.6dBm. In one scenario
the objective function was defined to minimize the ACPR at one specific power level.
This was tried for various power levels, with back-off levels as low as 1.5dB. Although
various compression curves were obtained with different levels of distortion away from
the target output power level, they were all close to a straight line near the target power
level and the derived minimum ACPR was the same as shown in Figure 2-14 at that
power level. In the second scenario the objective function was set to minimize the
average of ACPR for all power levels up to 31.6dBm. The resultant vector was a constant
gain with sharp saturation at 31.6dBm and the minimum obtained was the same as that of
Figure 2-14.
47
Although these observations cannot be considered as complete proof, they are practically
suggestive that among saturated amplifiers with a fixed maximum power level, the best
ACPR is achieved at all power levels by a perfectly linear amplifier with sharp saturation
at the maximum power as shown in Figure 2-14.
48
Chapter 3: PA linearization from an efficiency and complexity point of
view
Introduction
In this chapter various linearization techniques will be considered. The goal of this
exploration has been to achieve higher efficiency for linear amplifiers while maintaining
a low to modest complexity in the linearized system. As a result all the techniques are
based on using nonlinear amplifier classes in combination with control methods that
generate an overall acceptable in band and out of band linear performance for particular
applications.
In section 3.1 we revisit the envelope elimination and restoration (EER) technique with a
newer look at the envelope restoration (ER) function. Traditionally envelope restoration
is performed through modulation of the supply voltage. This chapter in contrast covers
only methods that re-inject the envelope modulation in the signal path, and usually at the
base of the output power devices. As a result the need for a fast tracking efficient power
supply, e.g. a fast tracking DC-DC converter [32], is eliminated and the power devices
themselves and the filtering function of their output matching networks play a main role
in restoring or modulating the envelope. Pulse deletion modulation (PDM), Pulse width
modulation (PWM) and bias controlled ER will be discussed in further detail.
In section 3.2 we will present one of the lowest cost and most efficient methods of
linearization based on a cascade of two self-biased nonlinear stages. As mentioned in the
previous chapter the possibility of such a solution was first predicted by the method
presented in chapter 2. This inspired further research that led to the final development of
this technique.
49
3.1 More on EER and newer ER techniques
Envelope elimination and restoration is an old technique for using nonlinear amplifiers
for amplification of modulated non-constant envelope signals [29]. The concept is that a
nonlinear amplifier can be used to amplify a signal containing the all phase information
and the magnitude or envelope information can be superimposed on the signal after the
RF amplification or in other words through a different signal path other than the main RF
amplification path. Figure 3-1 shows this general concept.
Figure 3-1: Envelope elimination and restoration
Traditional envelope elimination and restoration often referred to as the Kahn technique
[30 and 31] is based on modulating the supply voltage of the output stage of an amplifier
with the envelope signal to create a fully modulated amplified signal at the desired output
power. There are various solutions for the efficient supply modulation. Some common
approaches used in efficient tracking DC-DC converters are based on Pulse width
modulation,
delta-modulation
and
Class-S
amplification.
Two
alternative
implementations are shown in Figures 3-2 and 3-3.
50
Figure 3-2: EER using a delta modulated Class-D switching power supply [32].
Figure 3-3: Envelope and phase modulated signals generated separately by DSP [1].
Key concerns and tradeoffs in such systems are:
1. Delay between envelope and phase paths cause distortion such as jitter and
ACPR, and thus has to be maintained at an acceptably low level. This is a
common problem in EER implementations and for most of the currently used
single carrier systems can be accommodated.
2. The switching power supply output has to be filtered finely enough in order not to
introduce spurs in the output RF signal. Designing those filters without requiring
bulky external components is still an open challenge.
51
3. Amplifiers also show AM-PM behavior in response to supply voltage modulation
particularly when operated in deep saturation for higher efficiency. Therefore
some additional back off is required, at the cost of losing efficiency.
4. Linear envelope detection of modulated RF signals over a wide enough dynamic
range is extremely challenging. This favors solutions like the one in Figure 3-3
over those like the one shown in Figure 3-2. However, their implementation
requires a change to the base band chips, which poses a different set of
challenges.
5. Designers have to be particularly careful not to lose the higher efficiencies they
gain from operating the PA’s closer to saturation to the power they consume in
the limiter, envelope detectors, switching power supply and filter.
6. Size and complexity of the switching power supply reflect on the overall size and
cost of power amplifier modules in different ways depending on how the budgets
for the bill of material in the systems are allocated.
With the idea of addressing concerns mentioned in items 2, 3, 6 (and to some extent, 5) a
new alternative for the implementation of the EER systems was explored [48]. The main
concept is to eliminate the supply modulator and instead inject the envelope back through
the base or gate of the amplifier output stage and let the nonlinear amplifier stage perform
the act of combining or superimposing the envelope onto the modulation. In the
remainder of section 3.1 we explore a few alternatives for implementing the envelope
restoration function with this philosophy.
52
3.1.1 Pulse deletion modulation
Consider a periodic signal that consists of multiple pulses per period of the same
magnitude and evenly distributed over time. Let’s assume a period can consist of
maximum N pulses and in one sequence only m out of N pulses are transmitted. If we
look at the peak or envelope of the signal and average it over one period, this value will
be linearly dependent on the ratio of m over N.
mean= 0.22x (8/8)
Figure 3-4: Full power with no pulses dropped
The above Figure shows the full or saturation magnitude of the envelope, m=8 and N=8.
mean= 0.22x (6/8)
Figure 3-5: 2 out of 8 pulses dropped
mean= 0.22x (5/8)
Figure 3-6: 3 out of 8 pulses dropped
53
Figures 3-5 and 3-6 show the signal for m/N=6/8 and m/N=5/8 respectively. The question
is how this concept could be used for linear modulation or linearization of power
amplifiers?
One scenario can be a class C stage with the above pulse trains as its current waveforms.
The filters would reconstruct signals with various envelope amplitudes that are linearly
dependent on the mean of the current waveforms and as a result the reconstructed
envelope will be a linear function of the m/N or the non-dropped pulses to the total pulses
ratio. The interesting promise of the technique is that the efficiency should not degrade
much for lower powers because there would be fewer current pulses for lower powers.
The equivalent of this scenario with voltage transition pulses has promise for class D
amplifiers.
This suggests that the method could be used for linear reconstruction of the envelope at
the output of an EER system with promise of higher efficiency at lower powers.
However, like every other promising technique, this one also has issues that need to be
addressed. As a result its usage will be limited and it cannot deliver the full promise of
perfectly linear high efficiency amplification.
The first fact that cannot be overlooked is that even in the case of a perfectly linear
reconstruction of the envelope, the main source of nonlinearity would be a potential
phase modulation dependent on the amplitude of the incoming or reconstructed signal.
For cases like the one shown in Figure 3-2 this mandates difficult specifications on the
limiter circuit. Also, in the design of the output matching network of the amplifier, it
would be critical to be sure that in interaction with the power device no variable phase
shift dependent on the amplitude of the output is created. Otherwise the AM-PM
characteristic may negate all the benefits of the linear envelope reconstruction.
Another systematic artifact of this technique is the spurious emission that is created as a
result of pulse dropping. Therefore, in using this approach one ends ups trading off inband linearity with out of band spurs or out of band nonlinearity. Another artifact is the
54
jitter introduced into the constellation as a result of pulse deletion. The magnitudes of all
these effects are dependent on the signal’s amplitude relative to saturation and also the
dynamic range of the signal. In the remainder of this subsection these issues will be
discussed further.
55
3.1.1.1 In band vs. out of band linearity trade off
In order to gain a basic understanding of the spectrum trade offs to be expected in a PDM
based envelope restoration system we look at a very simple case. Let’s assume that the
output stage is a class C amplifier driven by a sequence of pulses so that the output
current pulses are generally similar to Figures 3-4, 3-5 and 3-6. The full power is
delivered when 8 out of 8 pulses are maintained. For now let’s consider that the output
matching performs a transimpedance and filtering function essentially equivalent to that
of a resonant tank circuit with a Q of 10 as shown in Figure 3-7.
Figure 3-7: Sample output filter frequency response
Let’s consider two cases as shown in Figures 3-8 and 3-9. Case a as shown in Figure 3-8
is the scenario of full power transmission. In case b, as shown in Figure 3-9, four out of
eight pulses are deleted. If the shape of the pulses does not change as a result of pulse
deletion function, as assumed in this scenario, the expected envelope magnitude out of
56
case b should be exactly half of that of case a, or the power should be 6dB lower for the
main carrier.
mean= 0.22x (8/8)
(5/8)
case a
Figure 3-8: Case a
mean= 0.22x (4/8)
(5/8)
case b
Figure 3-9: Case b
Figure 3-10: Spectrum of the signals for cases a and b
Figure 3-10 shows the spectrum of the output of the filter for the two cases and in fact
confirms that carrier signal level at b is exactly 6 dB below that of case a. Of course this
exactly linear relationship only holds true when the pulse shapes are the same for the two
57
cases. In practice maintaining the pulse shape becomes challenging if a large percentage
of the pulses has to be deleted at the carrier rate.
Figure 3-11: PDM output spectrum
Figure 3-11 shows the spectrum of the filtered output normalized with respect to the
carrier frequency component. This shows that in the ideal case where pulse shapes are not
affected, the harmonic content of the amplifier output should not change for various
amplitudes. However, the pulse deletion function introduces spurious emission.
In this example, since the full signal cycle is 8 carrier cycles, spurs occur at subharmonics
at multiples of one-eighth of the carrier frequency. In general, however, these spurs need
not be subharmonics of the carrier and this varies with the implementation method. If a
fixed code size look-up table approach is adopted for implementation, spurs will always
be at subharmonics. On the other hand, when the delta-sigma approach is adopted there
will not be a fixed code size and therefore spurs can move around as a function of the
amplitude. For fixed output amplitude in a delta-sigma based implementation without
addition of dither or randomization signal, this cyclic behavior recurs and spurs will be
58
created at subharmonics. Later on in this chapter we will briefly discuss various potential
implementation schemes.
Obviously if a narrower band or higher order filter is used with higher out of band
rejection overall spurious emission will be reduced further. An example is shown in
Figure 3-12 for the same pulse sequence as case a with a different filter.
Figure 3-12: Output spectrum with better filtering
We observe that, using PDM, theoretically perfect in-band envelope or amplitude
linearity can be achieved at the cost of generating spurs out of band. In-band nonlinearity
may be seen in practical PDM based systems because the RF pulse shape may not remain
constant when the PDM is applied or due to nonlinear phase behavior.
The out of band spur level is a function of the filter shape as well as the pulse deletion
rates, average cycle length and modulation depth and shape. The frequency at which
spurs are maximized is also a function of the modulation type, filter shape and pulse
deletion rate. Needless to say, the pulse deletion rate itself has to be determined based on
the desired amplitude in order to reconstruct the right average amplitude at the output.
59
3.1.1.2 Signal and modulation dynamic range effects
As mentioned in the previous subsection, an inherent characteristic of the PDM technique
is that it generates out of band spurs. In this section we will take a closer look at the
relative magnitude of the spurs generated for various output powers.
Figure 3-13: Impact pulse dropping ratio on spectrum
Figures 3-13 and 3-14 show the normalized spectrum of the output of an idealized PDM
modulated class C amplifier for various pulse deletion rates ranging from no deletion in
case a to deletion of 7 out of 8 pulses in case h. The observation suggests that the relative
spur levels in dBc go up as the pulse deletion ratio increases. The total dynamic range
explored in this case is 18dB, i.e. the output power level in case h is 18dB lower than in
case a.
60
Figure 3-14: Impact pulse dropping ratio on spectrum
As briefly mentioned before for fixed code size scenarios like the ones shown in the
previous subsection and in Figures 3-13 and 3-14 the relative harmonic content is not
changed for various power levels. All the harmonics of the carrier are exact linear
functions of the output magnitude and pulse deletion rate. The upper bound for both
harmonic content and sub harmonic spurs is primarily determined by the output filter.
Figure 3-15 shows the four closest spurs to the carrier. Due to lower rejection of the filter
at these frequencies these spurs show up as the strongest. It is more clearly seen that the
spur level in dBc goes up for lower powers produced by a higher pulse deletion ratio.
61
Figure 3-15: Spur levels with PDM based power level adjustment
In Figure 3-15 expected spur levels are shown for various nonmodulated output powers
when the PDM technique with a code size of 8 is used for power level adjustment. Back
off here means relative power level in dB with respect to the peak power. When an
envelope modulation is applied the spur levels are usually better than predicted for the
lowest power level in the modulation and worse than predicted for the highest power.
62
Figure 3-16: AM modulation with PDM
Figure 3-17: AM modulation with PDM
Figure 3-18: AM modulation with PDM
Figure 3-19: AM modulation with PDM
Figure 3-20: AM modulation with PDM
Figure 3-21: AM modulation with PDM
63
Figures 3-16 to 3-21 show the expected pulse sequence and the spectrum of the output
filtered by the typical filter shown in Figure 3-7 for an AM modulation with modulation
index of m=0.9. In this case the assumption is that pulses are either included in full or
deleted in full. The simulation was performed based on a sigma-delta envelope
modulation implementation technique that is discussed later in this chapter. For
generating this sequence of full pulses the sigma-delta modulator clock has to be set at
the same frequency and in synchronization with carrier. Figures 3-16, 3-18 and 3-20
show the current pulse sequence of an ideal class C amplifier and the desired envelope in
time domain. Figures 3-17, 3-19 and 3-21 show the spectrum of the filtered output. As is
seen in Figure 3-21 close in spurs, or harmonics of the envelope can be pushed down
easily and this in band linearity is achieved at the cost of out of band spurs.
The dynamic range of a signal can be looked upon in two ways. For a modulated signal
with fixed average power like the one shown in Figures 3-16 to 3-21, the peak to
minimum of 19dB can be used as an indicator of the modulation dynamic range at a fixed
average power. In a power controlled system, however, the average power of the
transmitted signal can vary substantially over a large transmit power dynamic range.
From the above discussion we conclude that the PDM method can reasonably handle
high average power signals with large modulation dynamic range but produces excessive
spurs at lower average power outputs in cases with large transmit power dynamic range.
In summary, the operable dynamic range of PDM systems is dictated by the feasible filter
rejections and tolerable spur level. These requirements severely limit the potential
applications of this approach, as most RF systems have tight spurious emission
specifications.
64
3.1.1.3 Jitter in the signal constellations
In considering potential artifacts of the pulse deletion method as described, one of the
first questions that comes to mind is whether the pulse deletion process introduces jitter,
i.e. timing or phase error, in the modulated signals and if so what are the related tradeoffs.
A simulation was performed for a hypothetical system with a carrier frequency of
250MHz and a 977 kilo-samples per second
π
4
QPSK modulated data stream.
Figure 3-22: Digital modulation with PDM
Figure 3-23: Digital modulation with PDM
Figure 3-24: Filtered output tracks input
Figure 3-25: Digital modulation with PDM
Figures 3-22 represents the PDM based modulated output in time domain. Figures 3-23
and 3-25 show the spectrum of the said output signal. The input to the system is a square
65
root raised cosine filtered
π
4
QPSK modulated data stream. Figure 3-24 shows the input
when filtered by a second square root raised cosine filter and superimposed on the output
of the system down converted to base-band and filtered by the same kind of filter. As
shown in Figure 3-24 the base-band spectrum is preserved very well.
Figure 3-26: I-Q trajectory
Figure 3-27: I-Q trajectory
Figure 3-28: Signal constellation
Figure 3-29: Signal constellation
Figures 3-26 and 3-27 show the I-Q trajectories for the input and output respectively.
Figures 3-28 and 3-29 show the signal constellation for the input and output. The input
and output match well. Therefore the proposed system theoretically is capable of
restoring the envelope with only small channel artifacts. In detecting the constellation the
assumption is that the clock and carrier frequencies are recovered perfectly and without
66
error and the timing recovery circuit successfully works to produce the lowest achievable
jitter.
Output
Input
Figure 3-30: PDM induced jitter
Figure 3-30 shows the spread of the phase error in degrees over several symbols for the
constellations shown in Figures 3-28 and 3-29. The dots correspond to the output
generated through PDM of Figure 3-29 and the solid line is that of the input.
For this particular modulation Figure 3-31 shows the relationship of the phase error
caused by timing errors with the corresponding timing error. It suggests that the mean
error of 0.11 degrees observed in this case is equivalent to the jitter caused by a 3 to
4nsec average timing jitter. Knowing the fact that in this system the carrier pulse duration
is 4nsec, it triggers another question. Is there any relationship between pulse duration and
the timing or phase jitter in such PDM systems?
67
Figure 3-31: Time/phase jitter for the modulation
Figures 3-32 and 3-34 show the constellation and jitter for a hypothetical system that has
carrier and maximum pulse deletion frequency that are 64 times the symbol rate or
oversampling ratio (OSR)=64. Figures 3-33 and 3-35 show the data for another case with
OSR=16. It appears that at lower carrier to envelope ratios or OSRs more jitter is
introduced by the pulse deletion function in PDM systems, as shown in Figure 3-36.
A potentially simpler descriptive relationship between jitter and pulse deletion rates is
suggested by the relationship between time and phase errors for the kind of modulation
discussed. A simple hypothesis is that the jitter in the pulse deletion schemes may be
introduced only by the pulse deletion function itself. If the jitter can all be attributed to a
timing error on the order of the duration of a deleted carrier pulse or a multiple of it
within same order of magnitude, then we could expect:
f symbol Tcarrier
∆Terror
≈
=
Eq. 3.1-1
Tsymbol
fc
Tsymbol
68
Figure 3-32: Output constellation for OSR=64
Figure 3-33: Output constellation for OSR=16
69
Figure 3-34: PDM jitter for OSR=64
Figure 3-35: PDM jitter for OSR=16
70
Figure 3-36: Phase jitter for various carrier/modulation frequencies
Figure 3-37: Modulation timing curve
Figure 3-38: Modulation timing curve
Then Figure 3-37 that shows the relationship between timing error and phase jitter for the
π / 4 QPSK modulation is useful for obtaining a rough estimate of the phase jitter
resulting from pulse deletion in such a PDM system.
71
Figure 3-39 further illustrates this idea. The data points correspond to the simulated phase
errors shown in Figure 3-36 and the solid lines represent the estimated phase error using
Eq.5.1-1 and Figure 3-37. As observed, phase jitter in the PDM systems can quickly be
estimated by looking up the phase error in Figures 3-37 and 3-38 for a timing error equal
to the ratio of modulation over the carrier frequency, f symbol / f c . Such estimates are
particularly more precise for larger ratios. Equivalent phase vs. timing error data such as
the one shown in Figures 3-37 and 3-38 is usually available for standard modulation
schemes and is independent of tradeoffs of the PDM method.
Figure 3-39: Simulation vs. fast estimates on phase jitter
It is important to remember that in this section only the jitter directly resulting from the
pulse deletion process in PDM systems was discussed. Any saturation or clipping effect,
envelope nonlinearity, AM-PM conversion or delay difference between envelope and
carrier signal paths are other factors that can cause additional jitter-like artifacts to appear
in the output signal of a PDM amplifier system.
72
3.1.1.4 Implementation methods for classes C and D amplifiers
An implementation of the PDM based on a Class C output stage is illustrated in Figure 340. The current pulses of the output device ideally will be similar to those shown in
Figures 3-4 to 3-6.
VDD
Envelope
in
Constant Envelope
RFin
PDM Pulse
Generator &
Bias Control
Class C PA
RL
Driver Stages
Figure 3-40: PDM on Class C amplifier
Drain efficiency for a Class C PDM modulated stage is
η=
Pout
Pout
=
PTotal Vcc ⋅ I average
Eq. 3.1-2
The highest efficiency η max is obtained when there is no pulse dropping as in Figure 3-4.
Since
2
Pout ∝ I ave ∝ ( N undeleted ) 2
Eq. 3.1-3
73
where N undeleted is the number of undeleted pulses per second, we have
P
I
Pout
N undeleted
η
= out ⋅ ave max =
=
η max Pout max I average
Pout max N undeleted + N deleted
Eq. 3.1-4
which shows that the efficiency versus power output rolls off as the square root of power
and is linearly dependent on the ratio of undeleted pulses to the total possible pulses. For
comparison, in a Class A amplifier, efficiency rolls off as a linear function of the power.
Also, the maximum efficiency can be as high as 60-70% (theoretically 100%, but at
essentially zero output) in Class C, while in Class A the peak theoretical efficiency is
50%. Thus, there is a promise of increasing the peak and average drain efficiency
substantially if the combination of PDM with a Class C output stage is used. The side
issues however are:
1. The preceding efficiency estimates are valid only as long as the output stage
current pulse shape remains constant. In reality it changes as a result of pulse
deletion. Although this is a secondary effect at low carrier frequencies, it can
become the dominant mechanism in degrading the efficiency at GHz-range carrier
frequencies.
2. The power consumed by the PDM pulse generator and bias control circuit may
offset a good portion of the power added efficiency improvement arising from
increasing the drain efficiency of the output stage. For implementing a complete
pulse deletion scheme the bias driver of this circuit has to switch the output stage
on and off at the carrier frequency. Given the big size of the output device, the
solution may prove ineffective by requiring excessive power to perform the
switching function. As a compromise we can decouple the pulse deletion rate
from the carrier frequency and eliminate the need for synchronous high speed
switching of the carrier. However, this may lead to truncated current pulses in the
amplifier which in return degrades the efficiency and linearity of the whole
system.
3. Given the current size and cost trends in GaAs handset power amplifier modules,
the addition of the PDM unit would be considered excessively expensive.
74
However if the PA integration into CMOS transceivers really becomes the trend
in the future it opens up the way for implementation of equivalent systems.
PDM can also be used to linearize Class D and Class F amplifiers. Figure 3-41 shows a
general sketch for a Class D amplifier modulated by PDM.
Envelope in
Constant Envelope
RFin
PDM
Pulse
Generator
&
Bias
Control
M1
VDD
RL
M2
Driver Stages
Figure 3-41: PDM on Class D amplifier
Figure 3-42: Waveforms at full power
Figure 3-43: Waveforms at 6dB back off
Figure 3-42 shows the current and voltage waveforms of the two transistors M1 and M2
and the output current waveform at full power. Figure 3-43 shows the same signals when
a back off of 6dB is applied through PDM.
The theoretical limits for efficiencies of Class D and Class F implementations are 100%.
Even at lower powers, i.e. higher pulse deletion rates, the current and voltage signals of
the devices theoretically do not have any time overlap. Therefore drain efficiency
remains at 100% with the assumption of pulse shapes not changing as a result of PDM. In
75
practical cases inevitably there are switching or nonlinear losses as well as passive
component losses. The losses in the passive components scale linearly with power output.
PLinear.Loss ∝ Pout
Eq. 3.1-5
The switching losses are more complex. The switching loss is the integral of the product
of the current and voltage waveforms of devices over the overlap time of the two
waveforms. If the pulse shapes of the current and voltage do not change as a result of
PDM, then the net effect of the PDM is the scaling of the current pulse magnitude. The
switching loss at each cycle then has voltage pulses that scale linearly with the current
magnitude, i.e., with square root of output power. The average switching loss is also
scaled linearly with the pulse transmission rate, which itself is proportional to square root
of output power.
E Loss.Per. Pulse ∝ I out ∝ Pout
Eq. 3.1-6
N Pulses. Per.Second ∝ I out ∝ Pout
Eq. 3.1-7
PSwitching.Loss ∝ N Pulses.Per.Second ⋅ E Loss.Per.Pulse ∝ Pout
Eq. 3.1-8
Therefore we have
PTotal .Loss = PLinear.Loss + PSwitching.Loss ∝ Pout
Eq. 3.1-9
and hence for drain efficiency we have
η=
Pout
Pout
=
= η max = Const. Eq. 3.1-10
PTotal Pout + PTotal.Loss
The above relation points to an extremely attractive potential, the promise of maintaining
the high efficiency of Class D or Class F power amplifiers over a range of power output
76
while amplifying modulated signals that require linear amplification. However, at high
carrier frequencies and high deletion rates the pulse shapes are affected by the PDM and
further degradation in the efficiency is expected for lower power outputs.
We cannot forget that even in these scenarios a back-off is required from the peak
amplifier power output to eliminate the clipping effects that were discussed in Chapter 2.
Figure 3-44: Normalized efficiency for PDM and Class A
Figure 3-44 shows the normalized efficiency roll off curves for the cases discussed in this
section. In summary, the theoretical maximum efficiency for the Class C and Class D
PDM is 100%, where for Class A it is 50%. At a back-off of 3.6dB we see from
Figure 3-44 a normalized efficiency of 0.66 for Class A, 0.82 for Class C PDM and 1 for
Classes D and F. This means a maximum theoretical linear (i.e., ACPR better than
-50dBc) drain efficiency of 33%, 82% and 100% for Class A, Class C and Class D or F,
respectively, at 3.6dB back-off.
77
At 1.8GHz, even considering a practically achievable peak efficiency of 55% for class C
and Class D, linear drain efficiencies of 45% and 55% may be achievable for Class C and
Class D/F, respectively. There will be substantial loss of power added efficiency due to
the power consumed in the PDM circuitry at these frequencies, however. This
substantially reduces the potential attractiveness of the PDM solution for GHz
frequencies.
In the remainder of section 3.1.1 we will briefly look at a number of potential approaches
for implementing the PDM pulse generator shown in Figures 3-40 and 3-41.
78
3.1.1.4.1 Feedback methods
So far we have considered various effects in the PDM based amplifier systems assuming
the availability of the needed pulse sequence. However we have not yet suggested how
the PDM pulse sequence is generated. If we can have output envelope feedback in the
system, the most intuitive approach would be to sample the output envelope and compare
it with the desired envelope. When the output envelope is smaller than the desired one,
the system should switch on and allow the RF pulses to go through. When the output
magnitude exceeds the desired envelope the system needs to switch off and not allow the
RF pulses to go through. This was in fact the first methodology we used to generate and
simulate potential PDM effects.
Bias Circuit
Constant Envelope
RFin
Driver Stages
Envelope in
+
Envelope
Detector
Coupler
Switch
-
PA
Output Stage
Load
Comparator
Attenuation
Figure 3-45: Asynchronous envelope delta modulation
Figure 3-45 shows the general concept of such an implementation. Asynchronous
envelope delta modulation based PDM can be a reasonable descriptive name for the
function performed here. An alternative to the above implementation can be the
synchronous version of the above which by controlling the switching time and
synchronizing it with the timing of the carrier pulses assures that full RF pulses go
through as shown in Figure 3-46.
79
Bias Circuit
Constant Envelope
RFin
Driver Stages
CLK
Envelope
Coupler
Switch
out
PA
Output Stage
Load
FF
in
+
in
Envelope
Detector
-
Comparator
Attenuation
Figure 3-46: Synchronous envelope delta modulation
Previously we noted that in order to suppress the out of band spurs they should be pushed
further away from the carrier which means that higher switching rates are more desirable
for the pulse deletion. In the feedback implementations, the actual switching rate is
mainly determined by the bandwidth of the feedback loop which, in turn, is limited by the
bandwidth of the envelope detector and the speed of the comparator in the presence of
offsets. The feedback loop bandwidth also directly affects the jitter introduced in the
signal. The higher the bandwidth, the lower the jitter would be.
Design of linear RF signal envelope detectors with large enough dynamic range is a
challenging task by itself. One of the additional requirements for the envelope detectors
shown in Figures 3-45 and 3-46 is that their detection bandwidth has to be sufficiently
larger than the envelope frequency and the loop gain bandwidth of the system to yield
good in-band linearity and stability. On the other hand, wide bandwidth in the envelope
detector allows all harmonics and spurious signals to pass. This causes a degradation of
the envelope detector linearity. A wideband envelope detector also passes too much
80
extraneous signal fluctuation into the comparator which is translated into a time-varying
modulation-dependent offset in the comparator. This shows up in the output as extra
spurious signals that can also appear to be extra out of band nonlinearity. A bandwidth
close to the geometric mean of the envelope and carrier frequencies seems to deliver
more reasonable results based on the simulations. We will discuss issues of envelope
detectors and loop bandwidth in some further detail in sections 3.1.3.3 and 3.1.3.4.
The main problem of all these feedback based implementations is the coupling of too
many otherwise unrelated system tradeoffs, e.g., in-band and out-of-band nonlinearity,
the bandwidth of the envelope detector, the speed of the comparator and the ratio of
carrier to envelope frequency. These are enough to suggest looking for an alternative that
eliminates the feedback.
81
3.1.1.4.2 Other methods
We shall not forget that the main promise of the PDM technique as we noted in section
3.1.1.1 is its promise to deliver perfect in-band linear behavior so long as the right pulse
sequence is fed into the amplifier and the pulse shapes are not affected by the pulse
deletion. Feedback is not necessary to accomplish this. Therefore if the appropriate pulse
sequence can be generated without feedback from the amplifier output, the system will be
feedback free and the limitations mentioned in the previous section go away, including
the need for an RF coupler and a linear wideband envelope detector.
One potentially effective approach could be to use a lookup table to maintain the
appropriate pulse sequence, i.e., codes with preferably fixed length, for various desired
envelope amplitudes. These code sets could be optimized to minimize out of band
spurious or in-band quantization noise. The quantization noise will be introduced because
the system will act as a digital to analog envelope converter with a finite number of levels
or code words. Such an implementation is shown in Figure 3-47.
Bias Circuit
Constant Envelope
RFin
Switch
Driver Stages
CLK
Frequency
Divider
Shift
Register's
CLK
1/N
CLK
Digital
Envelope in
MxN
Memory
1
2
Lookup
Table
N
N
PA Output Stage
out
Load
FF
in
1
2
N
Register
Figure 3-47: Lookup table based synchronous PDM
82
Looking back at the main characteristic switching signal that is used to create the PDM
pulse sequence, we realize that it’s a sequence of pulses that at any time has its windowed
average tracking the modulation signal. So what we need to create is a sequence of pulses
that maintains this feature. Sigma-delta modulation provides exactly the same
characteristic [49]. So an alternative for the implementation shown in Figure 3-47 could
be a system that has a sigma-delta modulator replacing the lookup table as shown in
Figure 3-48.
Bias Circuit
Constant Envelope
RFin
Switch
Driver Stages
CLK
PA Output Stage
out
Load
FF
in
CLK
Envelope in
Σ
1
s
Quantizer
First Order Sigma-Delta Converter
Figure 3-48: Synchronous PDM using envelope sigma-delta
Figure 3-48 shows a potential implementation of a synchronous PDM system based on
envelope sigma-delta modulation. In fact, the same model was used to simulate and
generate the modulated signals previously used in this chapter for analysis purposes.
The output signal spectrum around the carrier is the convolution of the spectra of the
sigma-delta modulator output and that of the constant envelope phase modulated carrier.
As a result all the available knowledge about close-in and spurious emission in sigmadelta modulators can readily be used in estimating the spectrum of the output of such
PDM systems. Higher order sigma-delta modulators can also be used. As a result of their
83
noise shaping behavior, they yield better in-band linearity at the cost of more out of band
spurs.
Although in the example of Figure 3-48 the clock of the sigma-delta modulator is
assumed to be in synchronization with the carrier pulses, this synchronization it is not a
necessary condition. In fact the sampling clock of the sigma delta modulator can be a
fraction of the carrier frequency in alternative synchronous implementations, or it can be
a totally uncorrelated clock at a different frequency in asynchronous implementations.
Synchronous and asynchronous applications of sigma-delta modulators in PDM systems
have been described in [48]. Potential for synchronous application of band-pass sigmadelta modulators in the transmitters has also been mentioned in [28 and 50]. Sigma-delta
modulators have been suggested as supply modulators in traditional EER as well [51].
The primary drawback of the asynchronous implementations is that partially deleted
pulses will be created. That affects the phase relationship between current and voltage in
the power device and, by increasing the unwanted overlap, degrades the efficiency. Since
the percentage of the distorted pulse shapes will depend on the output power, the
dependency of the efficiency on the output power will also slightly change from the
predictions made earlier in this section. Unfortunately, we still do not have an analytical
derivation of the efficiency in such cases and so it has to be simulated case by case.
Partial pulse deletion also leads to increased spurious around the harmonics of the carrier.
The primary drawback of the synchronous versions on the other hand is the extra
complexity as well as the challenges of running the sigma-delta modulator at carrier
frequency or dividing the carrier and synchronizing the switch to operate in synchronism
with both the carrier and the sampling clock.
84
3.1.1.4.3 Synchronous vs. asynchronous PDM
In our analysis of spurious and jitter in PDM systems so far, the assumption has been that
the pulses are either fully deleted or fully transmitted, which is valid for true synchronous
implementations. In discussion of the implementation methods it was seen that
asynchronous approaches may also be used and they may be more desired from
complexity point of view. It is therefore important to have a sense of the level of artifacts
created in the signal and the related tradeoffs in such asynchronous implementations. In
this section we will briefly look at spurious and jitter in asynchronous PDM systems.
Simulations were performed on the same platform used for section 3.1.1.3. The platform
consists of a MATLAB flow that generates the time samples of the phase modulated
carrier and the envelope signal. The envelope of the signal is fed to a sigma-delta
modulator. The time samples of the output of the sigma delta modulator are multiplied by
the time samples of the phase modulated carrier to generate a PDM sequence. The
sequence is subsequently fed into a behavioral model of the power amplifier and its
output filter. For simulating asynchronous PDM, the clock frequency and the sampling
times were not synchronized with the timing of the carrier pulses. The modulation,
carrier frequency, and output filter were kept the same as in section 3.1.1.3. The clock
frequency of the envelop sigma-delta modulator was changed, however, to obtain results
for various oversampling ratios.
As seen in Figure 3-49 the maximum spurious level goes down as the oversampling ratio
increases, because the spurs are pushed further away from the carrier frequency as the
oversampling ratio increases. This can be seen in Figure 3-50. As a result the spurs are
filtered more effectively by the PA output filter.
85
Figure 3-49: Magnitude of spurious in asynchronous PDM
Figure 3-50: Frequency of spurious in asynchronous PDM
86
The jitter introduced in the signal constellation is another factor to be considered.
As observed in Figure 3-51 the phase error decreases for higher oversampling ratios.
Comparing the synchronous and asynchronous cases for the same carrier and envelope
frequency for an oversampling ratio of 256, Figure 3-35 and Figure 3-51 show that the
phase error in the asynchronous case is higher than the synchronous version by only
about 30%. However Figure 3-51 suggests that the phase error remains reasonably small
for all oversampling ratios. Therefore the primary criterion in selection of the rates in
asynchronous PDM systems should be the spurious emission.
Figure 3-51: Constellation jitter in asynchronous PDM
87
3.1.2 Pulse width modulation
The biggest problem of the PDM method at high frequencies is the spurious emission that
cannot be filtered effectively due to lack of small low loss filters with narrow enough
bandwidth. In search for alternatives, one can think of a pulsed system that can modulate
the output by adjusting the pulse width. The goal, as before, is to maintain higher
efficiencies and to modulate the envelope.
VDD
Envelope in
Constant Envelope
RFin
PWM
Duty Cycle
Modulator
λ
4
@ fc
RL
Class F PA
Driver Stages
Figure 3-52: Modulating Class F amplifier with PWM
One way of doing so is to modulate the switching duty cycle of the output device in a
Class F power amplifier, as indicated in Figure 3-52. The output magnitude or envelope
is theoretically governed by the following relationship.
sout = Pout = sout .Max ⋅ sin(π ⋅ dutycycle)
Eq. 3.1-11
88
Figure 3-53: Magnitude vs. duty cycle in PWM
Since the behavior predicted by Eq. 3.1-11 is not linear, as also seen in Figure 3-53, some
additional envelope linearization may be required. Envelope feedback or envelope predistortion may be applied.
Figure 3-54: Waveforms in a PWM Class F amplifier
The nice feature of no overlap between voltage and current in the device in the Class F is
maintained for all duty cycles. This is seen, for example, for a 15% duty cycle sequence
89
in Figure 3-54. Therefore, theoretically the efficiency can be maintained constant at its
peak for all power levels.
Figure 3-55: PWM only creates narrow band harmonics
As seen in Figure 3-55 for an example PWM based system with a carrier frequency of
1GHz, in contrast to PDM techniques, this approach does not inherently generate out of
band spurs. It only creates narrow band modulated harmonics.
The practical issues that limit the effective usage of this approach for GHz range
amplifiers in the order of their importance are:
1. The need for generation or modulation of the duty cycle of very narrow pulses. As
an example, for a system with only 16dB dynamic range, duty cycles as low as
5% need to be handled. In a 1.8GHz system that means pulse width modulation
needs to be done on pulses as short as 27 picoseconds. Currently no simple
economical solution is available to perform this task.
2. The need for envelope feedback or envelope pre-distortion to linearize the PWM
behavior imposes the need for additional undesired complexity.
3. In practice the efficiency of the PWM modulated Class F amplifier does not
remain high at low power since due to the short pulse cycle, the device voltage
90
waveform does not maintain a rectangular pulse shape. In fact, at high enough
power at GHz frequencies the voltage waveform is not rectangular for any pulse
width. Therefore, the efficiency advantage simply disappears.
A good practical application for this technique may be found in low to medium power HF
transmitters. PWM has also been used in audio power amplifiers [52]. An alternative use
for PWM has been suggested in DC-DC converters used for modulating voltage supply
of power amplifiers in EER systems [53]. In general, however, from the in-band
nonlinearity point of view, PWM is not a good approach when high dynamic range is
required because distortion free modulation of the duty cycle over a wide range is not
easily achieved.
91
3.1.3 Pulse width and amplitude modulation (PW&AM)
In discussion of the PWM based solutions, we noted that adjusting output power level by
tuning pulse width yields reasonable expectation of producing good efficiency over a
range of power levels, but we could not offer a simple and practically viable technique
that can perform the pulse width modulation for large enough dynamic ranges at GHz
carrier frequencies. That triggers a search for a simpler approximation of PWM.
Dynamic bias control is an old concept suggested for Class A amplifiers [54 and 55]. We
also know that in a Class C stage the conduction angle is set by the bias level of the stage.
Therefore adjusting the bias level in a Class C stage could be the simplest way to adjust
the RF pulse width. The beauty of it is that no high frequency or high speed functional
block is required other than the device itself. PWM implementation could not be any
simpler than that. Since every device has a turn on threshold, the conduction angle of the
amplifier changes by adjusting the quiescent voltage level for the same RF input level, as
shown in Figure 3-56.
VDD
Envelope Control
in
Bias Control
Class C PA
Constant Envelope
RFin
RL
vg
Driver Stages
id
Vth
Figure 3-56: PW&AM on a Class C amplifier
92
This is a very simple approximate implementation for PWM. However, in Class C, PWM
implementation efficiency decreases faster than in Class-F.
In this particular
implementation shown in Figure 3-56, which can be called pulse width and amplitude
modulation or PW&AM, not only the conduction angle but also the current pulse
amplitude is adjusted. The drain efficiency will be
(i fund / i fund . max ) 2 .Po. max
(i fund / i fund . max ) 2
Po
η=
=
= η max .
PDiss.
(idc / idc. max ).PDiss. max
(idc / idc. max )
Eq. 3.1-12
in which
i fund =
idc =
imax
⋅ (2ϕ − sin 2ϕ ) ∝ Pout
2π (1 − cosϕ )
imax
⋅ (sin ϕ − ϕ cosϕ )
π (1 − cosϕ )
Eq. 3.1-13
Eq. 3.1-14
where imax is the peak current value in the device’s current waveform and 2ϕ is the
conduction angle of the device. Equations 3.1-13 and 3.1-14 show the relationship
between the fundamental frequency component of the current and dc current in Class C
amplifiers with respect to the peak of the current pulses and the conduction angle. In the
amplifier shown in Figure 3-56, the peak current and conduction angles are changing as a
result of the bias control. The highest conduction angles and highest peak currents
simultaneously occur when transmitting the highest power.
In order to predict the efficiency roll off behavior, in addition to the equations 3.1-12 to
3.1-14 the relationship between peak current and conduction angle must be known. This
depends on the pulse shape at the base or gate of the transistor and the device’s nonlinear
transconductance. In order to obtain a rough estimate of the efficiency roll off behavior
for such systems, we make the assumption that the gate voltage signal is sinusoidal and
93
the device has a sharp turn on threshold. Three sample transconductance profiles of
exponential, square-law and linear have been used to allow investigating the sensitivity to
device behavior for bipolar as well as long and short channel CMOS devices.
Figure 3-57: PW&AM efficiency for various maximum conduction angles
Figure 3-57 shows the efficiency roll off curves in PW&AM operation with linear
transconductance and turn on threshold and compares it with a classical Class A amplifier
as well as a PDM modulated Class C with 30% (108 degrees) conduction angle. In this
section we use a percentage scale in presenting conduction angles, e.g. 100% refers to
360 degrees conduction. In PW&AM maximum conduction angle is used at the highest
power output. Maximum conduction angle can be set by design. This suggests that
although the PW&AM method cannot achieve the theoretically expected efficiencies of
PDM and PWM, it promises substantial efficiency improvement compared to more
traditional linear solutions such as Class A amplifiers. When maximum conduction per
cycle is maintained below 50%, it guarantees Class C operation at all power outputs and
therefore efficiency is better than Class B or Class AB. When maximum conduction per
94
cycle is higher than 50%, the amplifier’s class of operation can shift from Class C at
lower power outputs to Class B or Class AB at higher power outputs. By evaluating the
efficiency for various profiles of conduction angles versus current magnitudes, figures 358 to 3-63 further illustrate the tradeoffs seen in PW&AM operation.
From the figures 3-58 to 3-63 it is noted that profiles with lower conduction angles
deliver higher efficiencies. When the peak conduction angles are smaller not only the
efficiency is higher, but also the efficiency roll-off curves are less sensitive to the device
nonlinearity shape. As seen in Figure 3-63, when the peak conduction angle becomes
100%, the efficiency roll-off curve is quite sensitive to the device behavior. For example,
at 4dB back-off, the efficiency ranges from 33% for the lower curve, to 47% for the
higher curve. Therefore, the accuracy of any simulation of the efficiency will be very
heavily dependent on the accuracy of the models for devices, as well as for matching
networks. On the other hand, when the peak conduction angle is maintained below 50%
(180 degrees) the predicted efficiency roll-off behavior is much less dependent on the
device characteristics. The peak efficiency itself, however, is heavily dependent on
device parasitics as well as on other losses in the system.
Although the lower peak conduction angles are more desirable from the efficiency and
sensitivity points of view, the lower gain and the need for negative supply voltage to bias
the device to allow low conduction angles are significant limiting factors. The major
limiting issue with the PW&AM technique noted so far is this need for negative supply
voltage. Without a negative supply, achieving conduction angles less than 50% (180
degrees) is not easy and controllability is very limited. However, generating an additional
negative supply voltage in cheap solutions like cell phone handsets is so undesirable that
it has already caused the handset PA industry to shift from MESFET technology to GaAs
HBTs.
95
Figure 3-58: 30% conduction angle profile
Figure 3-59: Efficiency for the 30% conduction angle profile
96
Figure 3-60: 50% conduction angle profile
Figure 3-61: Efficiency for the 50% conduction angle profile
97
Figure 3-62: 100% conduction angle profile
Figure 3-63: Efficiency for the 100% conduction angle profile
98
Another important point is that the transfer characteristic from the gate bias to output
envelope is nonlinear, as seen in Figure 3-64 for the example device. Therefore, for
systems intended for linear applications, there is a need for a scheme to linearize the
overall transfer characteristic from the desired envelope input to the envelope of the
output. Also, if the output device and the matching network are not carefully designed to
minimize the AM-PM effects it would be necessary to compensate for those effects as
well. We will discuss more about the AM-PM later in this chapter.
Figure 3-64: Output magnitude as a nonlinear function of base bias
99
3.1.3.1 EER with envelope feedback through bias control
As we noted in the previous section, PW&AM offers the promising potential for
providing better efficiency roll-off over power changes at the cost of very little additional
complexity in the bias circuit of the output device in an amplifier. This is in fact even
more promising for the systems deploying nonlinear modulations with power control. In
linear systems, however, there is an additional need for linearizing the overall
characteristic so that the restored output envelope remains a linear function of the desired
input envelope.
VDD
Class C PA
Constant Envelope
RFin
vg
Coupler
RL
Driver Stages
Bias Control
Envelope
Control
Envelope
in
Envelope
Detector/
Pre-distorter
Envelope
Detector
+
-
Error
Signal
Integrator
Attenuation
Figure 3-65: EER with envelope feedback through bias control
100
Figure 3-65 shows a scheme based on envelope feedback that can be used to linearize a
PW&AM based amplifier. The envelope feedback and error integration assures that, as
long as the feedback loop is stable and the loop gain is high enough, the output envelope
tracks the desired envelope of the signal.
101
3.1.3.2 Bias controlled envelope feedback without envelope elimination
In the traditional EER method, envelope elimination is recommended to avoid or
minimize AM-PM conversion. Since a constant envelope signal is fed to the gate, phase
variation occurs only due to supply voltage modulation.
Phase response in most
traditional amplifiers changes as a function of supply voltage and is most sensitive when
the amplifiers are pushed very deeply into compression. In the approach we propose for
PW&AM, the phase response is dependent on base or gate bias and therefore some
AM-PM conversion is expected as well. If specific care is not taken to avoid this design
problem in both approaches, AM-PM can become a main limiting factor in an amplifier’s
linear performance.
Figure 3-66: Output power controlled by supply voltage
Figure 3-66 shows how the output power of a typical InGaP HBT amplifier can be
controlled by supply voltage adjustment, as is done in traditional EER systems. Figure
3-67 shows the output power of the same amplifier when, instead of the supply voltage,
the base bias voltage is adjusted as suggested in PW&AM.
102
Figure 3-67: Output power controlled by base bias voltage
Figure 3-68 AM-PM in supply and base bias controlled amplifiers
103
As noted in Figure 3-68, AM-PM conversion occurs in both cases. For a 20dB dynamic
range from 10dBm to 30dBm, phase variation is about 24 degrees and 25 degrees in the
base bias control and supply control cases respectively. This is typical behavior for
amplifiers not specifically optimized for supply modulation or bias modulation. The
phase to amplitude sensitivity is similar in both approaches. However, as intuitively
expected, the bias control method generates less AM-PM at low power output compared
to supply control. The reason is that supply controlled devices operate very close to
maximum output, i.e. with very little headroom, at low powers. On the other hand, the
bias controlled approach creates more AM-PM at high powers because the device is
being pushed to its current handling limit.
The preceding results are derived from simulating a typical amplifier driven by a constant
input power while the supply or base bias voltages are swept. Among the results in
Chapter 2, we observed that in order to achieve a 50dBc or better ACPR at all power
outputs in CDMA, the maximum phase variation preferably should be maintained below
5 degrees, and definitely below 10 degrees. This suggests a need for a design change in
order to apply these techniques to CDMA.
The amount of AM-PM conversion is heavily dependent on the matching network
topology and impedance seen at the gate and drain of the device at the carrier and the first
few harmonics, as well as the size and behavior of the power devices. Making general
statements about how to reduce the AM-PM is not straightforward. In a few CMOS
designs we observed that decreasing the effect of the device’s parasitic capacitors by
purposely adding parallel linear capacitors to the matching network next to the device
helps in reducing AM-PM. This is an intuitive result because the impedances at device
terminals become less sensitive to the parasitic capacitance of the device. It is those
voltage dependent capacitors that change in response to a change in amplitude or
operating condition and cause the change in the impedance phases and hence the phase of
the signal. On the other hand, allowing some back-off helps considerably, but costs in
efficiency. Matching networks that deliver impedances that look closer to those of a
104
parallel tuned circuit at the device terminals tend to cause less AM-PM in CMOS
implementations. However, as the impedance transformation ratio increases due to
headroom limitations caused by higher power or lower supply needs, it becomes harder to
achieve that similarity and therefore the AM-PM sensitivity increases. In cases where
these simple design tradeoffs cannot reduce the AM-PM sufficiently, an external phase
correction mechanism may become required, such as phase pre-distortion or feedback
correction in traditional polar feedback.
From the foregoing it is clear that the envelope elimination function does not eliminate
the AM-PM problem. Then what is the advantage of having a limiter to eliminate the
envelope? The drawbacks are clear: additional complexity and cost, more power
consumption and hardship in providing the right clipping behavior over large enough
dynamic ranges. One benefit is that the drain efficiency roll-off curve will have a slower
slope compared to scenarios with variable input RF amplitudes. When translated to
power added efficiency, however, the tradeoffs are more delicate since the power
consumed in the driver stages and the limiter is taken into account. In a limiter-free
design, the power consumed in the driver stage is lower and obviously no power is
consumed for the limiting function. However, the drain efficiency in the output stage is
lower compared to a design with a limiter.
An example is shown in Figure 3-69 based on simulation of the same typical amplifier
used earlier in this section. Therefore, in a good design the limiter based architecture can
yield a lower slope in efficiency roll-off at power outputs higher than some threshold.
This translates into higher efficiency for some higher power outputs, and a higher slope
and lower efficiency at lower power outputs when the power consumed in the driver
stages and limiter become a substantial portion of the total power consumed.
105
Figure 3-69: Effect of limiter on the drain efficiency of the output stage
The conclusion is that having a limiter and performing the envelope elimination function
is not necessarily required or beneficial in all solutions that apply envelope feedback. It
potentially helps the efficiency and simplifies the envelope linearization problem at
higher power outputs, but does not help much with AM-PM and creates an additional
tradeoff between high power and low power efficiencies. Judgment is therefore required
on a case by case basis as to whether or not a limiter helps based on the specifics of the
power device and the efficiency, linearity and dynamic range specifications.
A general alternative configuration without a limiter is shown in Figure 3-70. The key
additional critical design factors in this configuration are the output stage base bias versus
desired power characteristic, as well as the gain compression curve of the driver and their
interaction. These factors determine the nonlinearity of the equivalent open loop transfer
function from the input envelope to the output envelope. That knowledge in turn dictates
the minimum gain required in the feedback loop to suppress artifacts generated by
envelope nonlinearity. Hence, the feasibility of a solution depends on whether the closed
loop system can be stabilized with the required feedback gain.
106
VDD
Class C PA
RF with
Modulated Envelope
RFin with
Modulated Envelope
vg
Coupler
RL
Driver Stages
Approximately linear
Bias Control
Envelope
Control
Envelope
Detector
+
Envelope
Detector
-
Error
Signal
Integrator
Attenuation
Figure 3-70: Envelope feedback PW&AM without limiter
107
3.1.3.3 Envelope detector dynamic range and integrator offset effects
Earlier we very briefly mentioned some of the challenges seen in feedback methods in
general and with the techniques deploying envelope detectors in particular. Now it is time
to take a closer look at these issues.
One of the most common nonlinear effects in envelope detectors is the turn-on threshold
or dead-zone effect. The quiescent operating condition of the rectifying diode or device
has to be set to minimize the dead-zone. The linearity performance of most envelope
detectors is usually worst at lower powers, since dead-zone related distortion becomes a
more substantial portion of the signal.
Figure 3-71: Waveform for an envelope detector with dead-zone
Figure 3-71 shows the time response of an envelope detector with dead-zone in response
to an AM modulated carrier as its input. For amplitudes below a threshold the detector
fails to track the envelope. In the frequency domain this translates into harmonics of the
envelope modulation frequency as seen in Figure 3-72. Any other nonlinearity in the
108
envelope detector, e.g. resulting from the nonlinear voltage vs. current of the diodes, will
contribute to further envelope harmonic content.
Figure 3-72: Effect of dead-zone on the spectrum of detected envelope
RF feed-through and RF harmonics are also common in the output of envelope detectors.
As the ratio of the bandwidth of the detector to the carrier frequency increases these
effects become more important. In feedback systems like the one shown in Figure 3-70,
the feed-through and harmonic RF content at the integrator can contribute to additional
amplitude dependent offset that degrades the overall system linearity. However, this is
usually a second-order source of nonlinearity in the closed loop system unless very
wideband envelope detectors are used.
Another problem in systems with two envelope detectors, like the one in Figure 3-70, is
that the artifacts generated by the envelope detector nonlinearity are generally not the
same in both detectors, either because of mismatch in the design or more importantly
because of different RF signal amplitude in the two detectors. In order for the artifacts to
cancel in a design with matched envelope detectors, the inputs to the detectors must have
the same amplitude. Unfortunately, the best detection performance usually is obtained in
109
power ranges different from the regular system’s input power ranges. Therefore,
implementations like Figure 3-70 may require pre-amplification of the system’s input
signal fed into the detector. This pre-amplification causes additional sensitivity to
operating frequency and can limit the operable signal dynamic range substantially.
Feeding the desired pre-distorted envelope signal directly from the base-band signal
processing is advantageous from this perspective, since the amplitude of the input to the
detector at the amplifier output can be adjusted by correct setting of the feedback
attenuation. However, such configurations eliminate the chance of canceling the
nonlinear artifacts of two envelope detectors in the subtraction.
In order to obtain information on the effects of mismatch in the envelope detectors on the
detected error signal we performed a few simple simulations using two essentially
identical detectors with turn-on thresholds of 200mV and 170mV driven by the same
modulated RF signal. Thus, the entire mismatch is modeled in a 30mV offset as shown in
Figure 3-73. Such an offset is typical in practical implementations and unfortunately
there is not a simple practical way to eliminate it for continuous time, non-sampled
envelope detectors.
Figure 3-73: Mismatch in envelope detectors
110
Figure 3-74: Error from envelope detector mismatch
Figure 3-75: Spectrum of error form mismatch
111
In Figures 3-74 and 3-75 are shown in the time and frequency domains one of the
envelope detector outputs and the difference of the two outputs, i.e., the envelope error.
Since the loop gain of the closed loop system attempts to zero the error signal which is
the input to the integrator, these errors are directly reflected as in band or spurious
artifacts on the power amplifier output signal spectrum. Any offset in the integrator is
reflected in the output in the same way. As observed in Figure 3-76, the envelope
detector turn-on threshold or dead-zone effect is reflected on the output signal of the
closed loop system as small bumps on the envelope as it crosses into or out of lower
magnitudes. In the frequency domain these bumps are seen as spurs generated at intermodulation frequencies of the carrier and multiple harmonics of the envelope as observed
in Figure 3-77.
Figure 3-76: Dead-zone effect in a closed loop system
112
Figure 3-77: Dead-zone effect in a closed loop system
In most systems, not only do envelope fluctuations exist due to modulation, but also a
usually larger variation of the signal amplitude occurs due to power adjustments.
Therefore, as explored before with other linearization methods, it is important to have a
clear knowledge of the linearity and dynamic range tradeoffs for the closed loop system.
Figure 3-78 contains simulation results for an example closed loop system deploying
envelope detectors with a turn on threshold of 100mV, input signal swing magnitudes
ranging up to 1.5V, an amplifier with 1dB compression point of 32dBm, and a feedback
network with 22dB voltage attenuation from the output to the envelope detector. The
system is fed with an AM modulated signal with modulation index of m=0.7, i.e., 15dB
peak to minimum, with the input power swept to see the dynamic range related effects.
113
Figure 3-78: Dynamic range of a PW&AM system with envelope feedback
As observed, at power outputs lower than 15dBm, the closed loop system cannot
reconstruct the in-band modulation dynamic shape and the modulation index is
suppressed. Substantial spurious emission is also created. This is a result of the fact that
at lower amplitudes the low side clipping of the signal in the envelope detector in the
dead-zone occurs for a high percentage of the time and therefore becomes the dominant
nonlinear effect in the system. Also at lower input and output powers, due to the deadzone, the loop gain is substantially reduced and therefore the loop fails to effectively
correct the distortions. In summary, unfortunately, the loop is not capable of correcting
the dead-zone effect. As the power output increases, the probability of the low side
clipping decreases and the system starts to correctly track the modulation index. As a
result, spurious emissions are reduced as less clipping occurs in the envelope detectors.
As the power increases, the envelope detector becomes more effective. Regrettably
amplifier saturation occurs soon after, substantially degrading the linearity by
114
suppressing the modulation index and increasing the spurs. Unfortunately, these power
and voltage ranges in handset amplifiers are very typical and as a result usage of
envelope detector based systems in handsets becomes severely limited for this same low
dynamic range problem. When higher voltages are available, various microwave diodes
make it possible to implement envelope detectors with better dynamic range. This means
that in systems with higher power output and higher supply voltages, the high side
clipping is shifted to the higher power output and the low side clipping is further shifted
to lower power output and as a result a wider dynamic range with reasonable linear
performance becomes achievable. This suggests that infrastructure amplifiers offer better
potential for envelope detector based feedback system implementations.
115
3.1.3.4 Bandwidth effects and dynamic nonlinearity
We mentioned before that one of the main drawbacks of the linearization methods
deploying feedback is a range of problems that arise from narrow bandwidth in the
feedback loop, including loop stability issues. In this section we quantify some of these
effects for the example closed loop PW&AM system with envelope feedback considered
earlier in this chapter. In a well designed case the closed loop system tracks the desired
envelope modulation very well for low enough envelope frequencies or narrowband
modulations. Figure 3-79 shows how well the output tracks the AM modulated input
when the envelope modulation frequency is around 150 kHz.
Figure 3-79: Closed loop system tracks slower modulations
116
Figure 3-80: Closed loop system fails to track fast modulations
In contrast when the same system is driven by a signal with the same AM modulation
depth, but with the envelope frequency of 15MHz, as observed in Figure 3-80, the closed
loop system fails to track the envelope modulation appropriately. Figure 3-81 shows the
effect of envelope modulation frequency on modulation depth and spurious emission at
the output of the system. As observed this particular system tracks the envelope
modulation reasonably well and generates relatively low spurs for envelope modulation
frequencies or modulation bandwidths lower than 1MHz. For envelope modulation
frequencies higher than 4MHz the spur level increases substantially and the closed loop
system fails to track the modulation depth as well.
In this example, while remaining approximately valid for modulation bandwidths lower
than 1MHz, the quasistatic assumption, discussed in the previous chapter, clearly fails for
modulation bandwidths higher than 1MHz. This example shows that application of the
quasistatic nonlinearity assumption needs careful consideration in systems with envelope
feedback, because in these kinds of systems envelope and RF signals are governed by
117
vastly different dynamics. This causes the difference in performance between
narrowband and wideband modulations.
Figure 3-81: Frequency response of a closed loop PW&AM system
One of the main and common considerations in every feedback system is stability.
Systems with envelope feedback are usually stable in the sense that when no modulation
is applied no oscillation is observed. However, a more descriptive notion would be
envelope stability. Envelope stability can be defined by how well the output envelope
tracks that of the input. We refer to this stability as in-channel envelope stability (ICES).
It can also be defined as a function of how much spur is generated as a result of imperfect
envelope tracking. We will refer to this second definition as out-of-channel envelope
stability (OCES). Thinking in the context of envelope stability as described here, we
observe that the loop is envelope stable up to certain frequencies and the envelope
stability gets worse for higher modulation frequencies. The loop gain in this kind of
systems is nonlinearly dependent on the envelope amplitude as well as the envelope
frequency. The frequency dependence is caused by the integrator, filters in the envelope
118
detectors and the frequency response of the amplifier’s output filter as well as the
feedback sampling network that are all frequency selective. The peak loop gain is
amplitude dependent because of the saturation in the integrator, output envelope detector
and the amplifier itself. As a result while still remaining a very useful tool for gaining
intuition about the behavior of the system, the simple linear stability analysis methods
based on the loop phase and gain margin fail to accurately predict frequencies where the
envelope stability starts to degrade.
Figure 3-82: Loop gain effect on envelope stability
However one of the expected tradeoffs that remains valid is the fact that higher average
loop gain reduces spurs further at the envelope frequencies where the loop is envelope
stable. At the same time higher loop gain reduces the overall envelope stable closed loop
bandwidth, while increasing the spurious level at higher envelope frequencies where the
system is not envelope stable. This is noted in Figure 3-82.
119
To summarize our observations, we have noted that linearity of the closed loop PW&AM
systems with envelope feedback, which can be seen by observing error in tracking of the
modulation depth as an in-channel measure and maximum spurious level as an out-ofchannel measure, is dependent on the signal amplitude and modulation depth as well as
the envelope frequency. The amplitude dependence is primarily caused by saturation
effects in PA stages and integrator, the turn-on threshold in the envelope detectors and
error offset in the envelope detectors and the integrator. The frequency dependence is a
result of the frequency dependent modules, e.g., error integrator, amplifier output filter,
coupling and feedback network and the envelope detector filters.
Before concluding this section let’s observe the combined effect of these factors in a
closed loop system.
Figure 3-83: In-channel linearity and stability
120
As far as the in-channel linearity is concerned, as seen in Figure 3-83, the envelope
detector dead-zone is the primary degrading factor. In systems with no dead-zone the
desired envelope is tracked very well for the in-channel-envelope stable envelope
frequencies, while the envelope skew substantially increases at higher frequencies where
the envelope stability degrades. Envelope detector turn-on threshold always is reflected
as a dead-zone in the system and causes envelope skew even at lower envelope
frequencies where the system is otherwise envelope stable. Any offset in the envelope
detector output and integrator input is reflected as an additional random error in the
envelope and is observed as a modulation skew or a change in modulation depth. In
systems with an envelope detector induced dead-zone, higher amplitude signals suffer
less from modulation skew, as intuitively expected. Also, as is observed in Figure 3-83,
the in-channel-envelope stability bandwidth of the closed loop system with dead-zone is
dependent on the amplitude. The in-channel envelope stable bandwidth is lower for the
lower signal amplitudes.
Figure 3-84: Out-of-channel linearity and stability
121
In Figure 3-84 we see the impact on the out of channel spurious generated in the closed
loop system. As noted for the high amplitudes, the presence of the dead-zone and offset
have minimal impact on spurious levels at the frequencies where the system is envelope
stable. However, the sensitivity of the spur levels to the amplitude of the signal is quite
high when the envelope detector induced dead-zone is present. This refers to the same
impact of the dead-zone on limiting the linear dynamic range as earlier observed in
Figure 3-78.
In conclusion, envelope detector dynamic range severely limits the achievable dynamic
range for the envelope feedback based systems in general, and for PW&AM systems with
envelope feedback in particular. On the other hand, the presence of the feedback loop
substantially limits the usable modulation bandwidth of the system. Therefore alternative
implementations of linear power amplifier systems that use no feedback and no envelope
detectors may be more desirable, when possible.
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3.1.3.5 Potential for bias-controlled ER with envelope pre-distortion
Based on what is observed so far, an implementation of the bias-controlled envelope
restoration without envelope feedback or envelope detectors, like the one shown in
Figure 3-56, promises higher bandwidth and higher linear dynamic range. Unfortunately
as noted earlier, in most of the amplifiers, the transfer characteristic from the output stage
bias to the output envelope magnitude is not linear. Therefore, an appropriately predistorted envelope control signal needs to be fed into the system in order to produce the
desired output modulation.
Common challenges of pre-distortion based systems, including sensitivity to temperature
and manufacturing and aging related drifts, apply to envelope pre-distortion based
PW&AM systems as well. As a result these may necessitate adaptive adjustments of the
envelope pre-distortion table. The advantage compared to traditional pre-distortion is the
potentially better efficiency vs. power roll off curves offered by bias controlled PW&AM
amplifiers.
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3.2 Linearization by design of shape of gain compression curve
Earlier in section 2.3 it was observed that an expansive gain response followed by a
compressive one right before the saturation provides a local minimum on the ACPR
versus power curve at a reasonably low back off from the saturation. This was in the
discussion of Figure 2-17 in a study of the effect of various biasing conditions and their
corresponding shape of gain compression curves. This means that an acceptable linear
performance can be achieved at back off levels lower than those traditionally assumed to
be required. The possibility of operating closer to saturation would allow higher peak
linear efficiencies to be achieved.
Also, as we will soon discuss in further detail, most power devices experience some level
of self-biasing [56 and 57]. That is, as the power output increases the bias current level in
the device increases. One positive benefit from this self-biasing behavior is that the
quiescent current of the device can be set at a lower current for most of the lower power
outputs and as the power output increases the device current is boosted up to the higher
currents required [58]. This leads to efficiency roll off curves with lower slope, i.e. higher
efficiencies at lower powers in devices with higher self-biasing [59]. One associated
problem though is that too much self-biasing with much lower bias currents at lower
powers creates an expansive gain behavior which can have destructive impact on the
linearity if not properly compensated. In this section we will discuss these issues in
further detail.
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3.2.1 A note on self-biasing
The base or gate bias lines of output and driver stage devices in power amplifiers is
usually supplied from bias reference circuits that have relatively low output impedance.
As a result these can be considered as voltage references. In HBT implementations the
base current needs to be supplied by the bias circuit. The impedance of the bias circuit’s
output has to be low enough to provide the drive capability to deliver the base current
while setting the correct base voltage. Figure 3-85 shows a bias scheme that is very
commonly used in InGaP HBT designs.
Vref
Bias Vcc
Vcc
Matching
Network
RF
To Next
Stage
Figure 3-85: Biasing an amplifier stage
When the output or driver transistors are driven with large RF signals the nonlinear
behavior of the device causes the device to function as a rectifier and generate the a
portion of the required DC current from the RF current pulses. This occurs when the
initially set quiescent current is not high enough. The amplification and rectification
function when the device amplifies larger RF signals causes the device to draw higher
DC currents from the Vcc and the base bias line to produce the output current pulses.
This self-biasing behavior allows the device to move automatically to operate at the DC
current levels needed to provide the needed current pulse amplitudes and waveforms.
125
Figure 3-86 shows this behavior as observed in the output stage of a typical power device
biased with a scheme essentially the same as the one shown in Figure 3-85.
Figure 3-86: Effect of load impedance on self-biased DC current
In figure 3-86 the fixed quiescent current is 60mA. As a result of the self-biasing, the DC
current substantially increases to provide the required current for delivering the output
power. When load impedance is lowered, higher currents are needed to deliver the same
power. The three curves represent the collector current of the same device with the same
input biasing and matching for three different load impedances on the collector.
Interestingly, the self-biasing mechanism automatically increases the current to deliver
the higher needed currents when the load impedance is lower.
The shape and magnitude of the high power part of the self-biasing curves in Figure 3-86
are functions of the device structure and the load impedance seen by the collector at the
carrier frequency and its harmonics. On the other hand at lower power outputs the bias
circuit determines the current. This behavior is very useful since it allows the device to
move to the operating condition needed to deliver the required power. However, it
complicates the amplifier design process since it couples the output match and biasing
126
design problems together. As long as the bias reference circuit has the capability of
delivering the maximum required base DC current, the tradeoffs can be made
successfully.
Before proceeding to explore how the tradeoffs in amplifiers with multiple self-biased
stages can be used to provide required linearity while improving the power efficiency, it
will be useful to briefly consider how the load impedance affects gain and power output
of self-biased amplifiers. As intuitively expected, when the primary saturation
mechanism is supply voltage limitation as is the traditional design in most amplifiers,
higher load impedance translates into higher gain and lower maximum output power.
This is shown in Figure 3-87.
Figure 3-87: Effect of load impedance on gain and power output
Another practical point that needs to be noted is that almost every power device
experiences some self-biasing unless particular care is taken to avoid it. At high levels of
self-biasing, the conduction angle in the device is quite high. Therefore, practical
implementations of most of the other techniques discussed earlier in this chapter that rely
on lower conduction angles in the devices, require careful design to minimize self-biasing
and that may dictate a need for negative bias supply voltages as well.
127
3.2.2 Cascade of self-biased nonlinear stages
As discussed in the previous section at higher power outputs the DC current of a device
in the self-biased region is primarily determined by the load it sees and the power of the
signal. When the device is large enough the compression behavior and the peak power is
primarily determined by the load impedance. Gain is always dependent on the current and
load impedance. On the other hand at lower power outputs the current is set by the
biasing circuit. As seen in Figure 3-86, a ten-fold variation in the DC current can occur.
Since gain is dependent on the current, more self-biasing is expected to cause more gain
variation over a power range. Since current at high power outputs is relatively
independent of the quiescent current, biasing devices at lower quiescent currents creates
more self-biasing which can cause more gain variation over the power range.
Figure 3-88: Self-biasing for various quiescent currents
128
Figure 3-89: Shape of gain
Figure 3-88, represents simulated DC current versus power output of the output stage in a
typical two stage amplifier for quiescent currents ranging from about 20mA to 80mA. For
higher power outputs, e.g., higher than 15dBm in this particular design, the current of the
stage is predominantly determined by the self-biasing mechanism. Figures 3-89 and 3-90
show the magnitude and phase of the amplifier gain for the same set of currents shown in
Figure 3-88. For lower quiescent current we observe more self-biasing, more gain
variation, larger gain peaking before saturation, compression at slightly lower power
outputs, and more phase variation over power change at lower power outputs. At
sufficiently large quiescent current the low power gain can be made large enough so that
no gain expansion occurs.
129
Figure 3-90: Phase variation
Figure 3-91: Impact of the second stage on current of the driver stage
130
In these simulations the maximum power output of the device changes from 31dBm to
31.5dBm as the quiescent current increases. Usually a change in the self-biasing curve,
i.e. DC current versus power output characteristic, in the output stage causes a change in
the self-biasing curve of the driver stage as well. This occurs because the base impedance
of the output stage changes as the current changes in the output stage. Through the
interstage matching network this change is reflected onto the impedance seen at the
collector of the driver stage. This changes the self-biasing curve of the driver stage as
shown in Figure 3-91. This further illustrates the fact that different stages in power
amplifiers interact so it is very important to perform the design and optimization of
multistage amplifiers as a whole with careful consideration of these interactions.
Figure 3-92: Power added efficiency of the two stage amplifier
For a two stage amplifier, simulated power added efficiency roll-off curves for the above
seven quiescent current values for the output stage are seen in Figure 3-92, and with
further detail in Figure 3-93 and Figure 3-94. At high power outputs the power added
efficiency roll-off slope is -4.4% per each dB of back off. This is reflected as a 2%
increase in the case of IQ=20mA compared with IQ=80mA as a result of the 0.5dB change
131
in the peak power. In general, designs using lower quiescent currents show higher
efficiencies compared to their equivalent counterparts with higher quiescent currents.
Figure 3-93: Power added efficiency of the two stage amplifier
Figure 3-94: Power added efficiency of the two stage amplifier
132
Therefore in more modern designs where there is a need to take advantage of all the
incremental improvements that can be achieved at no cost, the tradeoffs of linearity and
efficiency related to quiescent current and self-biasing behavior also need to be
considered. In general, lower current translates into better efficiency. Power capability of
the device and the load design dictate the minimum current at high power output, taking
into account the load requirements for the linearity. Minimum usable quiescent current is
limited by the required linearity and gain at lower power outputs as well as the
requirement to guarantee that devices remain biased on over the required temperature
range and manufacturing related device variations.
Figure 3-95: Linearity of the two stage amplifier
133
Figure 3-95 shows the simulated linearity performance of the two stage reference
amplifier used in this section for different quiescent currents. The ACPR curves are
derived using the method discussed in Chapter 2. As seen in the case of IQ=80mA, too
high quiescent current turns the gain response into a fully compressive one and therefore
the performance at power outputs below 27dBm is not as good as for IQ=70mA, which is
the closest approximation to a clipped linear gain characteristic. In all the other cases the
expansive/compressive nonlinear gain characteristic causes the ACPR to have a local
minimum between 26 and 27dBm. This range has been chosen by design to provide the
required linearity of close to, or better than, -50dBc ACPR at or below 28dBm output,
while minimizing the back-off and delivering the highest achievable efficiencies at
28dBm, the peak linear power specification for most CDMA handset amplifiers.
At lower power outputs as also discussed in Chapter 2, ACPR curves have a local
maximum between 18dBm and 13dBm and then roll down again. This is mainly due to
the gain magnitude having a zero second derivative somewhere in that power range. Of
course, the phase characteristics also have an impact on the shape of these ACPR curves.
Although considered second order effects due to reasonably low variation of the phase
with power output, these effects also have been taken into account. The case of 40mA
delivers the highest efficiency among the ones with acceptable linearity of better than
-50dBc at power outputs lower than 28dBm. This case shows 1.8dB of gain peaking,
peak power of 31.3dBm, i.e. back-off of 3.3dB at 28dBm delivering -50dBc linearity,
with a peak linear efficiency of 42% at 28dBm. These simulations were used here as an
example design case to show how the tradeoffs of gain, power, efficiency and linearity
related to load design, self-biasing and gain compression curve design for ACPR can be
interactively incorporated in one simple design that delivers the required linearity while
improving the efficiency. Before taking advantage of these tradeoffs in the design, the
highest linear efficiencies for CDMA handset power amplifiers were only slightly over
36%.
134
Vcc=3.4, Vref1=Vref2=3.0, F=1.765GHz
+25C
32.00
-30C
+85C
31.00
GAIN (dB)
30.00
29.00
28.00
27.00
26.00
25.00
0.00
4.00
8.00
12.00
16.00
20.00
24.00
28.00
Pout (dBm)
Figure 3-96: Measured gain
Vcc=3.4, Vref1=Vref2=3.0, F=1.765GHz
+25C
-30C
+85C
-40.00
-45.00
ACPR (dBc)
-50.00
-55.00
-60.00
-65.00
-70.00
0.00
5.00
10.00
15.00
20.00
25.00
30.00
Pout (dBm)
Figure 3-97: Measured ACPR
135
Vcc=3.4, Vref1=Vref2=3.0, F=1.765GHz
+25C
-30C
+85C
50.00
45.00
40.00
35.00
PAE %
30.00
25.00
20.00
15.00
10.00
5.00
0.00
15.00
17.00
19.00
21.00
23.00
25.00
27.00
29.00
Pout (dBm)
Figure 3-98: Measured power added efficiency
Figures 3-96, 3-97 and 3-98 show measurement results on a sample two stage power
amplifier designed using the above approach on a 2µm InGaP HBT process. Figure 3-96,
Figure 3-97 and Figure 3-98 show gain, adjacent channel ACPR, and power added
efficiency respectively. The data were collected at three ambient temperatures of -30C,
+25C and +85C. The expansion and compression is seen on the gain curves. Also local
minima close to 28dBm on the ACPR curves are observed as expected. Efficiency at
28dBm ranges from 39% to 42%. The test signal was a CDMA modulated carrier at
1.765GHz.
One interesting observation is that for +85C where the gain variation is less than that seen
for +25C and -30C, the ACPR curve is also lower at power outputs less than 26dBm.
This is consistent with the prediction from Figures 3-89 and 3-95 that cases with less gain
peaking would have lower ACPR at lower power outputs.
136
It also needs to be noted that the numerical error in simulating ACPR is dependent on the
length of the data sequence used in the simulation among other factors. In most of the
simulations in this thesis in order to maintain the simulation times reasonable, the length
was set and a fixed sequence was used. The numerical error due to this concatenation
causes the program to estimate an ACPR of -59dBc for the original non-distorted
sequence. This is reflected in most of the simulated ACPR curves in this thesis as a noise
floor of -59dBc. Since the target linearity is -50dBc, this sequence length provides a
reasonable margin to account for the critical ACPR induced by the amplifier nonlinearity
while maintaining the simulation times reasonable and the need for memory at
manageable levels. This is the reason for the observation that while the measured ACPR
results are below -60dBc at low power outputs, the simulation results have a minimum
value of -59dBc.
137
138
Chapter 4: PA module constructions and matching methods
In cellular phone handset applications, it is customary to use internally matched power
amplifier modules (PAMs). These modules include the amplifier die, elements for input
matching and output impedance transformation to 50 ohms and in some applications
additional semiconductor dice for bias and power control or other signal conditioning
functions [60]. The most usual construction includes a multilayer substrate to which the
other elements are soldered or glued using a die attach, and a mold on top that covers and
protects the wire bonds [61]. The input impedance for the module is 50 ohms.
The amplifier performance is optimized based on the assumption that the module sees a
50 ohm nominal load. The robustness is specified for a range of VSWRs. This has
become the standard way of specifying and measuring handset power amplifier module
performance. The objectives are to have more standardized ways of testing and
benchmarking PAs, standardizing transformation networks on the phone printed circuit
board and ultimately allowing “drop in” of equivalent power amplifiers from different
manufacturers. Since the output impedance transformation network has to have minimum
loss in order to minimize the efficiency degradation, it is not possible to design a module
with an output impedance of 50 ohms. Doing so will simply impose an extra
unacceptable 50% power loss. So the 50 ohm output matching refers to an impedance
transformation network that allows delivering the power to a 50 ohm load while
presenting the right impedance to the device so that it delivers appropriate power and
performance.
It is traditionally assumed that building high performance PAMs is only possible by using
off-chip inductors and capacitors for the output matching network. Among the reasons
are need for a) high-Q elements, since the loss at the output matching network causes
substantial efficiency degradation, b) low tolerance of amplifiers to output matching
element variations, and c) the need to manually modify and tune the module to yield the
139
desired performance, since most of the designs still are fine tuned by trial and error. As a
result the majority of today’s handset PAMs include a number of off-chip passive
elements that are used to implement the output impedance transformation network.
Various multi chip module (MCM) manufacturing technologies are used to integrate such
off-chip passives into the PAM [62][63][64]. In this chapter we show how these off-chip
passives can be eliminated to reduce the size and cost of the PA modules [65]. Pros and
cons of a few alternative matching network topologies are discussed along with some
related experimental data.
140
4.1 Traditional output matching network topologies and implementations
In today’s handset applications, power amplifiers operate on a rechargeable battery and
the supply voltage ranges from near 4V at full charge to 3.2V on a nearly fully
discharged one.
Thus, amplifiers have to deliver power while meeting linearity
specifications at supply voltages as low as 3.2V. The specification for peak power, i.e. no
back-off, ranges from about 32dBm in CDMA handsets to 35.5dBm in some of the
multimode GSM handsets. This requires the real part of the load impedance on the
collector of the output device to be in the range of 1.5 to 3 ohms. Output device sizes are
primarily determined by the need to drive such loads with the required power. The
imaginary part of the load at the collector is usually tuned to optimize for efficiency,
linearity or a mixture of the two for a specific device. It is the function of the output
matching network to transform the 50ohm load into the desired impedance in that range,
e.g. 3 ohms, at the collector of the device.
One of the most common and efficient topologies for the output stage impedance
transformation network in handset power amplifier modules is a two stage low pass
matching network as shown in Figure 4-1. Some of the common variations come with
additional series LC tanks in parallel with the collector that resonate at 2nd or other
harmonics and act as harmonic traps [66].
Vcc
Bond Wires
(Z ~ R+jX Ohm)
To Collector of the
Output Transistor
Chip
Module
Module Phone PCB
Figure 4-1: A two stage low pass matching network
141
The two stage design is attractive since the Q of each stage can be below 2 compared to
the Q’s above 4 that are required for single stage networks. Lower Q in the stages means
that more wideband impedance transformation is possible and also the networks and their
respective amplifiers can be designed to be less sensitive to component variations. This
promises better yield with typical component variations. Wider bandwidth is desired
particularly in multi-band PA applications.
Discrete Passives
Power Amplifier Chip
Bias Control Chip
Figure 4-2: A traditional PA module
As seen in Figure 4-1 such implementations require at least 6 passive elements either
implemented on or soldered onto the module’s substrate for each amplifier. A module
may include more than one amplifier to address the need for multiple frequency bands. In
142
topologies with additional harmonic traps this number grows to 7 or 8 depending on the
specifics of the implementation. Depending on the values of the inductors, some can be
implemented using traces on the substrate. In handset PA modules the capacitors are
usually standard components soldered onto the substrate. Figure 4-2 shows a picture of a
module that deploys a matching network topology and implementation like the one in
Figure 4-1.
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4.2 A new approach to eliminate off chip discrete passives
In the traditional matching method discussed in the previous section, a major portion of
the manufacturing cost is due to the extra passives and multi layer substrates large
enough to allow enough space for routing, mounting the PA die and soldering the
passives.
Module yield is another major cost related concern. Although the two stage matching
network design promises better yield from the perspective of sensitivity to component
variations, maintaining the module yield high enough while attempting to squeeze all the
extra passive components in a smaller area can be very challenging. One of the major
problems is the soldering yield when passives are squeezed too close together or to the
bond wires.
On the other hand smaller PA modules are more attractive since they save space on the
phone boards. At the same time the need to have multiple power amplifiers in a single
module to address the need for multiple standards or multiple bands imposes tighter
restrictions on the module size. Based on these concerns it is obvious that a major step in
improving the PA modules from the cost, manufacturability and size points of view is to
eliminate the off chip passives. In any alternative implementation approach the concern
about whether desirable performance and yield can be achieved remains a critical one.
The new alternative approach presented in the remainder of this chapter is based on a
simple and old concept. Every capacitor has to be implemented on the power amplifier
die. Every inductor has to be made of bond wires that go between the PA chip and the
package leads or the module’s substrate. We can call this the “no passives guideline”.
The bond wires quality factor is high enough to allow implementation of impedance
transformation networks with acceptable loss. Fortunately high-Q capacitors are also
available in InGaP processes that are commonly used in making handset power
amplifiers. This promises that the loss in the output matching networks implemented
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using this concept should have losses comparable with their off-chip counterparts in the
modules and therefore reasonable efficiencies should be achievable.
From a designer’s perspective one of the attractions of this approach is that one does not
have to deal with all the unwanted self resonance effects of the discrete passives
anymore. Those self resonances in the discrete capacitors are dominant factors in the
shaping of the impedance at the harmonics of the carrier in handset PAs. Therefore
design of higher order networks for the harmonic shaping can become more challenging
when using capacitors with low self resonance frequencies. A disadvantage of the newly
proposed approach however is that tuning the design by changing capacitor values
becomes impossible. At the same time dependence of the PA performance on the values
and couplings of the output related bond wires becomes more significant. Therefore more
careful electromagnetic modeling of the bond wire values and their couplings can create
substantially better insight in this kind of design. In summary some newer design
optimization methodologies, different from the ones used for more traditional modules,
are required to follow the no passives guideline presented here. That includes the need to
explore newer matching topologies for the output match, as well as devising fine tuning
methodologies based on appropriate design of experiments.
From the design for manufacturability perspective designers must deal with some newer
tradeoffs in the proposed no passives method. It becomes particularly important for the
designers to revisit the practical tolerances in the packaging process and their impact on
the range of values of the bond wires and their couplings and the subsequent effect on
amplifier performance.
In the remainder of this chapter we will discuss in further detail results obtained from
some specific attempts to make power amplifier modules based on the no passives
guideline.
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4.2.1 HP matching networks
The first thought that naturally comes to mind is to attempt implementing the same
proven matching network shown in Figure 4-1 based on the no passives guideline. Every
inductor has to be implemented using one or a few bond wires in series or in parallel.
Each end of an inductor that meets a capacitor needs to be bonded on the PA die. The
inductors that are connected to two capacitors need to have the two ends on the die.
Therefore they have to be formed using at least two bond wires in series one going out
from the die to a pin on the package and one coming back from the same or a connected
pin on the package to another bond pad on the die. For a matching topology like the one
in Figure 4-1 this calls for at least six critical bond wires that determine the shape and
value of the impedance at the collector and directly affect all the performance measures
of a PA. Any error, unexpected coupling or off tuning related to those inductors can ruin
the PA’s performance. Two capacitors are also required on the chip after the output
device which imposes additional restrictions on the layout of the PA chip’s output.
In summary implementing Figure 4-1 based on the no passives guideline sounds very
risky as a first attempt in checking the feasibility of the approach. In order to avoid the
unwanted extra risk in the first attempt it seems more logical to try a simpler topology. A
first natural step in simplifying the problem is to use a single stage matching network.
The available alternatives for a single stage match are the low pass and the high pass
matching networks. The low pass method calls for an extra DC blocking capacitor.
Figure 4-3 shows the circuit schematic and a sample sketch of a bonding diagram for the
low pass method.
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Vcc
Low Pass Method
To Collector of the
Output Transistor
Vcc
DC Block
Out
Out
50 Ohm
Load
To Collector of the
Output Transistor
To Ground through
Backside Via or
Bond Wire
Chip
Module/Package
Figure 4-3: Low pass matching
The alternative high pass method is represented in Figure 4-4. The naming is rooted in
the fact that the single stage LC networks that perform impedance transformation in the
two cases are low pass and high pass networks. Compared to the low pass case, the high
pass alternative needs one less capacitor and fewer bond wires and there is no need to
take the RF signal out of the chip and bring it back. This promises a much simpler tuning
problem. When needed, harmonic traps can be added to both networks by adding a
capacitor on the die with one side connected to the collector of the output stage and the
other side connected to bond wires going to ground on the module or package.
Vcc
High Pass Method
Bond Wire's
Parasitic
To Collector of the
Output Transistor
Vcc
Out
To Collector of the
Output Transistor
Gnd
50 Ohm
Load
Out
Chip
Module/Package
Figure 4-4: High pass matching
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Figure 4-5: PA module in a lead frame package with no discrete passives
As already noted when following the no passives guideline, matched power amplifier
modules can be built using standard lead frame based packaging techniques, such as the
one shown in Figure 4-5. Based on this approach several amplifiers have been designed,
built and tested. They successfully delivered their target performance for different
applications. As an example Figures 4-6 and 4-7 contain some measurement results from
a PA module implemented using the same approach for a wideband CDMA application.
Using this approach allows shrinking of the CDMA PA module sizes from 6mm x 6mm
to 4mm x 4mm and subsequently to 3mm x3mm in the newest generations.
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Vcc=3.6, Vref=3.0, F=1.95GHz
PAE +25C
50.00
PAE -30C
PAE +85C
45.00
40.00
PAE %
35.00
30.00
25.00
20.00
15.00
10.00
5.00
0.00
15.00
17.00
19.00
21.00
23.00
25.00
27.00
29.00
Pout (dBm)
Figure 4-6: Measure power added efficiency
V cc=3.6, Vref=3.0, F=1.95G H z
0.00
ACLR1 +25C
ACLR1 -30C
ACLR1 +85C
-10.00
ACLR (dBc)
-20.00
-30.00
-40.00
-50.00
-60.00
15.00
17.00
19.00
21.00
23.00
25.00
27.00
29.00
Pout (dBm )
Figure 4-7: Measured linearity
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4.2.2 LPHP and LPLP networks
As briefly mentioned in the previous section, two stage matching networks like the one in
Figure 4-1 can be designed to provide wider bandwidth for the impedance transformation
compared to the single stage cases discussed in the previous section. This is due to the
additional degree of freedom in the design provided by the second matching stage. In
some applications, such as some multiband and multistandard handsets where the PA
modules have to perform over wider bandwidths, single stage matching networks fail and
inevitably one has to consider the two stage matching networks. In this section we
discuss some results obtained from experiments in designing power amplifier modules
based on two stage output matching while attempting to follow the no passives guideline.
Following the same naming convention used in the previous section, the matching
network shown in Figure 4-1 can be referred to as a low pass-low pass (LPLP) network.
That topology can be implemented using on chip capacitors and bond wires as presented
in Figure 4-8.
To Collector of the
Output Transistor
Vcc
LPLP Matching
Out
To Ground through
Backside Vias or
Bond Wires
Chip
Module/Package
Figure 4-8: Low pass-low pass matching
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The main problem with such an implementation is the critical dependence of amplifier
performance on too many critical coupled bond wires. The coupling is high because of
the physical proximity that is dictated by the small size of the die’s output side. This
makes the task of tuning and optimization of the module much more complicated.
Another disadvantage of the implementation shown in Figure 4-8 is the need for three on
chip capacitors. Comparing this with the simple implementation of the single stage high
pass network in Figure 4-4 that has only one capacitor on the chip with only one critical
inductor implemented by a single bond wire or two parallel bond wires shows the
additional complexity of LPLP matching.
To reduce practical complexity of the implementation, one solution is to release the no
passives requirement to allow for only one capacitor on the module. As seen in
Figure 4-9, this approach reduces the number of bond wires and allows more space
between them and therefore reduces the couplings to a more manageable level. There is a
cost and space penalty for having the capacitor on the module but it is still much simpler
than traditional implementations requiring 6 passives or more on the module.
To Collector of the
Output Transistor
Vcc
LPLP Matching
with One Capacitor
on the Module
Out
To Ground through
Backside Vias or
Bond Wires
Chip
Module/Package
Figure 4-9: Low pass-low pass matching with one discrete capacitor
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Another alternative to the LPLP matching network is a two stage low pass-high pass
(LPHP) network consisting of a low pass and a high pass section as shown in
Figure 4-10.
Vcc
LPHP Matching
Bond Wire's
Parasitic
Out
To Collector of the
Output Transistor
50 Ohm
Load
Figure 4-10: Low pass-high pass matching
As observed in Figure 4-11, this topology can be fabricated following the no passives
guideline and the complexity is slightly lower than Figure 4-8 since it needs fewer bond
wires and one less capacitor on the chip.
To Collector of the
Output Transistor
Vcc
LPHP Matching
Gnd
Out
To Ground through
Backside Vias or
Bond Wires
Chip
Module/Package
Figure 4-11: Implementation of LPHP matching
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Other alternatives are high pass-low pass (HPLP) and high pass-high pass (HPHP)
networks. HPLP does not reduce the complexity of the problem any further. HPHP
networks are the simplest ones from the implementation point of view. The HPHP
network has only two or two sets of parallel critical bond wires as shown in Figure 4-12
and Figure 4-13.
Vcc
HPHP Matching
Bond Wire's
Parasitic
Out
To Collector of the
Output Transistor
50 Ohm
Load
Figure 4-12: High pass-high pass matching
To Collector of the
Output Transistor
HPHP Matching
Vcc
Gnd
Gnd
Out
Chip
Module/Package
Figure 4-13: Implementation of HPHP matching
However, another important practical concern is the allowable harmonic level at the
output of a power amplifier. With HPHP output networks more care and additional
mechanisms are needed to maintain tolerable harmonic levels. Hence, in a specific set of
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experiments performed to study feasibility and practical issues of two-stage output
matching networks for multiband power amplifiers intended for GSM applications which
have rather tight specs on harmonic levels, the experiments were narrowed to
accommodate only LPHP as in Figure 4-11 and LPLP with one capacitor on the module
as in Figure 4-9. We should remember that for each scenario of output matching, a new
chip has to be designed to include the correct capacitors and pin out for the output
matching network.
With careful design and enough effort in optimizing the solution through iterations both
of the topologies are promising. As expected, the simpler less coupled solution of
Figure 4-9 could be tuned to deliver the power output and efficiency with less effort. At
35dBm the efficiency was close to 55% after module tunings in the first attempt on the
chip. In the first IC run, the LPHP case delivered only 44% efficiency at around 33dBm
and was short on delivering the target power of 35dBm. Balanced and symmetric PA
layouts are common particularly at high frequencies [66]. However, in both of these
experiments in order to reduce the die size aggressively, no specific network was put in to
balance the load on the output device. This limits the balancing to whatever level is
provided by quasi-symmetric placements of wire bonds and other elements on the die and
module. This aggressive move created reasonably acceptable results in the LPLP case
where enough room was available to balance the layout more effectively while facing
fewer bond wire coupling related problems. On the other hand due to the space tightness
and coupling related problems, the more complex LPHP implementation had more
unsolvable asymmetry that degraded the amplifiers performance substantially.
This asymmetry effect was observed in thermal images of the amplifiers. Figure 4-14, the
LPHP case, shows much more loading asymmetry to the extent that the upper half of the
device is almost not functioning. Transistor temperature in the other half is as high as 189
degrees C. In comparison, as seen in Figure 4-15 for the LPLP case, transistor load is
balanced more effectively and most of the output transistor cells except for the ones close
to the two edges are functioning relatively well, allowing the hottest output device cells
to operate at cooler temperatures, as low as 102 degrees C.
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This area is least effective
Temperature= 167 °C
This area provides
most of the power output
Temperature= 189 °C
Figure 4-14: A grossly power imbalanced PA
Most active cells
Temperature= 102 °C
Bonding is more symmetric
compared to Figure 4-14
Figure 4-15: A PA with some power imbalance
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Unfortunately, there is no known systematic relationship between the achievable design
symmetry and the topology of the output match or its bonding complexity. In fact, with
additional iterations in making the LPHP design more symmetric, it should be possible to
achieve the same performance levels as the other topology. However, dealing with
multiple interrelated complexity and tradeoff problems at the same time can distract a
designer from being able to address all issues and thus to achieve the desired optimal
performance in one attempt. The many interrelationships between design tradeoffs are the
primary reason that power amplifier design is a highly iterative process. In summary,
comparing various alternative topologies and implementations for the output match, it is
still not clear what systematic performance related disadvantages or advantages exist for
any of them, except from the harmonic content point of view. One expects better
performance results can be achieved with less effort on iterations and tuning for the ones
that look simpler.
Since we brought up the issue of asymmetry and its effect on the thermal and electrical
performance of the amplifiers, it may be appropriate to conclude this section with a few
more sentences on this topic. An alternative and perhaps more appropriate phrase for the
asymmetry mentioned above could be power imbalance which can be defined as variation
of the delivered RF power and or dissipated power over different transistor cells in the
output stage. When transistor cells are identical in construction, power imbalance can be
caused by source imbalance, i.e. variation in the impedance seen by the base of the
transistor cells, DC or bias circuit imbalance, i.e. variation in the quiescent voltage or
current at the base from one cell to the other, or load imbalance, i.e. the load impedance
seen at the collectors of the transistors.
Power imbalance among the output power transistor cells of an amplifier results in some
of the cells delivering a higher portion of the total power output, and thus operating at
higher temperatures. Some other cells deliver less power and operate cooler. This
effectively reduces the active transistor size. This power imbalance leads to higher loss in
the combined device and is reflected in the overall PA performance as reduced efficiency
and lower power handling capability by the amplifier. This effect is seen in the
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experiment on the LPHP case in this section. Since with power imbalance, a portion of
the device operates at higher temperature, reliability of the device is reduced. This is
reflected in related measures, e.g. imbalanced devices may show shorter mean time to
failure.
Among the methods that help to reduce the power imbalance in larger devices are emitter
and base ballasting [68 and 69], although their primary objective is to avoid thermal
runaway [70, 71 and 72]. The primary mechanism is negative feedback. When power
output or temperature increases in one device, its current increases and causes additional
IR drop in the ballast resistors. This voltage drop in turn tends to reduce the operating
current. The net result of this mechanism is to reduce the current and power output in
that particular cell and thus to push the input impedance of the cell up and cause more of
the RF power input to be directed to other cells. Therefore the ballasts provide most help
in balancing when there are enough cool and low power adjacent cells available to
effectively take the load from the overloaded cells. In more modern amplifiers where cost
considerations further squeeze device sizes and the ballasting resistor values have to be
pushed to minimum acceptable values in the pursuit of higher power efficiency, the
balancing effect of the ballast resistors is decreased and they tend to provide mainly the
protection against thermal runaway. One of the areas open for further research is the
quantifying of the systematic balancing effects of ballast resistors in response to
temperature and power gradient over the power device cells.
The main method for reducing or avoiding power imbalance is to use balancing trees in
the layout between the amplifier stage RF input and the RF input to the bases of the cells,
between the DC bias network and the bias input to the bases of the cells, and between
collectors of the cells and the output load [66]. The cells are the same by construction, are
biased at the same levels (since they see the same impedance and voltage drop on the bias
network), and see the same load impedance on their collectors. They therefore present the
same large signal input impedance in the presence of the same RF signals. Therefore the
balanced tree in the RF input path sees the same impedance looking into the bases of the
cells and therefore delivers the same RF power to each cell. This way all the cells in the
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output device are expected to have the same power output and loss which yields a perfect
power balancing condition. However, we made a hidden assumption that the temperature
of all the cells is the same. Cells that generate the same heat, i.e. same power loss, will
have the same temperature only when the space around them exhibits the same thermal
behavior, i.e. same thermal conductivity and boundary conditions.
The fixed temperature assumption is valid when in layout the cells are positioned in a
thermally balanced way, or on a thermal balancing tree that makes the junction to
ambient thermal resistances the same. In practice there usually remains some imbalance
at the corners of the output device, but in good layouts most of the cells experience
approximately the same thermal environment. In these scenarios the ballasts may come
into play to further equalize the power levels on adjacent devices that are closer to the
corners. One interesting question that remains open for further research is in amplifiers
driven by power controlled signals with fast changes in power levels. The question is
what are the dynamics of the change in the temperature and power balance over the
device and how does that affect the performance of the amplifier.
Before we conclude let’s look back at Figures 4-14 and 4-15. As mentioned before no
balancing tree was used on the output of these devices. The objective was to save chip
space and associated cost and see if it still has reasonable performance. Note that the
output current is high and therefore the output balancing trees are composed of wide
traces. Therefore they take considerable space on the die. While we fully paid the toll in
the LPHP case, we obtained reasonable, yet sub-optimal efficiency in the LPLP case.
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Chapter 5: Conclusion
Section 5.1 provides a summary of the previous three chapters. We conclude by briefly
discussing future research directions in section 5.2.
5.1 Summary
We noticed the need for faster simulation methods and tools for estimating the effects of
power amplifier nonlinearities in the presence of non constant-envelope modulations. In
chapter 2 a very fast method was presented to address this need.
One of the main problems in linear amplifiers is their lower efficiency compared to the
nonlinear amplifiers. Also most of the modern handsets amplifiers have to operate over a
wide range of power levels due to the widely used power control schemes. Very low
efficiency at lower power is therefore an issue for most amplifiers. In chapter 3 PDM,
PWM, PW&AM and nonlinear cascading were presented as four alternative techniques to
the traditional linearization methods with the goal of addressing the need for higher
efficiencies in linear amplifiers both at high and low powers. The first two can
theoretically achieve much higher efficiencies when fast enough and efficient power
devices are available. Unavailability of such devices is the primary limitation on
effectiveness of these techniques at GHz carrier frequencies. PW&AM was presented as
a compromise solution with feasible implementations based on today’s devices. This
technique promises higher efficiencies for linear amplifiers.
In today’s handset applications the need for very low cost and small size in power
amplifiers severely limits the usefulness of any extra design complexity to improve the
performance. Nonlinear cascading was presented as an effective and yet most simple
possible solution to address the need for higher linear efficiency at high powers while
improving the efficiency at lower powers to some extent. As discussed in chapter 2, in
the ideal linear amplifier with saturation a back-off of 3.2 dB is needed to achieve -50dBc
of ACPR in a CDMA amplifier. In chapter 3 we observed measurement results of an
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amplifier designed based on nonlinear cascading delivering -50dBc ACPR at 3.3dB
back-off. Thus, using today’s existing devices and the nonlinear cascading design
approach, the theoretically achievable linear performance at high powers can be
practically delivered and there is no room left for any additional improvement (at high
powers) through further linearization. Therefore, any further efficiency improvement at
high powers will result from improvements in devices or by the use of higher efficiency
classes of amplifiers. Although at high power, performance (i.e. efficiency while
delivering acceptable linearity) is under control relatively well, there is huge room left for
improvements in efficiency at lower powers as will be discussed in section 5.2.
As discussed in chapter 4 in order to minimize the size and cost of power amplifier
modules a very important step was to eliminate the need for off-chip passives in the
module. Along this line we observed well performing alternative implementations of
output impedance transformation networks based on on-chip capacitors and bond wires
as the inductors. Through this approach the goal of size and cost reduction was achieved.
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5.2 Future research directions
The most important needs for future research in the design of power amplifiers for
handsets must take into account today’s major issues and objectives. Size and cost
reduction in handset PAs is a very common and pressing objective. Integration of PAs for
multiple frequency bands of operation in single packages is another objective. Delivering
higher efficiencies at lower powers is a major performance related improvement that is
most desirable if it can be achieved at very minimal or no additional cost. Integration of
the PAs with the other chips in a transceiver, if possible, is another long term goal. Based
on these objectives we briefly introduce a few research directions that we believe can
have the most valuable impact on the handset power amplifier technology.
5.2.1 Integrated dynamic load adjustment
As noted in Chapter 3 efficiency for most of the more practical classes of operation falls
rather sharply when the power output is reduced from the maximum. A question is
whether we can design the amplifier in such a way that its efficiency remains close to the
efficiency when the power output is close to its maximum. The answer is yes. The
maximum efficiency is usually achieved at maximum power output because at that power
the voltage swing across the collector or drain of the device is the largest and also
potentially the current and voltage waveform overlaps are minimized. In fact the output
impedance transformation network is traditionally designed to deliver the correct
impedance at the collector or drain to do so. This is why in designing amplifiers for
different maximum power outputs, different values are used for the elements in output
matching networks. This suggests that if we can switch between different matching
networks, or switch between or tune the component values for different power outputs
while operating an amplifier, the efficiency and linearity performance can be optimized
for different the power levels.
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Figure 5-1: Power added efficiency with load adjustment
Figure 5-1 shows the hypothetical efficiency curves expected from such an amplifier
designed with three output matching configurations, one for power below 100mW, one
for the 100mW to 200mW range and one for the 200mW to 300mW range. Efficiency at
lower power outputs, such as 50mW, can be doubled using such a scheme compared to a
fixed matching scenario.
The concept of load switching or load tuning for efficiency improvement at low powers is
not new [73]. However in the known implementations so far, there are tunable elements
or switches needed in series or parallel with components in the matching network that can
not be readily integrated on the power amplifier die. Design or use of semiconductor
processes that allow such devices to be integrated on the PA chip, such as the process
suggested in [74], is one approach to solving the problem. Another direction for
exploration is to try to make those tuning or switching functions out of the same kind of
devices used in the majority of today’s handset amplifiers, HBTs to be more specific. A
potentially more valuable yet achievable approach is to use portions of the output power
device to perform the switching or tuning functions as well. That way a die size increase
can be avoided and low cost can be maintained.
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5.2.2 Sharing output devices for multiple bands
Multi-band multi-mode cell phones have been available for several years. In many
phones there is a separate PA module being used for each frequency band. Multi-band
PA modules are available for some applications, and whenever available they are the
more desirable choice. In today’s multi band PA modules there is a separate amplifier for
each frequency band when bands are widely separated. These amplifiers may be
implemented on multiple dies or may be put on a single die.
In handset power amplifier dies, the output stages are the biggest elements on the die and
they take from a third to more than half of the chip space. Therefore a major future step
in reducing the cost and size of multi-band multi-mode PAs would be the sharing of all or
portions of the output device units for different bands or modes of operation. The nature
of the sharing related problems is essentially the same as is expected in load switched
PAs. Therefore some of the solutions developed for simple on chip load switching may
very well find their ways into device sharing multi-band PAs and vice versa.
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5.2.3 CMOS PAs & breakdown
Most of today’s commercial handset power amplifiers are made of HBT devices on
InGaP processes. The primary reasons are efficiency, reliability and single-supply
operation. InGaP processes are primarily used for power amplifiers and, as a result, these
limited-use specialized processes are 5 to 6 times more expensive than the most widely
used general purpose digital or even RF CMOS processes. Implementing digital or
analog signal conditioning blocks or switches in InGaP HBT processes is not usually
possible and in the few special possible cases is not trivial. This has dictated a need for an
additional CMOS chip in some of the more recent power amplifier modules that contain
more integrated signal conditioning functions such as power control [60]. These translate
into higher cost and bigger size for the power amplifier modules.
Two primary technical limitations have held the industry from being able to effectively
implement handset power amplifiers in CMOS. One is the achievable efficiency of 1 to 3
watt amplifiers in CMOS technology, and the common perception of the achievable
efficiency. The second and perhaps even more critical problem is the low breakdown
voltages of CMOS devices. In traditional handset applications, the power amplifier is
directly connected to the battery to minimize power waste. The phones have to function
while connected to chargers and in that mode the battery voltage can easily go above
4volts. Unfortunately most of today’s CMOS processes that can potentially deliver PA
performance at GHz frequencies have a breakdown of 3 volts or lower.
There has been considerable recent work on improving performance factors such as
efficiency and gain of watt range CMOS RF power amplifiers [75-79]. Results of further
research on design and configurations of single or combinations of devices on standard
processes that can act effectively as high speed power transistors while improving the
breakdown characteristics may lead to enabling technologies for commercial CMOS
PA’s [80-83]. Any future trend in reduction of battery voltages, usage of DC-DC
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converters for the supply line of the power amplifiers, or specific breakdown avoiding
methodologies like regulators and other protecting circuitry that become active when the
battery voltage is high, e.g. when on charger, may be effective alternative ways to enable
and encourage the usage of CMOS PAs for handsets. However one has to remember that
the total additional savings resulting from using CMOS technology compared to the
InGaP processes is very small and therefore the available budget for potential additional
complexity for breakdown avoiding mechanisms is very limited.
5.2.4 Device layout
Output power devices in power amplifiers are very large and occupy substantial chip
area. They usually consist of a large number of smaller transistor cells. There is not much
systematic knowledge available about the effects of relative placement and layout of
these cells on the thermal or electrical behavior of power amplifiers. Most of the existing
designs follow the rather straightforward parallel placement of the cells in a row or
multiple rows or columns [84]. Device size usually is chosen based on rules of thumb
derived from trial and error and based on engineering judgment on the size of fingers and
cells the output transistor layout is planned. From that point on most of the effort is
focused on squeezing the performance (i.e. desired combination of gain, efficiency and
linearity) out of that device through matching, biasing and other design steps. As a result
of this design approach there is no guarantee that better performance cannot be achieved
from power amplifiers built using existing processes.
Any positioning of device cells that can lead to cooler operation of the cells, lower series
resistance of traces or lower emitter or source inductance seen per cell can lead to better
performance. Spreading the cells apart can lead to cooler operation. On the other hand
most compact layouts, such as the constructions suggested in [85 and 86], are most
desirable from the cost point of view. There is no systematic knowledge available on how
to optimize a layout based on these objectives and constraints or on whether any
reasonable improvement, e.g. better efficiency or smaller size, over existing designs can
be achieved through such an optimization.
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With a potential for increasing the efficiency and power of the devices in the same chip
area, or reducing the area for the same power and efficiencies, one newer set of proposed
candidates includes the compact layout shown in Figure 5-2.
Figure 5-2: A compact layout for a power transistor [86]
These kinds of layouts reduce the emitter inductance by directly connecting the emitter
contacts of the device to a wide sheet of metal going to ground through a connected via,
and therefore may improve gain and efficiency of the stage [86]. Since vias act to block
the heat conduction though the substrate, laying out the device around the via and leaving
the surroundings open promises better overall conduction to take the heat out of the
device and therefore promises cooler operation for the same power outputs compared to
the example of Figure 4-17 in which the vias are to some extent thermally blocking one
166
side of the device. This happens since the substrate itself is the best conductor of heat
found in a power amplifier chip. Vias are holes coated on the sides with very thin layers
of metal for electrically connecting the top and bottom metal plates through the
electrically non-conducting GaAs substrate, and are therefore a relatively nonconducting
area from the thermal point of view compared to the remainder of the substrate. While it
appears that better thermal and electrical performance in smaller die areas should be
achievable using these kinds of devices, quantification of the potential improvements is a
problem left open for further study.
In general, based on today’s knowledge the interactions among layout, thermal and
electrical issues are not effectively and easily quantified. As a result most of the efforts
on layout improvements start with speculative hypotheses that can only be checked by
experimental confirmation. Further systematic research on these interactions can lead to
design of more efficient or more compact power devices and amplifiers using existing
semiconductor processes.
5.2.5 Dynamic interaction of thermal and electrical behaviors
There is fairly limited literature available on electro-thermal modeling of power
amplifiers [87-89]. Dynamic interaction of thermal and electrical behaviors and their
effect on the performance of power amplifiers in general and power controlled PA’s in
particular, is an area that is not well understood. Results of further studies in this area
may lead to further effective size (and potentially cost) reduction or power density and
efficiency improvement in power devices.
As mentioned in section 5.2.4 any knowledge obtained through study of these
interactions can lead to more compact device layouts capable of delivering higher
efficiencies at higher power densities. In 5.2.4 we proposed a heuristic search for finding
better devices. Here the objective should be developing a system approach for modeling
power amplifiers. Such models should incorporate device cell positions, thermal
resistances and time constants, power and loss distribution, thermal and electrical ballast
167
effects, and compression curve characteristics as well as the interactions among all these
factors.
More traditional device level modeling approaches attempt to incorporate some of the
specific thermal characteristics into the transistor model and leave the rest of the
modeling job to the designers and circuit simulator. Unfortunately circuit simulators are
not fast enough to allow exploratory simulation of transistor level amplifier models with
extensive behavioral model based electro-thermal cross coupling between elements. The
need for the simulations to cover multiple thermal and power control time constants
while delivering results over fine enough time steps that allow continuity and validity of
the electrical simulations is rendering the task even more difficult.
Therefore, the objective should be obtaining a very detailed yet manageable system level
modeling method for PAs. Provided that such a method is found, fast simulation
programs can be developed to enable systematic study and optimization of layout, load
and source and bias distribution, balancing, ballasting, and thermal response in the
presence of power controlled signals.
For example such a tool can lead to early prediction of potential hot spots in a design by
any designer. This effort can also lead to answers to the following questions: What are
the best layout, ballasting, and balancing methods from a static thermal design point of
view? In a power controlled system with wide dynamic range and continuous change in
average power, how much deviation in the performance is observed compared to
predictions by static models? Is the approach good at predicting signal dependent thermal
memory effects? If so, can those simulation methods be used to optimize design of
amplifiers and pre-distorters jointly to minimize the complications due to memory
effects? Availability of such a tool should lead to PAs with better overall performance.
168
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