Download high efficiency linear power amplifiers

The main problem with such an implementation is the critical dependence of amplifier
performance on too many critical coupled bond wires. The coupling is high because of
the physical proximity that is dictated by the small size of the die’s output side. This
makes the task of tuning and optimization of the module much more complicated.
Another disadvantage of the implementation shown in Figure 4-8 is the need for three on
chip capacitors. Comparing this with the simple implementation of the single stage high
pass network in Figure 4-4 that has only one capacitor on the chip with only one critical
inductor implemented by a single bond wire or two parallel bond wires shows the
additional complexity of LPLP matching.
To reduce practical complexity of the implementation, one solution is to release the no
passives requirement to allow for only one capacitor on the module. As seen in
Figure 4-9, this approach reduces the number of bond wires and allows more space
between them and therefore reduces the couplings to a more manageable level. There is a
cost and space penalty for having the capacitor on the module but it is still much simpler
than traditional implementations requiring 6 passives or more on the module.
To Collector of the
Output Transistor
Vcc
LPLP Matching
with One Capacitor
on the Module
Out
To Ground through
Backside Vias or
Bond Wires
Chip
Module/Package
Figure 4-9: Low pass-low pass matching with one discrete capacitor
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