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GLAST LAT Project PDU/GASU MRR, February 3, 2005 GLAST Large Area Telescope: PDU & GASU Manufacturing Readiness Review (MRR) Gamma-ray Large Area Space Telescope B. Estey, G. Haller SLAC xxxx LAT Quality Engineer [email protected] (650) 926-4257 [email protected] (650) 926-8531 4.1.7 DAQ & FSW V1 1 GLAST LAT Project PDU/GASU MRR, February 3, 2005 Contents • • • Presentation I (G. Haller) – DPU & GASU Module Description – Changes since CDR – Design and Test Documentation – Engineering Module Validation Presentation II (B. Estey) – Parts, Materials & Processes – Procurement Status – Manufacturing Facilities – Manufacturing Flow Plan – Quality Assurance Plan – Configuration Management – Manufacturing Issues/Concerns Presentation III (xxxxx) – Quality Assurance Plan 4.1.7 DAQ & FSW V1 2 GLAST LAT Project PDU/GASU MRR, February 3, 2005 GLAST Large Area Telescope: Gamma-ray Large Area Space Telescope PDU & GASU MRR Part I G. Haller SLAC [email protected] (650) 926-4257 4.1.7 DAQ & FSW V1 3 GLAST LAT Project PDU/GASU MRR, February 3, 2005 LAT Electronics ACD TKR Front-End Electronics (MCM) ACD Front-End Electronics (FREE) CAL Front-End Electronics (AFEE) TKR 16 Tower Electronics Modules & Tower Power Supplies CAL Global-Trigger/ACD-EM/Signal-Distribution Unit* Spacecraft Interface Units (SIU)* – Storage Interface Board (SIB): Spacecraft interface, control & telemetry – LAT control CPU – LAT Communication Board (LCB): LAT command and data interface EPU-1 3 Event-Processor Units (EPU) (2 + 1 spare) – Event processing CPU – LAT Communication Board – SIB EPU-2 Power Dist. Unit* empty empty GASU* empty empty empty SIU* SIU* EPU-3 Power-Distribution Unit (PDU)* – Spacecraft interface, power – LAT power distribution – LAT health monitoring * Primary & Secondary Units shown in one chassis 4.1.7 DAQ & FSW V1 4 GLAST LAT Project PDU/GASU MRR, February 3, 2005 PDU & GASU Mounted on LAT Show picture of PDU and GASU on test-bed CAL TEM 4.1.7 DAQ & FSW V1 TPS 5 GLAST LAT Project PDU/GASU MRR, February 3, 2005 Power Distribution Module (PDU) • Primary and Redundant Circuits in one Enclosure – Receives Primary and Redundant 28-V from spacecraft – Each, primary and redundant DPU can select between primary and redundant spacecraft power – Filters 28V – Turns on/off 28V to 16 towers and 3 EPU’s under program control – Protects PDU and down-stream circuits from overcurrent and under-voltage situatations • Over-current via poly-switches • Under-voltage via custom circuit in each poweron branch – Receives command/clock from GASU – Digitizes voltaes/temperatures from > 150 sources • Includes temperatures from radiators, GRID used for thermal control – Reads back data to SIU via GASU – Provides PDU DAQ voltage and temperature analog data to spacecraft for monitoring 4.1.7 DAQ & FSW V1 EM PDU enclosure with primary/redundant PDU circuit cards, no coating/staking 6 GLAST LAT Project PDU/GASU MRR, February 3, 2005 GASU • Primary and Redundant Circuits in one Enclosure – Contains two types of circuit card assemblies • GASU Power Supply CCA • GASU DAQ Board CCA – GASU Power Supply • Receives 28-V supply voltages for – • Primary and redundant DAQ board, generates 3.3V and 2.5v ACD power-switch circuit for ACD FREE cards – – EM PDU enclosure with primary/redundant PDU circuit cards, no coating/staking Filtering GASU DAQ Board • Contains 9 FPGA’s • Includes Command Response Unit, Fan-out and fan-in of commanding to 16 TEMs, PDU, EPU’s, ACD • Includes Global Trigger Logic • Includes LAT Event-Builder Logic • Includes command/control/read-back for ACD sub-system • Includes power-control for ACD FREE Boards 4.1.7 DAQ & FSW V1 7 GLAST LAT Project PDU/GASU MRR, February 3, 2005 Changes since CDR • PDU – Creation/Modification of PDU FPGA code – Power-on circuit was modified to include under-voltage shut-off to protect MOS power-on switches – In-rush current limits modified to loads • GASU – Code in 9 FPGA’s were modifed/finalized and bugs fixed – ACD power-on low-frequency system clock selection added – ACD power circuits replaced with circuit to protect for overcurrent and updated ICD interface voltage/current requirements 4.1.7 DAQ & FSW V1 8 GLAST LAT Project PDU/GASU MRR, February 3, 2005 Peer Review RFA Status • Are there any? 4.1.7 DAQ & FSW V1 9 GLAST LAT Project PDU/GASU MRR, February 3, 2005 PDU (replace spread-sheet below) Tower Electronics Module LAT-DS-01481-04 LAT-PS-02615-02 LAT-SS-00288-01 LAT-TD-03415-01 LAT-TD-03875-01 LAT-TD-04097-01 LAT-TD-03831-01 LAT-DS-00554-06 LAT-DS-00555-06 LAT-DS-01026-02 LAT-DS-01031-02 LAT-DS-01646-04 LAT-DS-01649-05 LAT-DS-02583-03 LAT-DS-02588-02 LAT-DS-01650-02 LAT-TD-02230-02 LAT-TD-01782-02 LAT-TD-01785-02 LAT-DS-03895-50 LAT-DS-04376-01 LAT-DS-04452-01 LAT-DS-03894-50 LAT-DS-04377-01 LAT-DS-04453-01 LAT-TD-01880-01 LAT-TD-01881-01 LAT-DS-03582-01 LAT-DS-04354-01 4.1.7 DAQ & FSW Assembly, Tower Electronics Module Statement of Work, TEM Assy Specification, TEM Assembly Test Procedure, TEM LPT Electrical Interface Continuity and Isolation Test, TEM TEM Interface Verification Test TEM Safe to Mate Procedure TEM Box Base TEM Box Lid TEM Connector Plate TEM Connector Pin Circuit Card Assembly, TEM DAQ Printed Wire Board, TEM PWB Fab, Loading and Assembly Connector and Cable Assembly, TEM CCA Schematic Diagram, TEM CCA Bill of Materials, TEM CCA Parts Stress Analysis, TEM CCA Worst Case Design Analysis, TEM CCA Programmed FPGA, GTIC Program, GTIC FPGA Design Database for GTIC FPGA Programmed FPGA, GTIU Program, GTIU FPGA Design Database for GTIU FPGA VHDL, LAT TEM GTIC FPGA VHDL, LAT TEM GTIU FPGA Spacer, TEM Connector Washer, TEM CAL Baseplate V1 Signed Off Signed Off Signed Off Signed Off Pending Sign-Off Pending Sign-Off Pending Sign-Off Signed Off Signed Off Signed Off Signed Off Signed Off Signed Off Signed Off Signed Off Signed Off Signed Off In Review In Review Signed Off Signed Off Signed Off Signed Off Signed Off Signed Off Signed Off Signed Off Signed Off Signed Off 10 GLAST LAT Project PDU/GASU MRR, February 3, 2005 GASU 4.1.7 DAQ & FSW V1 11 GLAST LAT Project PDU/GASU MRR, February 3, 2005 ASICs • LAT-TD-01812-01 LAT-DS-01811-01 LAT-TD-01550-02 LAT-TD-01810-01 LAT-TD-02656-02 LAT-TD-01882-01 LAT-TD-02487-01 GTCC ASIC _ Part of TEM CCA LAT-DS-01646 Layout, GTCC ASIC Schematic Diagram, GTCC ASIC Specification, GTCC ASIC Test Procedure, GTCC/GCCC ASIC Screening and Test Plan, GTCC/GCCC ASIC VHDL, GTCC ASIC GTCC1 ASIC T36T Wire-bonding and Packaging Require Signed Off In sign-off Signed Off Signed Off Draft-In Work Signed Off Signed Off LAT-TD-01814-01 LAT-DS-01815-01 LAT-TD-01549-02 LAT-TD-02656-02 LAT-TD-01883-01 LAT-TD-02486-01 GCCC ASIC - Part of TEM CCA LAT-DS-01646 Layout, GCCC ASIC Schematic Diagram, GCCC ASIC Specification, GCCC ASIC Screening and Test Plan, GTCC/GCCC ASIC VHDL, GCCC ASIC GCCC1 ASIC T36T Wire-bonding and Packaging Require Signed Off in sign-off Signed Off in sign-off Signed Off Signed Off GLTC radiation and qualification – SEL and SEU ok – TID is scheduled for next week in Italy – Qualification at GSFC will start after the radiated ASICs are tested on the test-setup, so it can be shipped to GSFC. – ASICs for flight boards are being burned in and tested, full quantity required ready within one week. 4.1.7 DAQ & FSW V1 12 GLAST LAT Project PDU/GASU MRR, February 3, 2005 Engineering Model Design Validation • PDU & GASU – Tested on bench and on test-bed • Functionality and performance validated on test-bed • 16 TEM/TPS connected to EM PDU and GASU and to SIU, EPU’s and ACD FREE’s – Validated over frequency and voltage margins – GASU used in ACD G3 test-stands at GSFC – Limitations • No temperature tests performed on PDU or GASU • Flight boards checked for flight component foot-prints • PDU: flight board loaded with some flight components and tested • GASU: no flight board tested yet 4.1.7 DAQ & FSW V1 13 GLAST LAT Project PDU/GASU MRR, February 3, 2005 Issue • GLTC ASIC (GASU) – ESD sensitivity about 200V • Assembly controls to < 50V • Trigger FPGA code (GASU) – Only recently finalized and tested on test-bed • Flight FPGA’s slower – Could not burn 9 flight FPGA’s for use on non-flight board – Finite risk • Omnirel fixed-voltage regulator (PDU) – Was recalled and we are waiting for replacements, promised end of February • Transient Suppressor diode did not pass DPA (PDU) – Ordered S-class replacements which were in stock • PCB’s did not pass coupon testing (PDU) – Fabricated new batch, is at GSFC for coupon testing 4.1.7 DAQ & FSW V1 14