Download 7.6 - A 1.2Gb/s/pin Wireless Superconnect Based on Inductive Inter

ISSCC 2004 / SESSION 7 / TD: SCALING TRENDS / 7.6
7.6
A 1.2Gb/s/pin Wireless Superconnect Based on
Inductive Inter-Chip Signaling (IIS)
Daisuke Mizoguchi1, Yusmeeraz Binti Yusof1, Noriyuki Miura1,
Takayasu Sakurai2, Tadahiro Kuroda1
Keio University, Yokohama, Japan
University of Tokyo, Tokyo, Japan
1
2
Decreasing path length is a key to increasing bandwidth and
reducing dissipation in chip-to-chip communications. “System in
a Package” reduces the chip distance significantly, providing
strong motivation to develop a high-speed, low-power interface.
Three technologies are reported. These are a three-dimensional
integrated circuits (3D-ICs) with high-density vertical interconnections [1], an ac-coupled interconnection between a chip and a
multi-chip module substrate [2], and a wireless superconnect
(WSC) where two chips are stacked face-to-face and capacitive
coupled [3]. Issues in 3D-ICs are yield degradation due to difficulty in screening a known good die and cost increase caused by
additions in process complexity. In the second technology, interchip distance cannot be shorter than the chip size. WSC solves
all these limitations. Chips are tested before assembly by the
wireless interface without process addition, and they are placed
within microns of each other. Moreover, the non-contact interface
removes a highly capacitive ESD protection structure to reduce
delay, power, and area. A remaining issue is that WSC cannot be
used for connection of more than three chips for which the communication distance is several hundred microns.
In this paper, a multi-drop bus for more than three stacked chips
is presented. Figure 7.6.1 illustrates an overview of the proposed
Inductive Inter-chip Signaling (IIS). Chips are stacked face up
and inductively coupled by metal spiral inductors. Power and
clock signals are provided to them by a bonding wire or inductive
coupling. Transition of the transmitting data (Txdata) causes a
current change in a transmitter inductor (dIT/dt). It generates
small voltage signals in receiver inductors (VR) which are converted to digital signals as receiving data (Rxdata). VR is given by
VR=k√LRLT(dIT/dt)∝nRnT(dIT/dt), where k is a constant determined
by distance and feature size of inductors, The parameter nR (nT)
is number of turns of the receiver (transmitter) inductors.
Advantages of inductive coupling (L-coupling) over capacitive
coupling (C-coupling) result from device scaling. As indicated in
the above equation, VR is increased by increasing number of
turns of the inductors. Transmission gain is increased by exploiting an increased number of the metal layers, whereas in C-coupling only the topmost metal layer is utilized. Another advantage
is accrues when supply voltages are lowered in scaled devices.
Transmission power increases in current-mode signaling with Lcoupling, while it is limited by supply voltages in voltage-mode
signaling with C-coupling. Figure 7.6.2 depicts the simulated
magnetic field when three chips are stacked and operated at 1V.
In the L-coupling VR of 65mV is generated at distance of 180µm,
while in the C-coupling it is as small as 0.4mV. It is noted that
reflection or absorption is much smaller in the L-coupling, since
the permeability (µ) is about the same while permittivity (ε)
changes in semiconductor devices.
An equivalent circuit of the inductive coupling is analyzed, and
the transfer function is derived as depicted in Fig. 7.6.3(a). It is
considered that the transmitter (Tx) corresponds to the secondorder low pass filter, magnetic coupling to a differentiator, and
the receiver (Rx) to the first-order low pass filter. In total, the
inductive coupling behaves as a band pass filter. The pass band
is designed around the major frequency of Txdata. It is expected
that the inductive coupling tolerates noise from LSI circuits if its
frequency is lower than the cutoff frequency (typically some hundreds of MHz), but it is protected from ambient noise by magnetic shielding in a package. A simple yet accurate model is developed by using Biot Savart’s law to extract L and k from a layout.
Calculations using the model agree very accurately agree with
simulation using parameters extracted by FDTD (Finite
Difference Time Domain) analysis as shown in Fig. 7.6.3(b).
Circuit diagram of a transceiver is depicted in Fig. 7.6.4, and operating waveforms by SPICE simulation are shown in Fig. 7.6.5.
The transmitter is implemented by an H-bridge circuit where IT
flows for a period of delay (Ttransmit) by a delay buffer. The shorter
Ttransmit, the smaller power dissipation in Tx, but the smaller timing
margin to capture VR. For the purpose of experimental exploration, Ttransmit is set as wide as 600ps. With accurate timing control
using DLL (Delay Locked Loop), Ttransmit is shortened. In the receiver VR is detected by a sense-amplifying flip-flop (SA-FF) which is
activated by Rxclk with appropriate timing and duration. If the rising edge of Rxclk is too early or too late, Rx reads erroneously due to
noise. The duration time, Tsense, should be long enough for detecting small VR. But if it is too long, Rx operates erroneously because
of noise when the same data continues in Non Return to
Zero(NRZ) signaling. These timing constraints are investigated by
using SPICE simulation and the results are summarized in Fig.
7.6.6 which indicates the timing margin window is wide enough.
The simulation takes account of parasitic effects in layout, as well
as mismatch in device pairs. The noise in VR early in the precharge
phase in Fig. 7.6.5 is caused by voltage change in the internal
nodes of SA-FF in precharging. The noise is sufficiently diminished if the precharge (Tprecharge) period is longer than 340ps.
A test chip was designed and fabricated in a 0.35µm CMOS technology. Chip thickness is 300µm, corresponding to a stack of five
chips [4]. Two chips are stacked face up and assembled in a
package as shown in the photomicrograph in Fig. 7.6.7. Several
different sizes of transceivers are arranged in various pitches to
raise the probability of finding transceiver pairs in good alignment. Clock timing and duty ratio are changed by 70ps steps by
digital control. A 32b FIFO with Linear Feedback Shift Register
(LFSR) is implemented to measure the BER. Timing margin is
measured by changing Tsense and the difference between the rising edges of Rxclk and Txclk (∆T). The results are plotted in Fig.
7.6.6. Measured results agree very well with the simulation
results. Correct operation at Tsense of 470ps and Tprecharge of 340ps
corresponds to 1.2Gb/s data rate. Power dissipation at that rate
is 43mW in Tx and 2.5mW in Rx.
Acknowledgements:
The VLSI chip in this study has been fabricated in the chip fabrication
program of VLSI Design and Education Center(VDEC), the University of
Tokyo with the collaboration by Rohm Corporation and Toppan Printing
Corporation.
References:
[1] J. Burns et al., “Three-Dimensional Integrated Circuits for Low-Power,
High-Bandwidth Systems on a Chip,” ISSCC Dig. Tech. Papers, pp. 268269, Feb. 2001.
[2] S. Mick et al., “4Gbps High-Density AC Coupled Interconnection,” 2002
CICC, pp. 133-140.
[3] K. Kanda et al., “1.27Gb/s/pin 3mW/pin Wireless Superconnect (WSC)
Interface Scheme,” ISSCC Dig. Tech. Papers, pp. 186-187, Feb. 2003.
[4] M. Usami et al., “Powder LSI: An Ultra Small RF Identification Chip
for Individual Recognition Applications,” ISSCC Dig. Tech. Papers, pp.
398-399, Feb. 2003.
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
ISSCC 2004 / February 17, 2004 / Salon 1-6 / 11:15 AM
Metal Inductor
Tx
VR
Material Structure
Rx
Chip#3
Chip#3(Memory)
Si
SiO2
Tx
Plate or Inductor
VR
Rx
I
Tx
Rx
og
*
Ez
65mV
Si
SiO2
0.4mV
2mV
230mV
Si
60Pm
T
(b)
(a)
* 1V-peak Gausian Excitation
Chip#1
A
na
l
Chip#4
I
T
Hz
C-Coupling
Si
SiO2
Chip#2
Clock & Power
60Pm
Chip#2(Memory)
L-Coupling
(HSi=12.0, HSiO2=3.9, PSi=PSiO2=1)
Chip#1(Logic)
Figure 7.6.2: Electromagnetic field, (a) inductive coupling, (b) capacitive coupling.
Figure 7.6.1: Inductive Inter-chip Signaling (IIS).
<Receiver>
IT
LT
1
Rxdata
0
Inductor
Model
-1
RT
Duty
Controller
Tsense,
Tprecharge
RR/2
FDTD
0
CT
Rxclk
Vbias
0.5 1.0 1.5 2.0 2.5 3.0
+ VT -
Time [ns]
(a)
(b)
+ VR
FF
LR
LT
˜ jZ k ˜
1 jZ C R R R
Rout (1 Z 2 LT CT ) RT jZ CT RT Rout LT VR
VT
Rxclk
Delay Buffer
'T
jZ k LT LR IT
RR/2
Rxclk
2CR
normarized VR
+ VR -
2CR
Txdata
IT
Txclk
Delay Buffer
Clk
<Transmitter>
2
40
20
IT
Txdata
0
1
-20
-40
0
0
1
VR
0
Rxdata [V]
-200
VR [mV]
Rxclk [V]
Rxclk
200
1200
'T
600
Tprecharge=340ps
Rxclk
P P P P
P P P
Tsense
VR
P P
400
Fail when Txdata changes,
H to L, L to H
:Pass in SPICE
Rxdata
2
Txclk
P P P
800
200
3
Fail when same Txdata continues,
H to H, L to L
1000
3
2
1400
Tsense [ps]
3
Figure 7.6.4: Transceiver circuit diagram.
IT [mA]
Txdata [V]
Figure 7.6.3: Inductor design, (a) equivalent circuit and transfer function, (b) comparison of proposed inductor model to FDTD analysis.
P :Pass in measurement
0
1
100
200
300
400
500
600
'T [ps]
0
0
1
3
Time [ns]
5
Figure 7.6.5: Operating waveform (SPICE simulation).
7
8
Figure 7.6.6: Receiver timing margin (measured data and SPICE simulation).
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
Upper Chip
Bonding Wire of Upper Chip
Bonding Wire of Lower Chip
Lower Chip
Transceiver Array
0.35Pm CMOS Tech.
Triple Metals
3.3V Power Supply
Chip Thickness 300Pm
Area:
Transmitter 90PmX40Pm
Receiver 20PmX40Pm
Inductor 100PmX100Pm
Metal Inductor
Figure 7.6.7: Microphotograph of stacked test chips.
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
Metal Inductor
Tx
VR
Rx
Chip#3
Chip#3(Memory)
Tx
VR
Rx
Chip#2(Memory)
Clock & Power
Chip#2
I
Chip#4
A
na
l
og
Tx
T
I
T
Rx
Chip#1
Chip#1(Logic)
Figure 7.6.1: Inductive Inter-chip Signaling (IIS).
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
Material Structure
Si
SiO2
60Pm
Plate or Inductor
L-Coupling
Hz
65mV
Si
SiO2
C-Coupling
Ez
0.4mV
2mV
230mV
Si
SiO2
*
Si
60Pm
* 1V-peak Gausian Excitation
(a)
(b)
(HSi=12.0, HSiO2=3.9, PSi=PSiO2=1)
Figure 7.6.2: Electromagnetic field, (a) inductive coupling, (b) capacitive coupling.
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
2CR
jZ k LT LR IT
RR/2
IT
LT
1
RR/2
normarized VR
2CR
+ VR -
RT
CT
VR
VT
FDTD
0
Inductor
Model
-1
0
0.5 1.0 1.5 2.0 2.5 3.0
+ VT -
Time [ns]
(a)
(b)
LR
LT
˜ jZ k ˜
1 jZ C R R R
Rout (1 Z 2 LT CT ) RT jZ CT RT Rout LT Figure 7.6.3: Inductor design, (a) equivalent circuit and transfer function,
(b) comparison of proposed inductor model to FDTD analysis.
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
<Receiver>
Rxclk
Rxdata
Duty
Controller
Tsense,
Tprecharge
Rxclk
Rxclk
Delay Buffer
'T
Vbias
+ VR FF
Txdata
IT
Delay Buffer
<Transmitter>
Txclk
Clk
Figure 7.6.4: Transceiver circuit diagram.
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
IT
Txdata
2
40
20
0
1
-20
-40
0
IT [mA]
Txdata [V]
3
3
200
2
0
1
0
Rxdata [V]
-200
VR
3
Rxdata
2
1
0
0
1
3
Time [ns]
5
7
8
Figure 7.6.5: Operating waveform (SPICE simulation).
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
VR [mV]
Rxclk [V]
Rxclk
1400
1200
Fail when same Txdata continues,
H to H, L to L
'T
P P P
1000
Tsense [ps]
Txclk
Rxclk
P P P P
P P P
800
600
Tprecharge=340ps
Tsense
VR
P P
400
200
Fail when Txdata changes,
H to L, L to H
:Pass in SPICE
P :Pass in measurement
0
100
200
300
400
500
600
'T [ps]
Figure 7.6.6: Receiver timing margin (measured data and SPICE simulation).
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
Lower Chip
Bonding Wire of Upper Chip
Bonding Wire of Lower Chip
Upper Chip
Transceiver Array
0.35Pm CMOS Tech.
Triple Metals
3.3V Power Supply
Chip Thickness 300Pm
Area:
Transmitter 90PmX40Pm
Receiver 20PmX40Pm
Inductor 100PmX100Pm
Metal Inductor
Figure 7.6.7: Microphotograph of stacked test chips.
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE