Download Impact of Quantum Confinement Scattering on the Magnitude of

Impact of Quantum Confinement Scattering on the Magnitude of Current Fluctuations in Double
Gate MOSFETs.
C. Riddet, A. R. Brown, C. Alexander, J. R. Watling, S. Roy and A. Asenov
Device Modelling Group, Department of Electronics and Electrical Engineering, University of Glasgow
G12 8LT, Scotland, UK
E-mail: [email protected], Tel: +44 (0)141 330 4792, Fax: +44 (0)141 330 4907
Beyond the 45 nm Technology Node Ultra-thin Body (UTB) Double-Gate (DG) MOSFETs (see Fig.
1) are expected to replace their conventional counterparts due to better electrostatic integrity and
resistance to short channel effects [1,2,3]. However, as devices are scaled to silicon thicknesses below 5
nm, required for sub-10 nm channel lengths, in addition to parameter fluctuations resulting from discrete
dopants in the source and drain regions, trapped charges in the channel and LER [4], variations in the
current are introduced as a result of body thickness fluctuations due to atomic scale interface roughness.
As the interface roughness patterns are unique to each transistor there will be a variation in drive current
from device to device that will hamper their integration into modern chips. The current variations
associated with body thickness fluctuations originate from variations in the electrostatic and quantum
confinement along the channel [4] and are enhanced due to scattering from the corresponding variations
in the quantum potential illustrated in Fig.2. In the case of large self-averaging devices this additional
scattering results in a sharp reduction of the mobility for body thicknesses below 5 nm as depicted in
Fig. 3.
In this paper for the first time we study the magnitude of the current variation in UTB DG MOSFETs
considering both electrostatic and confinement variation and the corresponding scattering effects. The
study is based on ensemble Monte Carlo simulations employing a ‘frozen field’ approximation. Initially,
devices with smooth interfaces were simulated using the Glasgow ‘atomistic’ drift-diffusion simulator
[5] at low drain bias of 1 mV to comply with the conditions for using the ‘frozen field’ approximation.
The simulations implement quantum corrections by virtue of the density gradient formalism [6]. The
electron density obtained from the drift-diffusion simulation was used to initialise the particles in the
Monte Carlo module and the quantum potential corresponding to the density gradient formalism was
used to calculate the field that acts as a driving force. A close agreement between the result of the driftdiffusion and Monte Carlo simulation illustrated in Fig. 4 validates the use of the ‘frozen field’
approximation.
At the next stage we performed statistical simulations of the threshold voltage variations in an
ensemble of 200 devices, each with a different randomly generated interface roughness and body
thickness pattern. From these devices 3 were chosen, one with a high, one with a low and one with
average threshold voltage. Each one was again simulated under the same conditions as their smooth
counterpart, but with the surface roughness generated by the drift-diffusion simulator used to alter the
boundaries in the Monte Carlo module, thus implementing interface roughness and quantum
confinement variation scattering in an ab initio fashion. The variation of the effective quantum potential
in the channel for the three selected devices which corresponds to the density gradient formulation is
illustrated in Fig. 5 a,b,c. The percentage change in current between rough and smooth transistors was
then calculated for the case of drift diffusion and Monte Carlo simulations and presented in Table 1. The
results clearly indicate that the variations in calculated current are significantly larger under Monte Carlo
simulation than under drift diffusion. This confirms the important role of the scattering from the
quantum confinement variation, which is captured only in the Monte Carlo simulations.
References
[1]
[2]
[3]
[4]
[5]
[6]
D. Hisamoto, IEDM Technical Digest., pp. 429-432, 2001.
Z. Ren, R. Venugopal, S. Datta and M. Lundstrom, IEDM Technical Digest., pp. 107-110, 2001.
T. Ernst, S. Cristoloveanu, G. Ghibaudo, T. Ouisse, S. Horiguchi, Y. Ono, Y. Takahashi, and K. Murase, IEEE Trans Electron Dev,
50(3), pp. 830-838, 2003
A. R. Brown, A. Asenov and J. R. Watling, IEEE Trans. Nanotechnology, 1(4), pp. 195-200, 2002.
A. Asenov, A. R. Brown, J. H. Davis and S. Saini, IEEE Trans. CAD of Integ. Circuits and Systems, 18(11), pp. 1558-1565, 1999.
M. G. Ancona and G. J. Iafrate, Phys. Rev. B, 39, pp. 9536–9540 1989.
Fig. 1: Schematic of UTB DG MOSFET.
Fig. 2: Potential barriers resulting from thickness variations.
Fig. 3: Comparison of mobility dependence on silicon
thickness in devices with rough and smooth interfaces.
Fig. 4: Comparison of ID-VG characteristics between Monte
Carlo and Drift-Diffusion simulations for planar devices.
(a)
(b)
(c)
Fig 5: Potential plane (running from source at the left to the drain at the right), taken as a horizontal slice through the centre
of the device. Shown are planes for VG = 0.8 V, with (a) low VT, (b) average VT and (c) high VT.
Drift-Diffusion
Monte Carlo
ΔID/ID (Low VT)
2.37%
16.31%
ΔID/ID (Average VT)
9.27%
25.87%
ΔID/ID (High VT)
9.73%
30.43%
Table 1: Comparison of percentage current reduction due to thickness fluctuations in drift diffusion and Monte Carlo
for VG = 0.8 V.