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MICROELECTRONICS - CMOS Course MICROELECTRONICS Chapter: CMOS Michael E. Auer Source of figures: Jaeger/Blalock: Microelectronic Circuit Design, McGraw-Hill Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS Course Content Introduction and Milestones in Microelectronics Solid-state Electronics Solid-state Diodes and Diode Circuits Field-effect Transistors (FET) Bipolar Junction Transistors (BJT) Integrated Transistor circuits Introduction to Digital Microelectronics NMOS Logic Circuits Complemetary MOS Logic (CMOS) Bipolar Logic Circuits Semiconductor Memories Application Specific Integrated Circuits (ASIC) Microelectronic Technology Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS Chapter Content The CMOS Inverter / CMOS Inverter Dynamic Behavior / Dynamisches Verhalten CMOS NOR and NAND Gates / CMOS NOR und NAND Gatter Complex CMOS Logic Gates / Komplexe CMOS Gatter CMOS Transmission Gate / CMOS Transmission Gate Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS Chapter Content The CMOS Inverter / CMOS Inverter Dynamic Behavior / Dynamisches Verhalten CMOS NOR and NAND Gates / CMOS NOR und NAND Gatter Complex CMOS Logic Gates / Komplexe CMOS Gatter CMOS Transmission Gate / CMOS Transmission Gate Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS CMOS Technology • Complementary MOS, or CMOS, needs both PMOS and NMOS devices for the logic gates to be realized • The concept of CMOS was introduced in 1963 by Wanlass and Sah, but it did not become common until the 1980’s as NMOS microprocessors were dissipating as much as 50 W and an alternative design technique/technology was needed • Michael E.Auer CMOS dominates digital IC design today 01.05.2007 MET09 MICROELECTRONICS - CMOS MOTOROLA‘s PowerPC 620 (32/64 Bit RISC) Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS CMOS Inverter (a) (b) (c) Michael E.Auer Circuit schematic for a CMOS inverter Simplified operation model with a high input applied Simplified operation model with a low input applied 01.05.2007 MET09 MICROELECTRONICS - CMOS CMOS Inverter Technology • • Michael E.Auer The CMOS inverter consists of a PMOS device and an NMOS device, but they need to be fabricated on the same wafer To accomplish this, the technique of “n-well” implantation is needed as shown in this cross-section of a CMOS inverter 01.05.2007 MET09 MICROELECTRONICS - CMOS PMOS & NMOS Transistors Drain Currents NMOS Transistor NMOS (v GS ≥ VTN ) PMOS Linear (Triode) Region : iD = K n' Saturation Region : Michael E.Auer W⎛ v ⎞ ⎜vGS − VTN − DS ⎟v DS L⎝ 2 ⎠ K n' W 2 iD = (vGS − VTN ) (1+ λv DS ) 2 L 01.05.2007 iD = K 'p (v GS ≤ VTP ) W⎛ v ⎞ ⎜ vGS − VTP − DS ⎟v DS L⎝ 2 ⎠ K 'p W 2 iD = (vGS − VTP ) (1+ λv DS ) 2 L MET09 MICROELECTRONICS - CMOS Static Characteristics of the CMOS Inverter Michael E.Auer 01.05.2007 • The figure shows the two static states of operation with the circuit and simplified models • Notice that VH = 5V and VL = 0V, and that ID = 0A which means that there is no static power dissipation MET09 MICROELECTRONICS - CMOS CMOS Voltage Transfer Characteristics (1) • The VTC shown is for a CMOS inverter that is symmetrical (Kp = Kn) • Region 1: vO = VH vI < VTN Region 2: |vDS| ≥ |vGS – VTP| Region 4: vDS ≥ vGS – VTN Region 5: vO = VL vI > VDD – |VTP| • • • Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS CMOS Voltage Transfer Characteristics (2) Michael E.Auer 01.05.2007 • The simulation results show the varying VTC of the inverter as VDD is changed • The minimum voltage supply for CMOS technology is VDD = 2VT ln(2) V MET09 MICROELECTRONICS - CMOS Noise Margins for the CMOS Inverter Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS CMOS Inverter Layout Michael E.Auer 01.05.2007 • Two methods of laying out a CMOS inverter are shown • The PMOS transistors lie within the n-well, whereas the NMOS transistors lie in the psubstrate • Polysilicon is used to form common gate connections, and metal is used to tie the two drains together MET09 MICROELECTRONICS - CMOS CMOS Inverter Layout Michael E.Auer 01.05.2007 • Two methods of laying out a CMOS inverter are shown • The PMOS transistors lie within the n-well, whereas the NMOS transistors lie in the psubstrate • Polysilicon is used to form common gate connections, and metal is used to tie the two drains together MET09 MICROELECTRONICS - CMOS Chapter Content The CMOS Inverter / CMOS Inverter Dynamic Behavior / Dynamisches Verhalten CMOS NOR and NAND Gates / CMOS NOR und NAND Gatter Complex CMOS Logic Gates / Komplexe CMOS Gatter CMOS Transmission Gate / CMOS Transmission Gate Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS Propagation Delay Estimate (1) Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS Propagation Delay Estimate (2) τ PHL RonN τp = • Michael E.Auer ⎧⎪ ⎡ ⎛ VH − VTN = RonN C ⎨ln ⎢4⎜⎜ ⎪⎩ ⎣ ⎝ VH + VL 1 = K n (VH − VTN ) τ PHL + τ PLH 2 ⎞ ⎤ 2VTN ⎫⎪ ⎟⎟ − 1⎥ + ⎬ ⎠ ⎦ VH − VTN ⎪⎭ = τ PHL If it is assumed the inverter is “symmetrical” with (W/L)P = 2.5(W/L)N, then τPLH = τ PHL 01.05.2007 MET09 MICROELECTRONICS - CMOS Rise and Fall Times • The rise and fall times are given by the following approximate expressions: t f = 2τ PHL Symmetrical inverter: t r = 2τ PLH Michael E.Auer tf = tr 01.05.2007 MET09 MICROELECTRONICS - CMOS Static Power Dissipation Michael E.Auer • CMOS logic is considered to have no static power dissipation • This is not completely accurate since MOS transistors have leakage currents associated with the reverse-biased drainto-substrate connections as well as sub-threshold leakage current between the drain and source 01.05.2007 MET09 MICROELECTRONICS - CMOS Dynamic Power Dissipation • There are two components that add to dynamic power dissipation: 1) Capacitive load charging at a frequency f given by: PD = CV2DDf The current that occurs during switching which can be seen in the figure 2) Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS Chapter Content The CMOS Inverter / CMOS Inverter Dynamic Behavior / Dynamisches Verhalten CMOS NOR and NAND Gates / CMOS NOR und NAND Gatter Complex CMOS Logic Gates / Komplexe CMOS Gatter CMOS Transmission Gate / CMOS Transmission Gate Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS CMOS NOR Gate Y=A+B Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS CMOS NOR Gate Layout Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS CMOS NOR Gate Y=A+B+C It is possible to extend this same design technique to create multiple input NOR gates Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS CMOS NAND Gate Y=A·B Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS Multi-Input CMOS NAND Gates Y=A·B·C·D·E Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS Chapter Content The CMOS Inverter / CMOS Inverter Dynamic Behavior / Dynamisches Verhalten CMOS NOR and NAND Gates / CMOS NOR und NAND Gatter Complex CMOS Logic Gates / Komplexe CMOS Gatter CMOS Transmission Gate / CMOS Transmission Gate Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS Complex CMOS Logic Gate Design Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS Complex CMOS Logic Gate Example Y = A + B · (C + D) Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS Chapter Content The CMOS Inverter / CMOS Inverter Dynamic Behavior / Dynamisches Verhalten CMOS NOR and NAND Gates / CMOS NOR und NAND Gatter Complex CMOS Logic Gates / Komplexe CMOS Gatter CMOS Transmission Gate / CMOS Transmission Gate Michael E.Auer 01.05.2007 MET09 MICROELECTRONICS - CMOS CMOS Transmission Gate Michael E.Auer 01.05.2007 • The CMOS transmission gate (T-gate) is a useful circuits for both analog and digital applications • It acts as a switch that can operate up to VDD and down to VSS MET09 MICROELECTRONICS - CMOS CMOS Transmission Gate (2) • The main consideration that needs to be considered is the equivalent on-resistance which is given by the following expression: REQ = Michael E.Auer Ronp Ronn Ronp + Ronn 01.05.2007 MET09 MICROELECTRONICS - CMOS Summary • • • • • • Michael E.Auer In CMOS logic each gate contains both an NMOS and a PMOS switching network and every logical input is connected to at least one NMOS and one PMOS transistor. The high and low output voltage are VDD and VSS and therefore the noise margins are maximal. NAND gates, NOR gates and complex CMOS logic gates can all be designed as for NMOS circuitry. The NMOS and the PMOS switching networks are behavioral or structural dual. CMOS power dissipation is determined by the energy required to charge and discharge the load capacitance at the desired switching frequency. The static power dissipation is nearly disappearing. During switching of the CMOS gate a pulse of current occursbetween the positive and negative power supplies. This current causes an additional component of the power dissipation in CMOS gates that can be as much as 20 to 30 percent of the dissipation resulting from charging and discharging the load capacitance. A new bidirectional circuit element, the CMOS transmission gate that utilizes the parallel connection of an NMOSand a PMOS transitor was introduced. When the transmission gate is on, it provides a low-resistance connection between it‘s input and output terminals over the entire input voltage range. 01.05.2007 MET09
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