Download ADC Test Setup - inst.eecs.berkeley.edu

EE247
Lecture 15
Data Converters
• Practical aspects of converter testing
• Signal source
• Filters for signal source harmonic distortion
attenuation
• Clock generator requirements
• Evaluation board considerations
• D/A converter design
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 1
ADC Test Setup
Specs?
Signal
Generator
Evaluation
Board?
Bandpass
or
V
in
Lowpass
Filter
ADC
How to get
data across?
Data
Acquisition
PC
Clock
Generator
Specs?
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 2
Clock Generator
• Let us check if for the clock a "valuepriced" signal generator will suffice...
• No! The clock signal controls sampling
instants – which we assumed to be
precisely equi-distant in time (period T)
• Variability in T causes errors
– "Aperture Uncertainty" or "Aperture Jitter"
• How much Jitter can we tolerate?
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 3
Clock Jitter
• Sampling jitter adds an
error voltage
proportional to the
product of (tJ-t0) and the
derivative of the input
signal at the sampling
instant
• Jitter doesn’t matter
when sampling dc
signals (x’ (t0 )=0)
EECS 247 Lecture 15: Data Converters
x(t)
actual
sampling
time tJ
x’(t0)
ous
Instantane
jitter
nominal (ideal)
sampling
time t0
© 2005 H.K. Page 4
Clock Jitter
• The error voltage is
x(t)
actual
sampling
time tJ
e ~ x’(t0)(tJ – t0)
x’(t0)
error
nominal
sampling
time t0
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 5
Jitter Example
Sinusoidal input
Amplitude:
Frequency:
Jitter:
A
fx
dt
x( t ) = Asin ( 2π f x t )
x' ( t ) = 2π f x Acos ( 2π f xt )
x' ( t ) max ≤ 2π f x A
Worst case
A = AFS
e( t ) < <
dt <<
f x = fs
2
∆
2
or 2π fs
2
2
AFS
2
dt < <
AFS
2 B +1
1
2 π fs
B
Then:
e( t ) ≤ x' ( t ) max dt
e( t ) ≤ 2π f x A dt
EECS 247 Lecture 15: Data Converters
# of Bits
fs
dtmax
16
12
8
10 MHz
100 MHz
1000 MHz
0.5 ps
0.8 ps
1.2 ps
© 2005 H.K. Page 6
Law of Jitter
• The worst case looks pretty stringent …
what about less conservative statistical “average”?
• Let’s calculate the mean squared jitter error (variance)
• Assume sampling a sinusoidal signal
x(t) = Asin(2πfxt),
then
– x’(t) = 2πfxAcos(2πfxt)
– E{[x’(t)]2} = 2π2fx2A2
• Assume the jitter has variance E{(tJ-t0)2} = τ2
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 7
Law of Jitter
• If x’(t) and the jitter are independent
– E{[x’(t)(tJ-t0)]2}= E{[x’(t)]2} E{(tJ-t0)2}
• Hence, the jitter error power is
E{e2} = 2π2fx2A2τ2
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 8
Law of Jitter
DR jitter =
=
A2 / 2
2π f x2 A2τ 2
2
1
2π 2 f x2τ 2
= −20 log10 (2πf xτ )
ADC under test:
SNR=73dB
fin=37.5MHz
⇒ τ <<1ps rms !
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 9
More on Jitter
•
Once we have a good enough generator, other circuit and test
setup related issues may determine jitter, but...
•
Usually, clock jitter in the single-digit pico-second range can be
prevented by appropriate design techniques
– Separate supplies
– Separate analog and digital clocks
– Short inverter chains between clock source and destination
•
Few, if any, other analog-to-digital conversion non-idealities
have the same symptoms as sampling jitter:
– RMS noise proportional to input frequency
– RMS noise proportional to input amplitude
àIn cases where clock jitter limits the dynamic range, it’s easy
to tell, but may be difficult to fix...
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 10
Evaluation Board
• Planning begins with converter pin-out
– Example of poor pin-outà clock pin right next to a digital
output...
• Not "Black Magic", but weeks of design time
and studying
• Key aspects
– Supply/ground routing, bypass capacitors
– Coupling between signals
• Good idea to look at ADC vendor datasheets
for example layouts/schematics/application
notes
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 11
Vendor Eval Board Layout
[Analog Devices AD9235 Data Sheet]
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 12
One thing to remember...
• A converter does not just have one "input" pin
but:
– Clock
– Power Supply, Ground
– Reference Voltage
• For good practices on how to avoid issues
see e.g.:
– Analog Devices Application Note 345: "Grounding
for Low-and-High-Frequency Circuits"
– Maxim Application Note 729: "Dynamic Testing of
High-Speed ADCs, Part 2"
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 13
How to Get the Bits Off Chip?
• "Full swing" CMOS signaling works well for
fCLK<100MHz- For higher frequencies:
– Uncontrolled characteristic impedance
– High swingà higher level of spurious coupling to other
signals
– Low power efficiency
• But we want to build faster ADCs...
• Alternative to CMOS: LVDS – Low Voltage
Differential Signaling
• LVDS vs. CMOS:
– Higher speed, more power efficient at high speed
– Two pins/bit!
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 14
LVDS Outputs
Analog Devices Application Note 586: "LVDS Data Outputs for High Speed ADCs"
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 15
LVDS Outputs
Analog Devices Application Note 586: "LVDS Data Outputs for High Speed ADCs"
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 16
Data Acquisition
• Several options:
– Logic analyzer with PC interface
– FIFO board, interface to PC DAQ card
– Vendor kit, simple interface to printer port:
[Analog Devices, High-Speed ADC FIFO Evaluation Kit]
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 17
Post-Processing
•
•
•
•
LabView (DAQ Software Toolbox)
Matlab
Some vendors provide example source code
E.g. Maxim Application Note 1819: "Selecting
the Optimum Test Tones and Test Equipment
for Successful High-Speed ADC Sine Wave
Testing"
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 18
Example: Complete ADC Test Setup
[Maxim Application Note 729: "Dynamic Testing of High-Speed ADCs, Part 2]
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 19
Debugging
• State-of-the-art converters almost always yield
surprises in silicon
– If models anticipate everything, the application probably isn’t
state-of-the-art
• Analog designers and mixed-signal architects at
times invent new circuits while measuring in the lab
• How do we debug converters?
– Start with a simple time domain test. Does the captured
digital waveform look like a sine wave?
– Begin your DFT/INL signature analysis by scaling down
sampling frequencies and signal input frequencies together
– If you can’t explain performance with essentially infinite
settling times, don’t add dynamic errors to the mix
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 20
Debugging
• Typical problems come from nonidealities never built into your "model"
– E.g. half-circuit models for fully-differential
circuits inherently can’t explain some types
of differential-symmetry errors
• You can’t afford to rediscover old nonidealities in new silicon
– Talking to veterans early in the modeling
phase can be important
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 21
Debugging
• Design teams usually track down and fix single-cause
problems quickly
• Problems due to circuit interactions are much more
difficult to debug, try to avoid by good design/layout
• Interaction examples:
– Digital activity-dependent clock jitter
• S/(N+D) degradation only happens when large
amplitude, high frequency analog inputs coincide with the
offending digital activity
– Distortion cancellation
• Nonlinear phenomena don’t obey superposition
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 22
Debugging
SFDR vs. Input Frequency (fclk =75MHz)
85
[dB]
80
75
70
SFDR
65
60
0
10
20
30
40
50
60
70
fin [MHz]
• Cancellation of Nonlinearities?
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 23
Debugging
• Never assume all of your data is good
– One bad data set can “rule out” the correct
explanation, leading you astray forever
• "Compare measurements to themselves“
• But, noise is a random variable, and the noise
power in 1000 time samples will vary from
DFT to DFT
• How big an effect is this?
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 24
Debugging
• Can show that:
– Variation of noise in 1000 samples yields a
standard deviation in SNR of 0.2dB
– This means that 68.3% of all DFTs will produce
SNRs within 0.2dB of the average
– 99.7% of 1000 point DFTs yield SNRs within
±0.6dB of the average
• If you’re seeing ADC noise variation of
greater than ±0.6dB in the lab, some sort of
interference is usually the culprit
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 25
Testing & Debugging
• Always try to use two independent measurement
methods to verify important results
– Correlate INL & SFDR, DNL & SNR
• Comparing time domain and frequency domain views
of the same measurement is good practice
– e.g. DNL & SNR
Debugging and testing of state-of-the-art circuitry
à Non-trivial
à Need to plan ahead
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 26
D/A Converters
•
D/A architecture examples
– Unit element
– Binary weighted
• Static performance
– Component matching
– Architectures
• Unit element
• Binary weighted
• Segmented
– Dynamic element matching
• Dynamic performance
– Glitches
• DAC examples
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 27
D/A Converters
• Comprises voltage, charge, or
current based elements
• Examples for above three
categories:
– Resistor string
– Charge redistribution
– Current source type
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 28
R-String DAC
Vref
R
R
2B Rs, all Rs equal
R
R
à Generates 2B
equally spaced
voltage sources
R
R
R
R
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 29
R-String DAC
Example
Vref
Example:
Input code 101
à Vout= 5Vref/8
τsettling
=
=(3R||5R) x C
=0.23 x 8RC
EECS 247 Lecture 15: Data Converters
7Vref/8
6Vref/8
5Vref/8
4Vref/8
3Vref/8
Vout =
5Vref /8
C
2Vref/8
Vref/8
R
© 2005 H.K. Page 30
R-String DAC
•
Advantages:
Vref
– Simple, fast for <8-10bits
– Inherently monotonic
– Compatible with purely digital
technologies
•
Disadvantages:
– 2B resistors & ~22B switches for
B bits à High element count &
large area for B >10bits
– High settling time for B > 10:
τmax = 0.25 x 2B RC
C
Ref:
M. Pelgrom, “A 10-b 50-MHz CMOS D/A Converter with 75-W Buffer,” JSSC, Dec. 1990, pp. 1347
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 31
R-String DAC
Including Interpolation
Resistor string DAC
+ Resistor string interpolator
increases resolution w/o drastic
increase in complexity
e.g. 6bit DACà 3bit +3bit
Vref
Vout
Considerations:
q Interpolation string loading of main
R-string
q Large R values à less loading but
lower speed
q Can use buffers
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 32
R-String DAC
Including Interpolation
Vref
Use buffers, issues:
à Buffer offset
à Speed
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 33
Serial Charge Redistribution DAC
•
•
Nominally C1=C2
Operation sequence:
– Discharge C1 & C2à S3&
S4 closed
– For each bit in succession
beginning with LSB, b1:
• S1 open- if bi=1 C1
precharge to VREF if bi=0
discharged to GND
• S2 & S3 & S4 open- S1
closed- Charge sharing C1
& C2
à ½ of precharge on C1
+½ of charge
previously stored on
C2à C2
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 34
Serial Charge Redistribution DAC
Example: Input Code 101
b1 b2
•
•
•
b3
Example input code 101à output (1/8 +0/8 +4/8 )VREF =5/8 VREF
Very small area
N redistribution cycles for N-bit conversion à quite slow
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 35
Parallel Charge Scaling DAC
reset
Vout
2(B-1) C
8C
4C
2C
C
bB-1 (msb)
b3
b2
b1
b0 (lsb)
C
Vref
B −1
Vout =
∑ bi 2 i C
i =0
2B C
Vref
• E.g. “Binary weighted”
• B+1 capacitors & switches (Cs built of unit elements à 2B cap units)
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 36
Charge Scaling DAC
Example: 4Bit DAC- Input Code 1011
a- Reset phase
reset
8C
4C
2C
b3
b2
b1
b- Charge phase
Vout
C
C
8C
4C
b3
b2
Vout
2C
C
b1
b0 (lsb)
b0 (lsb)
C
Vref
Vout =
Vref
20 C + 21 C + 23C
11
Vref = Vref
24 C
16
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 37
Charge Scaling DAC
reset
CP
Vout
2(B-1) C
8C
4C
2C
C
C
B −1
∑b 2 C
i
bB-1 (msb)
b3
b2
b1
b0 (lsb)
Vout =
i =0
i
2 B C + CP
Vref
Vref
•
•
•
Monotonicity depends on element matching
Sensitive to parasitic capacitor @ outputà gain error
Large area of caps for high DAC resolution (10bit DAC ratio 1:512)
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 38
Charge Scaling DAC
CI
reset
CP
2(B-1) C
8C
4C
2C
C
bB-1 (msb)
b3
b2
b1
b0 (lsb)
Vout
+
Vref
B −1
Vout =
•
bi 2i C
∑
i =0
CI
Vref
Opamp helps eliminate the parasitic capacitor effect
– Issue: opamp offset & speed
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 39
Charge Scaling DAC
Utilizing Split Array
reset
8/7C
+
C
C
2C
4C
b0
b1
b2
C
2C
4C
b3
b4
b5
Vout
-
Vref
Cs e r i e s =
•
∑ a l l LSB array C
∑ all MSB array C
C
Split arrayà reduce the total area of the capacitors required
– E.g. 10bit regular binary array requires 513 unit Cs while split array (5&5)
needs 64 unit Cs
– Issue: Sensitive to parasitic C
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 40
Resistor Ladder (MSB) & Binary Weighted
Charge Scaling (LSB) Segmented DAC
•
Example: 12bit
DAC
–
–
6-bit MSB
DACà R string
6-bit LSB DAC
à binary
weighted
charge
redistribution
Complexity much
lower than full R
•
reset
...
...
...
.
Vout
32 C
16C
8C
b5
b4
b3
4C
2C
b2
b1
C
C
b0
string
– Full R stringà
4096 resistors
– Segmented à
64 R + 7 Cs
(64 unit caps)
6bit
resistor
ladder
6-bit
binary weighted
charge redistribution DAC
Switch
Network
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 41
Current Source DAC
Unit Element
……………
Iref
……………
•
•
•
•
•
Iout
Iref
Iref
Iref
“Unit elements ”
Monotonicity does not depend on element matching
2B-1 current sources & switches
Suited for both MOS and BJT techologies
Output resistance of current source à gain error
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 42
Current Source DAC
Unit Element
R
……………
Vout
+
Iref
……………
•
Iref
Iref
Iref
Output resistance of current source à gain error problem
à Use transresistance amplifier- output of current source held
@ virtual ground – error due to current source output
resistance elliminated
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 43
Current Source DAC
Binary Weighted
……………
2B-1 Iref
……………
Iout
4 Iref
2Iref
Iref
• “Binary weighted”
• Monotonicity depends on element matching
• B current sources & switches (2B-1 unit elements)
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 44
Static DAC INL / DNL Errors
• Component matching
• Systematic errors
–
–
–
–
Contact resistance
Edge effects in capacitor arrays
Process gradient
Finite current source output resistance
• Random errors
– Lithography
– Often Gaussian distribution (central limit theorem)
*Ref: C. Conroy et al, “Statistical Design Techniques for D/A Converters,” JSSC Aug. 1989,
pp. 1118-28.
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 45
Probability density p(x)
Gaussian Distribution
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
( x−µ )
2
p( x ) =
1
2πσ
−
e
2σ
-3
-2
-1
0
1
2
3
x /σ
2
where standard d e v i a t i o n : σ = E( X 2 ) − µ 2
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 46
P (− X ≤ x ≤ + X ) =
=
1
+X −
2π
−X
∫
e
x2
2 dx
Probability density
p(x)
Yield
P(-X ≤ x ≤ +X)
 X 
= erf 

 2
0.4
0.3
0.2
0.1
0
1
0.8
0.6
0.4
0.2
0
95.4
68.3
38.3
0
0.5
1
1.5
2
2.5
3
X
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 47
Yield
X/σ
0.2000
0.4000
0.6000
0.8000
1.0000
1.2000
1.4000
1.6000
1.8000
2.0000
P(-X ≤ x ≤ X) [%]
15.8519
31.0843
45.1494
57.6289
68.2689
76.9861
83.8487
89.0401
92.8139
95.4500
EECS 247 Lecture 15: Data Converters
X/σ
2.2000
2.4000
2.6000
2.8000
3.0000
3.2000
3.4000
3.6000
3.8000
4.0000
P(-X ≤ x ≤ X) [%]
97.2193
98.3605
99.0678
99.4890
99.7300
99.8626
99.9326
99.9682
99.9855
99.9937
© 2005 H.K. Page 48
Example
• Measurements show that the offset voltage of
a batch of operational amplifiers follows a
Gaussian distribution with σ = 2mV and µ = 0.
• Fraction of opamps with |Vos| < X = 6mV:
– X/σ = 3 à 99.73 % yield (we’d still test before
shipping!)
• Fraction of opamps with |Vos| < X = 400µV:
– X/σ = 0.2 à 15.85 % yield
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 49
Component Mismatch
Example: Two side-by-side
Resistors
No. of resistors
400
300
∆R
200
R
100
Large # of devices
measured
0
996 1000 1004 1008 1012
& curved à typically if
988 992
sample size large shape
R[ Ω ]
is Gaussian
E.g. Let us assume in this example 1000 Rs measured
& 68.5% within +-4OHM or +-0.4% of average
à 1σ for resistorsà 0.4%
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 50
Component Mismatch
Probability density p(x)
Two side-by-side
Resistors
R=
0.4
R1 + R2
2
0.35
0.3
R
∆R
0.2
R
0.15
0.1
0.05
0
−3σ −2σ
dR = R1 − R2
σ d2R ∝
0.25
−σ
0
σ
2σ
For typical technologies & geometries
1σ for resistorsà 0.02 το 5%
1
Area
3σ
dR
R
In the case of resistors σ is a function of area
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 51
DNL Unit Element DAC
E.g. Resistor string DAC:
Vref
∆ = Rn o m I ref
Iref
∆i = Ri I ref
DNLi =
=
∆ n o m − ∆i
∆nom
Ri − R
nom
Rn o m
=
dRnom
Rnom
≈
d Rn o m
Ri
∆i = Ri I ref
σ DNL = σ dRi
Ri
DNL of unit element DAC is
independent of resolution!
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 52
DNL Unit Element DAC
E.g. Resistor string DAC:
Example:
If σdR/R = 0.4%, what
DNL spec goes into
the datasheet so that
99.9% of all converters
meet the spec?
σ DNL = σ d R
i
Ri
DNL of unit element DAC is independent of resolution!
Note similar results for all unit-element based DACs
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 53
Yield
X/σ
0.2000
0.4000
0.6000
0.8000
1.0000
1.2000
1.4000
1.6000
1.8000
2.0000
P(-X ≤ x ≤ X) [%]
15.8519
31.0843
45.1494
57.6289
68.2689
76.9861
83.8487
89.0401
92.8139
95.4500
EECS 247 Lecture 15: Data Converters
X/σ
2.2000
2.4000
2.6000
2.8000
3.0000
3.2000
3.4000
3.6000
3.8000
4.0000
P(-X ≤ x ≤ X) [%]
97.2193
98.3605
99.0678
99.4890
99.7300
99.8626
99.9326
99.9682
99.9855
99.9937
© 2005 H.K. Page 54
DNL Unit Element DAC
Example:
If σdR/R = 0.4%, what DNL spec
goes into the datasheet so that
99.9% of all converters meet
the spec?
E.g. Resistor string DAC:
σ DNL = σ d R
i
Ri
Answer:
From table: for 99.9%
à X/σ = 3.3
σDNL = σdR/R = 0.4%
3.3 σDNL = 1.3%
àDNL= +/- 0.013 LSB
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 55
DAC INL Analysis
Output [LSB]
N
B
E
n
A
n
N=2B-1
Input [LSB]
A=n-E
Ideal
n
B=N-n+E
N-n
Variance
n.σε2
(N-n).σε2
E = A-n
r =n/N
N=A+B
= A-r(A+B)
= A (1-r) -B.r
à Variance of E:
σE2 =(1-r)2 .σΑ2 + r 2 .σB2
=N.r .(1-r).σε2
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 56
DAC INL
n

σ E 2 = n  1 −  ×σ ε 2
 N
To find m a x . v a r i a n c e :
→ n=N/2
•
dσ E 2
dn
=0
Error is maximum at mid-scale (N/2):
σ INL =
1
2B − 1 σ ε
2
with N = 2 B − 1
•
INL depends on DAC resolution and element matching σε
•
While σDNL = σε
Ref: Kuboki et al, TCAS, 6/1982
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 57
Untrimmed DAC INL
Example:
σ INL ≅
1 B
2 −1 σε
2
σ 
B ≅ 2 + 2 log2  INL 
 σε 
EECS 247 Lecture 15: Data Converters
Assume the following requirement:
σINL = 0.1 LSB
Then:
σε = 1%
σε = 0.5%
σε = 0.2%
σε = 0.1%
à
à
à
à
B = 8.6
B = 10.6
B = 13.3
B = 15.3
© 2005 H.K. Page 58
Simulation Example
12 Bit converter DNL and INL
DNL [LSB]
2
1
-0.04 / +0.03 LSB
σε
B
0
-1
500
1000
1500 2000 2500 3000 3500 4000
bin
1
Computed INL:
σINL = 0.3 LSB
(midscale)
2
INL LSB]
= 1%
= 12
-0.2 / +0.8 LSB
0
-1
500
1000
1500 2000 2500 3000 3500 4000
bin
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 59
INL for Binary Weighted DAC
•
INL same as for unit element
DAC
•
DNL depends on transition
Iout
– Example:
0 to 1 àσDNL2 = σ(dΙ/Ι) 2
1 to 2 à σDNL2 = 3σ(dΙ/Ι) 2
•
Consider MSB transition:
0111 … à 1000 …
EECS 247 Lecture 15: Data Converters
2B-1 Iref
……………
4 Iref
2Iref
Iref
© 2005 H.K. Page 60
MOS Device Matching Effects
Id =
Id1 + Id 2
2
Id1
dId Id1 − Id 2
=
Id
Id
Id2
dId
dW L
dVth
=
+
W
Id
VGS −Vth
L
• Current matching depends on:
- Device W/L ratio matching
à Larger device area less mismatch effect
- Threshold voltage matching
à Larger gate-overdrive less threshold voltage mismatch effect
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 61
Current-Switched DACs in CMOS
Iout
Iref
d Id
Id
=
dW L
W
L
+
Switch Array
d Vth
……
VG S −Vth
256
•Advantages:
Can be very fast
Small area for < 9-10bits
128
64 ………..…..1
Example: 8bit Binary Weighted
•Disadvantages:
Accuracy depends on device W/L & Vth matching
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 62
Binary Weighted DAC DNL
•
Worst-case transition occurs at
mid-scale:
15
(
)
(
)
σDNL2/ σε2
2
σ DNL
= 2B−1 − 1 σε2 + 2B−1 σε2
10
144244
3
14243
0111...
1000...
≅ 2Bσε2
σ DNLmax = 2B / 2σε
5
σ I N Lmax ≅
•
0
2
4
6
8
10
12
14
1
2
2B − 1 σ ε ≅
1
2
σ DNLmax
Example:
B = 12, σε = 1%
DAC input code
EECS 247 Lecture 15: Data Converters
à σDNL = 0.64 LSB
à σINL = 0.32 LSB
© 2005 H.K. Page 63
“Another” Random Run …
DNL and INL of 12 Bit converter
DNL [LSB]
2
-1 / +0.1 LSB,
1
Now (by chance) worst
DNL is mid-scale.
0
-1
-2
500 1000 1500 2000 2500 3000 3500 4000
bin
Statistical result!
INL [LSB]
2
-0.8 / +0.8 LSB
1
0
-1
500 1000 1500 2000 2500 3000 3500 4000
bin
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 64
Unit Element versus Binary Weighted DAC
Unit Element DAC
Binary Weighted DAC
σ D N L = σε
σ DNL ≅ 2
B
2σ
σ INL ≅ 2
B
2 −1
σ INL ≅ 2
B
2 −1 σ
ε
ε = 2σ INL
σε
Number of switched elements:
S=B
S = 2B
Key point: Significant difference in performance and complexity!
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 65
Unit Element versus Binary Weighted DAC
Example: B=10
Unit Element DAC
Binary Weighted DAC
σ DNL = σ ε
σ DNL ≅ 2 2σ ε = 3 2σ ε
σ INL ≅ 2
B
2
B
−1
σ ε = 16σ ε
σ INL ≅ 2
B
2
−1
σ ε = 16σ ε
Number of switched elements:
S = 2B = 1024
S = B = 10
Significant difference in performance and complexity!
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 66
DAC INL/DNL Summary
• DAC architecture has significant impact on DNL
• INL is independent of DAC architecture and requires
element matching commensurate with overall DAC
precision
• Results are for uncorrelated random element
variations
• Systematic errors and correlations are usually also
important
Ref: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string A/D
converters. IEEE Transactions on Circuits and Systems, vol.CAS-29, (no.6), June 1982. p.383-9.
EECS 247 Lecture 15: Data Converters
© 2005 H.K. Page 67